Assessment of ABET Categories a) Through k) for Core ...unh.edu/ece/Department/ABET/Response to ABET Request for More Information about...Use of Multisim for a digital design problem

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Assessment of ABET Categories a) Through k) for Core Courses in the ECE Program

Overview

This document provides assessments, including examples as to how those assessments were made, for all ECE core courses with respect to the ABET categories they satisfy. The infor-mation given here was provided by the faculty member who last taught the course, using as-sessment techniques deemed appropriate by that faculty member. That information has been aggregated by the department Chair, and this assessment process is to be performed every year which will produce a new assessment document every year. The summary table given below is an adaptation of Table 4-1 in the ABET Self-Study Report and it provides an aggregate of the assessments performed in each core course. A blank for a par-ticular category indicates that the category is not associated with that course, and a “-“ indi-cates that the category is covered in the course although it is not assessed explicitly. There is a significant variation in the assessment information provided by individual faculty members; some have chosen to provide a selected exam or homework problem while others provide complete lab reports written by students. It is expected that those assessments will converge on a format that is more consistent and concise as this process continues. It is also ex-pected that the ABET categories associated with the courses will change over time. This document is maintained online so that it can be readily referenced by ECE faculty to facili-tate program review and/or so that they can get a clear sense of what was covered in courses related to the ones they teach.

Contents Overview ......................................................................................................................................... 1

ABET Assessment Summary for AY17-18 .................................................................................... 3

ABET Attributes for ECE 401: Perspectives in ECE ..................................................................... 4

ABET Attributes for ECE 541: Circuits 1 ...................................................................................... 8

ABET Attributes for ECE 548: Circuits II ................................................................................... 12

ABET Attributes for ECE 543: Digital Circuits ........................................................................... 15

ABET Attributes for ECE 562: Digital Circuits ........................................................................... 17

ABET Attributes for ECE 602: Engineering Analysis ................................................................. 19

ABET Attributes for ECE 603: Electromagnetics ........................................................................ 21

ABET Attributes for ECE 617: Junior Lab I ................................................................................ 27

http://www.unh.edu/ece/Department/ABET/Response%20to%20ABET%20Request%20for%20More%20Information%20about%20Assessments-%20May%202018.pdf

2

ABET Attributes for ECE 618: Junior Lab II ............................................................................... 59

ABET Attributes for ECE 633: Signals & Systems I ................................................................... 85

ABET Attributes for ECE 634: Signals & Systems II .................................................................. 90

ABET Attributes for ECE 647: Random Processes ...................................................................... 97

ABET Attributes for ECE 651: Electronic Design II ................................................................. 108

ABET Attributes for ECE 791: Senior Project I ......................................................................... 114

ABET Attributes for ECE 792: Senior Project II ....................................................................... 116

3

ABET Assessment Summary for AY17-18

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Course a b c d e f g h i J k

ECE401 Messner 75 80 80 80 80 88 100 100 85 85

ECE541 Smith 90 90 90 0 90 - 90

ECE543 Pah-

levanzadeh 65 60 60 75 75 65

ECE548 Jenney 89 - 89 100 93 - - 75

ECE562 Pah-

levanzadeh 75 70 45 75 90 88

ECE602 Carter 80 80 - 80

ECE603 Kirsch 85 30 - - - 75

ECE617 Smith 96 96 96 0 96 - 96 100

ECE618 Smith 96 96 96 0 96 - 96 96

ECE633 Yoon 90 88 85 85

ECE634 Smith 60 60 60 - 95

ECE647 Smith 85 95 - 95

ECE651 Song 81 - 72 97 - 83 94

ECE791 Messner 87 87 87 87 87 100 100 87 87 87 87

ECE792 Messner 90 90 90 90 90 100 100 90 90 90 90

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ABET Attributes for ECE 401: Perspectives in ECE

ABET Category Example %

Meeting Criteria

a An ability to apply knowledge of mathematics, science, and en-gineering

Lecture example problems and vari-ous homework problems (see typical problems below)

75%

b An ability to design and conduct experiments, as well as to ana-lyze and interpret data

c An ability to design a system, component, or process.

Project Design Team efforts to design from a spec.

80%

d An ability to function on multi-disciplinary teams

Team effort for Project Design 80%

e Identify, formulate, and solve engineering problems

Team project and individual project efforts

80%

f Professional and ethical respon-sibility

Lecture sequence on both profes-sional responsibility and ethics. Writ-ten responses by students to an ethi-cal dilemma question

80%

g An ability to communicate effec-tively

Project Teams must submit detailed written documents on their design Individual projects must present their efforts in a poster session and oral presentation

88%

h

The broad education necessary to understand the impact of en-gineering solutions in a global and societal context

This is covered in many ways during guest lecturers from both industry and academics

100%

i A recognition of the need for, and an ability to engage in life-long learning

Covered in class lectures. Class has mandatory attendance

100%

5

j A knowledge of contemporary issues

Classroom discussion of technology in use that have potential ethical im-pact. Example: Drone imagery of pri-vate property from above

85%

k

An ability to use the technique, skills, and modern engineering tools necessary for engineering practice

Use of Multisim for a digital design problem. Use of Excel as an engi-neering calculating tool. Use of Matlab for plotting of functions

85%

6

7

8

ABET Attributes for ECE 541: Circuits 1


Meeting Criteria


See attached Exam#3 problem 1. 90


See attached Lab#1. Students use measurements to verify Kirchhoff’s Voltage and Current Laws

90


Introductory circuits course so major-ity of instruction was based on analy-sis without much design. Majority of homework assignments contained at least one design problem. For exam-ple, see attached problem 3.19 from our text.

90


Not applicable. Students work individ-ually on all ECE541 labs.

0


See attached Exam#3 problem 2. 90



h




Discussed but not assessed. N/A

9

k


All Prelab assignments require use of NI Multisim (See attached Lab#1)

90

10

University of New Hampshire Department of Electrical and Computer Engineering

Reference: Nilsson and Riedel, Chapters 1 and 2 Introduction This laboratory exercise will refresh your memory from ECE 401 about some of the basic instru-ments that will be used throughout the semester. This lab will be an introduction to the use of the Digital Multimeter (DMM) and DC power supplies. It is important to understand how each instrument functions, what range(s) of voltage and current over which it was designed to oper-ate, the basic accuracy of the instrument, and how to properly and safely use the instrument. The material in this laboratory exercise will include the basics of each instrument while more advanced applications will be covered in future laboratory exercises. The instruments covered in this laboratory exercise are the DC power supply and DMM. During the first section of the laboratory exercise the instructor will discuss each instrument. Please take notes and ask questions if you do not understand any material being presented. In the second section of this exercise you will be asked to perform basic circuit measurements and report on what you recorded. It is important to understand how to properly connect elec-tronic instruments to a circuit, make basic measurements, and understand how the instrument might affect the measurement being made. Please include proper units in your measurements and answers where appropriate. Objectives

To introduce the student to the resistor color code

To introduce the student to basic resistive circuits

To introduce the student to the digital multimeter (DMM) and the variable DC power supply

To introduce the student to Ohm’s Law, Kirchoff’s Voltage Law, and Kirchoff’s Current Law

To introduce the student to resistive sensors

Pre-Lab Procedure

You are to simulate the circuit in part 4 of the In-Lab procedure (Figure 3) using Multisim.

Using the DMM, measure voltages V1, V2, V3 and currents i1, i2, i3.

ECE541 Laboratory#1 Weeks of 9/11/17 and

9/18/17

Introduction to DC Resistive Circuits

11

V1: __________________, V2: __________________, V3: __________________ i1: __________________, i2: __________________, i3: __________________

In-Lab Procedure

1. Resistance Measurements

Review the resistor color code in figure 4 at end of lab handout.

Using the DMM (ohm measurement mode) measure the resistance of the following re-sistors:

1.8 kΩ:________________ 2.7 kΩ:_________________ 3.3 kΩ:_________________

Do your measurements make sense based upon the color code?

Are the resistors within stated tolerance (5% or 10%)? Explain.

Construct the following resistor circuits and measure the equivalent resistance. Com-pare the measured values with the calculated theoretical values.

Measured Value: __________________ Theoretical Value: _________________

2.7 kΩ

3.3 kΩ

1.8 kΩ

Req

12

Measured Value: __________________ Theoretical Value: _________________

2. Voltage Measurements

Connect the DC voltmeter and two resistors as shown in the circuit in Figure 1

Figure 1

Using the DMM adjust the DC power supply voltage (Vs) to the indicated value.

Using the DMM measure and record the DC voltages V1 and V2: V1: ___________________ V2: _____________________

V1

+

- V

S = 10 V

i

R1= 10 kΩ

R2= 5 kΩ V

2

+

-

2.7 kΩ 3.3 kΩ 1.8 kΩ Req

13

Reverse the leads of the DMM then measure and record the DC voltages V1 and V2: V1: ___________________ V2: _____________________

What effect did reversing the leads of the DMM have on voltage measurements?

3. Current Measurements

Using the DMM (see Figure 2) measure and record the current i. Note the current should equal 10 V / (Sum of R1 and R2). i: __________________________

Figure 2

Show the TA how you measured the above current. TA’s Signature:______________.

Reverse the leads of the DMM then measure and record the current i: i: ________________________

V1

+

- V

S = 10 V

i

R1= 10 kΩ

R2= 5 kΩ V

2

+

-

A

14

Place the ammeter between the 10K and 5K resistors and measure the current: i: ________________________

Comment on the current measurement taken between the DC power supply and the 10K resistor; and the current measurement taken between the two resistors. What effect did reversing the leads of the DMM have on current measurements?

Calculate the power related to the DC power supply and the two resistors. Which ele-ments absorb power and which elements deliver power? Is the conservation of energy principle (i.e. the net power in the system) satisfied?

4. Kirchhoff’s Voltage and Current Laws

Build a circuit as shown in Figure 3 below.

Figure 3

Using the DMM, measure the voltages V1, V2, V3.

V1: __________________, V2: __________________, V3: __________________

Use the measured voltages above and Ohm’s Law to calculate the currents i1, i2, i3.

i1: __________________, i2: __________________, i3: __________________

V2

+

-

VS = 10 V 10 kΩ V

3

+

-

5 kΩ

V1 + -

2 kΩ

i1

i3

i2

a

b

15

Verify KCL by applying the law at node a. Set up the equation and use your experimental

measurements.

Verify KVL by applying the law around loop b. Set up the equation and use your experi-

mental measurements.

5. Resistive Sensors

Identify the variable resistance force sensor on your workbench. Force sensitive resis-tors (FSR) exhibit a decrease in resistance with an increase in force to the active surface. Attach the FSR to the DMM (ohmmeter) and measure its resistance. FSR resistance without force:___________________.

Change the resistance of the FSR by pressing on the active surface. New FSR resistance :__________________.

After finishing the lab, clean up your workstation, turn off all equipment, place resistors

and cable back to their original locations. Enter name/date below and obtain TA signa-

ture.

16

Example:

R = 10 x 102 ± 5% = 1000 Ω (± 5%) = 1 k Ω (± 5%) Figure 4 Resistor Color Code1 0 10

2 ± 5%

0

1

2

3

4

5

6

7

8

9

10

11

12

ABET Attributes for ECE 548: Circuits II


Meeting Criteria


Final Exam Problem #1 89





All students were required to work in groups in the labs

100





This category was not assessed ex-plicitly

-

h




Students were not assessed in this category

-

k


All students passing the lab portion of this course learned to use basic lab equipment.

13

Final Exam Problems in ECE548

1. (10 pts) For the circuit shown on the right, the parameters are

R = 600Ω, C = 0.33µF. Find:

(a) the transfer function H(s).

(b) the cut-off frequency 𝜔𝑐 (in rad/s) and 𝑓𝑐 (in Hz).

(c) the value of |𝐻(𝑗𝜔)| and ∠𝐻(𝑗𝜔) when 𝑓 = 0.3𝑓𝑐.

(d) If 𝑉𝑖𝑛(𝑡) = 10 cos(3000𝑡), find 𝑉𝑜𝑢𝑡(𝑡).

2. (10 pts) For the following circuit, let R = 500 Ω, L =

400 mH, C = 0.5 µF. Find:

(a) the cut-off frequencies 𝑓𝑐1, 𝑓𝑐2 (in Hz).

(b) center frequency 𝑓𝑜 (in Hz).

(c) Plot |𝐻(𝑗𝜔)| vs. f (Hz). Indicate the cut-off frequen-

cies and the center frequency on the plot.

3. (10 pts) The circuit below contains an ideal transformer with a turns ratio of 5:1. Find the

transformer voltages v1(t), v2(t), and the currents i1(t) and i2(t).

C R V

out (t)

+

-

Vin

(t)

+

-

Figure 1

Vin

(t) VO(t)

R

C

L

+

−

+

−

|H(jω)| ∠H(jω)

14

4. (5 pts) The formula which describes the relationship between current, I, and voltage, V,

for a resistor is V = I * R or Ohm’s Law. What is the formula which describes the rela-

tionship between current, I, and voltage, V, for an Inductor with inductance of L?

15

ABET Attributes for ECE 543: Digital Circuits


Meeting Criteria


Add the following decimal numbers in BCD.

65%


Design a 4-bit BCD Adder. The given block diagram below is a 4-bit BCD adder and is consisted of a combinational logic circuit (the blank box) and two 4-bit BFAs. The top 4-bit BFA adds two BCD numbers (A and B) together. The combinational logic circuit determines whether the sum is a BCD number or not and converts it to BCD by using the bottom 4-bit BFA if necessary.

60%


Same exam problem in part (b). Design a 4-bit BCD Adder.

60%


16


Assuming 2’s complement 8-bit represen-

tation for the following decimal numbers;

+70 and +80.

Add the given numbers in binary and

state if the result is correct. In case the re-

sult is incorrect, suggest a method to

solve the problem.

75%



h




Impact of gate delays on the output waveform. Draw the timing diagram of the given combinational logic with the given gate delays for each component.

75%

k


Design a Moore state machine that generates an even parity bit.

65%

17

ABET Attributes for ECE 562: Digital Circuits


Meeting Criteria


What decimal value does the 8 bit bi-

nary number (10011110)2 have if:

a) It is interpreted as an unsigned

number?

b) It is on a computer using

signed-magnitude representa-

tion?

c) It is on a computer using two’s

complement representation?

75%


Consider 1Gx16 memory chips that

make up a 32Gx64 memory that uses

low-order interleaving.

a) How many banks are needed

to build a 32Gx16 memory

from 1Gx16 memory chips?

b) How many 1Gx16 chips are

needed in each bank?

c) What is the total number of

1Gx16 chips in the 32x64

memory?

d) How many address bits does

each 1G x 16 chip need?

e) How many bits are needed in

the address of the 32G x 64

memory, assuming it is word

addressable? Where would ad-

dress 33 be located (Deter-

mine the address of the mod-

ule and offset in decimal num-

bers)

70%

18

f) Repeat part (e) assuming the

memory is byte addressable. In

addition, determine which byte

of the 32 bit word is ad-

dressed.


Construct the hard-wired control logic

for the LoadI X instruction in MARIE.

a) Determine the control signals

for each microoperation.

b) Design the hard-wired control logic for this instruction.

45%



Assuming 2’s complement 8-bit repre-sentation for the following decimal numbers; +70 and +80. Add the given numbers in binary and state if the result is correct. In case the result is incorrect, suggest a method to solve the problem.

75%



h




Same exam problem in part (e). (Lim-ited storage space for data)

k


Show how a 8Gx16 memory can be built by using 2Gx8 RAM chips. Clearly draw the connections and la-bel each wire. Determine the number of address and data lines for each chip.

60%

19

ABET Attributes for ECE 602: Engineering Analysis


Meeting Criteria


Fall 2017 final exam, Problems 2, 6 80





Fall 2017 final exam, Problems 2, 5 80



h




Discussed in lecture, not assessed --

k


Fall 2017 final exam, Problem 2,6 80

20

Comment by instructor: To estimate percentages of students meeting the various attrib-ute coverage, I used the threshold value of 70% on the final exam score – students who obtained at least 70% of the maximum possible points overall were deemed to have met the attribute requirement. I found that 44 of the 55 enrolled students met this require-ment.

ECE 602 Engineering Analysis – sample problems from Fall 2017 Final Exam

Problem 2

A weight of 200 lbs is suspended by a 17 foot long rope from

two points separated by a distance of 13 feet as shown in the dia-

gram at right.

(a) Find |F1| and |F2|

(b) Find the angles and

Problem 5

(a) Find equations for the lines that are tangent and normal to the level curve f(x, y) = c at the

point P0 = (1, 2) where f(x, y) = y2/2 – x2/2 and c = 3/2.

(b) Sketch the tangent and normal lines and level curve together with the gradient of f(x,y) at the

point P0.

Problem 6

(a) Find the work Wpath1 done in the vector field F = 2xy i + x2 j + k while moving along the direct

straight line path from (0, 0, 0) to (1, 1, 1).

(b) Suppose an alternate path is taken, namely (0, 0, 0) ----> (1, 1, 0) -----> (1, 1, 1), in the same

vector field F as described in part (a). Is the work Wpath2 done along this path necessarily the

same as that found in part (a)? Under what conditions on F could you answer this question with-

out actually calculating a contour integral again? [Hint: consider the component test on F.]

21

ABET Attributes for ECE 603: Electromagnetics


Meeting Criteria


Final Exam #3 (Electromagnetics and vector calculus)

85





Final Exam #1 (Determine a transmis-sion line load with Smith Chart)

30



h


Discussed in class, but not evaluated -



Discussed in class, but not evaluated. -

22

k


Homework #13, Problem 10.26 (Us-ing a Smith Chart tool)

75

23

24

25

26

27

ABET Attributes for ECE 617: Junior Lab I


Meeting Criteria


See sample student lab report (BJT Amplifier Design)

96



96



96


Not Applicable. All students work in-dividually on designs.

0



96



See sample student poster presenta-tion (Audio Amplifier Deign)

h




Contemporary Issues: Formal Report Writing, Presentation Skills.

96

k


See sample lab report (BJT Amplifier Design). Simulation using NI Multisim

100

28

ECE617 Junior Laboratory I Fall 2016

Exercise VII

Cascaded Amplifier Design – Interfacing a Base-Band Audio Signal to a Speaker

Introduction

Throughout this semester a number of topics have been covered in the Junior

Laboratory I course. These topics include:

steps in analog circuit design

analog circuit simulation

BJT, differential, and MOSFET transistors configurations

characteristics of transistor amplifiers

preparation of documentation

prototyping and testing

The experiences gained in the preceding laboratory exercises will be used to complete

laboratory exercise seven.

In this laboratory exercise a cascaded JFET/BJT/Class-AB amplifier will be

designed, simulated, prototyped, tested, and verified. The cascaded amplifier will provide

the interface between a base-band audio signal and an eight-ohm audio speaker (see Figure

1). Each student will prepare a poster presentation and live demonstration of his/her

amplifier design. ECE faculty and students will be invited to the presentations.

Purpose

To construct a cascaded JFET/BJT/Class-AB amplifier according to a set of given

design criteria.

To observe the effects of cascading transistors.

To verify that an amplifier meets the design criteria.

To interface a small base-band signal to an audio speaker creating a basic audio

amplifier stage.

To prepare a poster presentation and live demonstration of an engineering project.

Class A/B

Output

Stage

BJT Gain

Stage(s)

JFET High

Impedance

Input

StageSignal Source

Figure 1, System Block Diagram

8 ohm speaker

29

Reference

Sedra and Smith Textbook (7th Edition), sections 12.1-12.6 (Output Stages)

Procedure

(Nov. 7- Nov. 11 / Nov. 14- Nov. 18)

Using related transistor specifications and experience obtained from previous

laboratories, design a cascaded (multi-stage) amplifier according to the specifications given

at the end of this handout. You may use any configuration of transistors that is

appropriate, but it must include a JFET input stage and a class A-B output stage. The

circuit topologies shown in figures 2 and 3 below are good models to follow. Simulate the

design in Multisim and verify the design meets the given specifications.

Note: The 2N3906 and 2N3904 transistors may be replaced by the following Darlington

power transistors; however there are no transistor models in Multisim:

TIP122

TIP125

TIP102

TIP106

(Nov. 21 – Nov. 25 / Nov. 28 – Dec. 2)

In-lab construction and testing of the JFET input stage and BJT gain stages.

In-lab construction and testing of the Class A-B stage. Interface the amplifier stages to

the base-band audio signal and audio speaker, then adjust circuit parameters to improve

the quality of the small radio system. Remember to include an adjustable gain feature.

(Dec. 5 - Dec. 9)

Prepare a poster presentation of your design and be prepared to give an oral

presentation and demonstration of the working audio amplifier. The poster presentation

guidelines are attached to this handout. No laboratory report is required; you must pass in

the material displayed for the poster presentation.

Cascaded Amplifier Performance Specifications

(These specifications are provided as a guideline. You should make your gain adjustable

to compensate for variation in signal strength and desired speaker volume).

1) Minimum Output: approximately 0.2 – 0.3 volts peak to peak with load

30

2) Maximum Gain with LOAD, AmaxL: 100

3) Minimum Gain with LOAD, AminL: 50

4) Load Resistance, RL: 8 ohms (simulate 8-ohm speaker)

5) Minimum Resistance of input stage, Rin: 500,000 ohms

6) Source Frequency, FS: 500 to 10,000 Hertz

7) Supply Voltage: Dual +12 / –12

8) The design should have an adjustable gain control to compensate for variations in the

strength of the input signal. A potentiometer can be used to adjust the gain. You

should put some thought into where to place the gain control in the system.

31

32

33

ECE 617 Junior Laboratory I Fall 2017

Exercise III: BJT Amplifier Design

Introduction

This laboratory exercise leads the student through the development stages of a

bipolar junction transistor (BJT) amplifier design. Each student will be given a different

set of amplifier specifications. Your assignment is to design two amplifiers that meet the

minimum specifications which have been assigned. The two amplifiers will be constructed

in the laboratory and tested to verify that each circuit meets the minimum specifications.

Purpose

To go through the design stages necessary to implement a transistor amplifier

To calculate and measure the DC power requirements and efficiency of a BJT

amplifier

To determine the power requirements of a BJT in an amplifier circuit

To evaluate a transistor amplifier design using A SPICE based simulator

To prototype and test a transistor amplifier circuit

To prepare documentation for a BJT amplifier design

To investigate the effects of cascading two BJT amplifiers

To observe the effects of circuit performance when component parameters vary

To design a circuit that will minimize the effects of parameter variation

Reference

Sedra and Smith, 7th Edition, Chapters 6 and 7

Jaeger and Blalock, 5th Edition, Chapters 5, 13, 14

Phase I (Pre-lab)

The Beta parameter of common BJTs varies within and between fabrication runs

and manufacturers, as well as temperature. This exercise will demonstrate the procedure

for designing a transistor amplifier that reduces the effects of Beta variations. Design each

amplifier (Amplifier A and Amplifier B in figures 7 and 8) according to the assigned

amplifier specifications, the available resistor values (1/4 watt, 5% carbon), and the

capacitors needed. You must clearly show how you calculated the values for each circuit

element. Using Multisim, confirm that the amplifier designs meet the minimum assigned

specifications. Be sure to use the simulation models of the transistors assigned to be used

in this laboratory exercise. Determine the following based upon proper formulas and

simulation data:

DC voltage at the collector, base, and emitter.

34

Undistorted signal voltage gain (Vout/Vin) over the frequency range of 100 to

100kHz without the load and source resistors.

Undistorted signal voltage gain (Vout/Vin) over the frequency range of 100 to

100kHz, with the load and source resistors.

DC power dissipated by the amplifier and the DC power dissipated by the

transistor.

Variation in signal voltage gain (Vout/Vin) as the Beta of the transistor is varied over

the specified range without the load and source resistors.

Input/Output resistance of the two BJT amplifiers.

To determine the variation in gain due to changes to Beta (bf in model parameter)

use the parameter sweep feature in Multisim. Figure One shows the dialog box used to set

up the parameter sweep function. Choose Parameter Sweep from the simulation menu.

Figure 2 Parameter Sweep Window Showing a 50% Variation in Beta

35

You should receive a family of curves representing the gain at different values of Beta as

shown in Figure Two. The following plot has been zoomed in to observe the individual

traces. Click on the traces to observe the different gains in the Model Parameter Sweep

window.

Figure 3 Model Parameter Sweep Window

Figure Two illustrates the variation in gain due to the variation in Beta. The gain will also

vary as the other circuit elements (resistors and capacitors) vary.

Next perform a Monte Carlo analysis to help determine the gain variation due to

variation of all circuit elements. Choose Monte Carlo from the analysis menu. Choose Add

a new tolerance and the following dialog box, as shown in Figure Three, will appear. Set

up the dialog box as shown for the transistor.

36

Figure 4 Monte Carlo Tolerance Window

Also add all the amplifier resistors (5% tolerance) and capacitors (20% tolerance) as shown

in Figure Four. Do not add the load and source resistors.

37

Figure 5 Analysis Window

Choose the Analysis Tab and set up the analysis as shown in Figure Five (use the correct

output variable for your circuit). Then activate the Simulate button. You will see a family

of 50 curves representing the random variations of parameters over the specified tolerance

values.

38

Figure 6 Analysis Parameters

Look at the family of curves as shown in Figure Six and see if your design still meets the

specifications. (NOTE: your design does not have to meet the minimum specifications

with all elements varying, just with the variation of Beta as determined in the

parameter sweep analysis) The Monte Carlo analysis is performed to illustrate the effects

of parameter variation.

Figure 7 Family of Monte Carlo Curves

39

Compare the results obtained from simulations to values that you obtained through

calculations. If your simulation results predict that the assigned specifications will not be

met review your design and make the necessary changes.

Phase II (In-lab)

When you are confident that your transistor amplifier meets the minimum design

specifications, you will construct, test, and record measurement values for the two amplifiers

(A and B) in the laboratory as outlined below. All AC voltage gains are measured at a

frequency of 5000 Hz as stated in the specifications.

Construct each of your amplifier stages on the same board (you will eventually

need to cascade the amplifiers). Do not connect the DC power supply

Set the DC power supply to the assigned value

Carefully check the voltage polarities and then connect the DC supply to your

circuit

Measure the collector, emitter, and base DC voltages for the two amplifiers

Using the signal generator, apply a small AC voltage (sine wave) and measure the

undistorted AC signal voltage gain Vo/Vin

Add an external source resistor (RS) to the signal generator to increase the input

signal’s source resistance to the value specified for your design (recall that the

signal generator has an output resistance of 50 ohms) and measure the AC voltage

gain of each amplifier. Do not use load resistor.

Add an external load resistor (RL) and measure the AC voltage gain of each

amplifier. Do not use source resistor.

Measure the small-signal input and output resistance of each of your BJT

amplifiers. A laboratory instructor will review the measurement technique.

Compare the measured values to the calculated values.

Cascade amplifier A(without load and source resistors) with amplifier B (connect

the output of A to the input of B), connect load resistor RL to amplifier B, and then

measure the AC voltage gain of the two cascaded amplifiers

Cascade amplifier B(without load and source resistors) with amplifier A (connect

the output of B to the input of A), connect load resistor RL to amplifier A, and then

measure the AC voltage gain of the two cascaded amplifiers.

Report

40

As stated in course syllabus, reports are to include the following:

Cover page stating the course, lab title, student name and section, experiment date, and report

submission date.

Abstract summarizing the experiment and results (may be placed on cover page).

Introduction

Procedure/Methods

Results/Discussion

Summary/Conclusion

Appendix

The list below provides additional guidance in writing your report:

Procedure/Methods

detailed schematic of each amplifier

calculations used to determine circuit element (resistor and capacitor) values

calculations used to compute the input/output resistance of the two BJT amplifiers

Results

AC simulation of circuits over a frequency range of 100 to 100 kHz, with and

without the load and source resistors

AC simulation of parameter sweep and Monte Carlo analysis (no load and source

resistances)

table that compares in-lab measurements to simulation results:

DC voltage at base, emitter, and collector

AC voltage gain with and without the load and source resistors

DC power dissipated by the amplifier, the DC power dissipated by the

transistor

table that compares the in-lab measurements for amplifier gain A and amplifier gain

B.

table of the gain achieved when cascading the two amplifier stages

table comparing the measured input/output resistance of the two BJT amplifiers to the

calculated input/output resistance of the two BJT amplifiers.

Summary/Conclusions

summarize the procedures used to design and test the amplifiers

discuss the results obtained (gain, power, biasing) and their significance to the

overall design.

41

describe how you computed and measured the input/output resistance of the

BJT amplifiers. Discuss how the input/output characteristics of an amplifier

affect its performance.

discuss the results achieved when cascading the two transistor amplifiers

Appendix

original design specifications.

Mathematical derivations of formulas used for design

Remember that all figures, plots, and tables should be numbered and have descriptive titles.

Figure 7 Amplifier A (Common Emitter with Unbypassed Emitter Resistor)

Vcc = ______________

Amplifier Operating Specifications at 5000 Hz with infinite load resistance and zero

source resistance:

Minimum Voltage Gain (Vo/Vin) = ____________

Maximum Voltage Gain (Vo/Vin) = _____________

Maximum Voltage Gain Variation when the Value of Beta Changes by +-50% = 10%

Load Resistance RL = 400 ohms

Source Resistance RS = 10,000 ohms

42

Figure 8 Amplifier B (Common Collector)

Vcc = ______________

Amplifier Operating Specifications at 5000 Hz with infinite load resistance and zero source

resistance:

Minimum Voltage Gain (Vo/Vin) = 0.5

Theoretical Maximum Voltage Gain (Vo/Vin) = 1.0

Maximum Voltage Gain Variation when the Value of Beta Changes by +-50% = 20%

Load Resistance RL = 200 ohms

Source Resistance RS = 25,000 ohms

43

44

BJT Amplifier Design Lab #1

Abstract

In this laboratory exercise two bipolar junction transistor amplifiers were designed, built, and tested. The

amplifiers targeted to reduce the effects of Beta variations due to inconsistencies within the fabrication

process and different manufacturers. The circuit for Amplifier A is a common emitter amplifier with an

unbypassed emitter resistor. The circuit for Amplifier B is a common collector amplifier. The only specifi-

cations given for the circuits is a Vcc (supply voltage for the BJT) which is set at 10V for both amplifiers, a

minimum voltage gain of 18 for Amplifier A, a maximum voltage gain of 19 for Amplifier B, and a mini-

mum voltage gain of .5 for Amplifier B. AC simulations were performed on the circuits to ensure that the

voltage gain would meet specifications over a wide frequency range. In addition, a parameter sweep and

Monte Carlo analysis was conducted on each circuit to illustrate the variation in gain due to the variation

in Beta and the variation in gain due to all of the circuit elements. Overall, the circuits met all specifica-

tions during the laboratory testing, and the appropriate voltage gains for each circuit (18.35 for Amplifier

A and .9642 for Amplifier B) were achieved.

Introduction

Bipolar junction transistors are a significant element in relation to amplifier circuitry. The first transis-

tor was created in 1947 by John Bardeen, Walter Brattain, and William Shockley at Bell Laboratories in

Murray Hill, New Jersey (Bellis). Since this new piece of technology was developed, amplifier circuitry

has been revolutionized.

In this laboratory, the bipolar junction transistor was heavily studied and explored. When operating in

the active mode, the transistor can be used as an amplifier. The main purpose of this laboratory was to

design and construct two amplifier circuits with voltage gains independent to variations in Beta. The Beta

parameter can vary from 100 to 300 for the PN2222A transistor, according to the datasheet. This large

variation is due to differences between fabrication runs and manufacturers, as well as temperature. It is

paramount to have a

45

consistent voltage gain that is independent of which PN2222A transistor is used. Therefore, the voltage

gain must be independent of Beta.

Two main amplifier circuits were built in lab, Amplifier A and Amplifier B. Amplifier A and B both have a

Vcc (supply voltage for the transistor) of 10V. Amplifier A must have a voltage gain between 18 and 19,

and Amplifier B must have a minimum voltage gain of .5. Amplifier A is a common emitter amplifier with

unbypassed emitter resistor and Amplifier B is a common collector amplifier.

Many steps were taken prior to laboratory to make sure that the circuits would achieve the appropriate

voltage gains with the given parameters. Calculations were performed to find the resistor and capacitor

elements needed for each circuit and many analyses were performed to ensure each circuit was working

correctly. Through Multisim, the DC voltages at the collector, base, and emitter were obtained, AC simu-

lations were performed to ensure that the voltage gain would meet specifications over a wide frequency

range, parameter sweeps were conducted to illustrate the variation in gain due to the variation in Beta,

and Monte Carlo analyses were utilized to portray the variation in gain due to all of the circuit elements.

As far as in-laboratory procedures, Amplifiers A and B were both constructed on the same board. The

digital multimeter was used to adjust the DC power supply to the assigned value. The DC voltages at the

collector, emitter, and base were obtained for the two amplifiers with the digital multimeter. Next, a

signal generator was used to apply a small AC voltage (sine wave) and the maximum undistorted AC sig-

nal gain (Vo/Vin) was measured with an oscilloscope and digital multimeter. External source and load

resistors were added to each amplifier, and the gain was measured for each case. The amplifiers were

also cascaded with each other and voltage gains were measured for each scenario.

46

Laboratory Discussion

All circuit schematics are shown in Figures 1 and 2. The calculations that were used to determine the

values of the circuit elements are shown in Appendix A.

Amplifier A- Common Emitter Amplifier with Unbypassed Emitter Resistor

Figure 1, Amplifier A

Amplifier B- Common Collector Amplifier

Figure 2, Amplifier B

47

The simulation results are displayed in Figures 3 through 10.

Amplifier A- AC Simulation 100Hz-100kHz (Without Load and Source Resistors)

Figure 3, AC Analysis for Amplifier A

Amplifier B- AC Simulation 100Hz-100kHz (Without Load and Source Resistors)

48

Figure 4, AC Analysis for Amplifier B (No Load or Source Resistors)

Amplifier A- AC Simulation 100Hz-100kHz (With RL=400Ω an d RS=10 kΩ)

Figure 5, AC Analysis for Amplifier A (With Load and Source Resistors)

Amplifier B- AC Simulation 100Hz-10 0kHz (Wit h RL=20 0Ω an d RS=25 kΩ)

49

Figure 6, AC Analysis for Amplifier B (With Load and Source Resistors)

50

Amplifier A- Beta Parameter Sweep- AC Analysis

Figure 7, Beta Parameter Sweep for Amplifier A (Without Load and Source Resistors)

Amplifier B- Beta Parameter Sweep- AC Analysis

51

Figure 8, Beta Parameter Sweep for Amplifier B (Without Load and Source Resistors)

52

Amplifier A- Monte Carlo Analysis- AC Analysis

Figure 9, Monte Carlo Analysis for Amplifier A (Without Load and Source Resistors)

Amplifier B- Monte Carlo Analysis- AC Analysis

53

Figure 10, Monte Carlo Analysis for Amplifier B (Without Load and Source Resistors)

54

Table 1 illustrates the values of measured and simulated results and the percent difference between them.

Table 1: Lab Measurements and Simulated Results

Amplifier A- CEA Amplifier B- CCA

In Lab

Values

Simulation

Values

%

Difference

In Lab

Values

Simulation

Values

%

Difference

DC Voltage

at Base

3.2543V 3.26V .175% 3.285V 3.26V .767%

DC Voltage

at Emitter

2.6168 2.62V .122% 2.653V 2.63V .875%

DC Voltage

at Collector

6.7149V 6.66 .824% 9.999V 10V .010%

AC Voltage

Gain with-

out RS and

RL at 5kHz

18.348 18.378 .163% .9642 .99291 2.89%

AC Voltage

Gain with

RS

3.256 3.176 2.52% .079773 .08085 1.33%

AC Voltage

Gain with

RL

1.9482 1.9865 1.928% .7772 .7163 8.50%

DC Power

Dissipation

of Ampli-

fier

.01987W .0201W 1.144% .015955W .016W .28125%

55

DC Power

Dissipation

of Transis-

tor

4.17mW 4.12mW 1.214% .00453 .00450W .667%

Efficiency

of Ampli-

fier

.2612% .8867% 70.5% .104% .319% 67.4%

Table 1, Comparison of In-Lab Results to Simulations Results

Table 2 compares the in-lab measurements of the gains of Amplifier A and Amplifier B under different load

conditions.

Table 2 Gain V/V

At 5 kHz Frequency Amplifier A Amplifier B

Unloaded 18.348 .9642

With Load Resistor 1.9482 .7772

With Source Resistor 3.256 .079773

Table 2, Measured Gains for Amplifier A and Amplifier B

Table 3 illustrates the gains achieved when cascading the two amplifier stages.

Table 3 Gain V/V

At 5 kHz Frequency A Cascaded with B

(RL=200ohms connected to

Amp B)

B Cascaded with A

(RL=400ohms connected to

Amp A)

Connected with Load Resistor

RL

2.45 1.92

56

Summary and Conclusions

The procedure used to design and test the two amplifiers follows a pattern of calculations, simulating,

prototyping, and evaluating. Calculations must first be performed with the given specifications in order

to make sure that the parameters for the circuit can be met. This is an important aspect in the design

progression because it is paramount to make sure that the specifications can be attainable and it is also

paramount to find the parts for the circuit that will make the specifications work.

The circuit design focused around the circuit layouts given for each amplifier, the notion that the volt-

age gain should not vary with Beta, and the given parameters for each circuit (voltage gain and Vcc).

Assumptions were made during the calculation process that helped formulate circuit values for the

amplifiers. It was assumed that the transistor must operate in the active region in order for the

PN2222A to operate as an amplifier.

For Amplifier A, the rule of thirds was used to determine the voltages at the collector, base, and emit-

ter. A Quiescent Point was picked to be Ic=1mA. The collector resistor can be found from the equation

IcRc=(1/3)(Vcc). Therefore Rc equals approximately 3333ohms. Next, the given voltage gain can be used

to calculate the emitter resistance. The emitter resistance was found to be approximately 160ohms

from the equation Av=-(Rc/Re). Resistors R1 and R6 form a voltage divider, and assuming the current to

be 1mA and it is known that the voltage supply is 10V, the resistor values can be obtained. R1 was

found to be about 6666ohms and R6 was found to be about 3333 ohms.

For amplifier B, the gain is equivalent to RL/(RL+re). Therefore in order to have a gain close to one, a

large resistance was chosen for RL (4300 ohms).

The next part of the design process was taking the values obtained for each component and electroni-

cally building the circuits to be tested for simulation. The circuits were simulated using National Instru-

ments Multisim, and thorough analyses were conducted on each of the amplifiers. The AC analysis is

helpful to see how the gain varies over a wide frequency range (from 100 to 100kHz), which is useful in

order to see that the circuit specifications are achieved. Large capacitance values (47microFarads) were

used in order to accommodate this wide frequency range. The capacitors are used as coupling and by-

pass capacitors, so as long as they are sufficiently large, the frequency range should not be an issue. A

Monte Carlo Analysis was run on each amplifier to see how the variation of all circuit components var-

ied with the voltage gain. The parameter sweeps are very beneficial for ensuring that the value for Beta

does not affect the voltage gain.

57

The results obtained from in-lab testing were very close to the simulated values. The majority of the

percent errors were below 2%. The voltage gains were all very close when comparing simulating values

to experimentally obtained values. Also, percent errors for the power calculations were fairly accurate

when comparing simulated values against experimental values. The major flaw, however, is that the ef-

ficiency of the amplifier is really low. The amplifier has two input power sources. One comes from the

AC signal, and the other from the DC power supply. The amplifier functions for 360 degrees of the input

signal and uses a lot of power because it does not function for 180 degrees of the input signal. Because

it uses more power, the amplifier has less power offered to the output signal. Therefore, the efficiency

is low.

Cascading Amplifier A with Amplifier B led to a gain of 2.45 and cascading Amplifier B with Amplifier A

led to a gain of 1.92. Cascading Amplifier A with B is comparable to taking the product between the

gain with source resistance in Amplifier A with the gain with load resistance of Amplifier B. Cascading

Amplifier B with Amplifier A is similar to taking the product between the gain of Amplifier A with RL

and the gain of Amplifier B.

This laboratory was extremely useful for learning about the applications of BJT amplifiers and how

they operate. Designing two separate amplifying circuits was incredibly helpful for understanding how

all of the resistor and capacitor values contribute to the overall voltage gain. This laboratory is a very

real-life scenario, because having an amplifier that varies with

Beta is not practical because Beta can vary between 100 and 300 for a PN2222A. Overall, this labora-

tory successfully achieved the objective of creating two amplifying circuits within the given parameters.

Amplifier A met its design specifications with a Vcc of 10V and an AC voltage gain between 18 and 19.

Amplifier B also met its design specifications with a Vcc of 10V and an minimum AC voltage gain of .5.

Overall, this laboratory ran fairly smoothly from calculations, to simulation, to prototyping, and two

successful amplifying circuits were achieved.

References

S.Sedra, Adel, and Kenneth C.Smith. Microelectronic Circuits. 6th. New York: Oxford

University Press, 2004. Print.

Bellis, Mary. "The History of the Transistor."http://inventors.about.com. New York

Times Company, 2012. Web. 17 Sep 2012.

http://inventors.about.com/

58

<http://inventors.about.com/od/tstartinventions/a/transistor_history.htm>.

http://inventors.about.com/od/tstartinventions/a/transistor_history.htm

59

ABET Attributes for ECE 618: Junior Lab II


Meeting Criteria


See sample student lab report (Active Filter Design)

96



96

100 An ability to design a system, component, or process.


96


Not applicable. Students work individ-ually on labs.

0



96



See attached Formal Oral Presenta-tion Guidelines

h




Contemporary Issues: Formal Report Writing, Oral Presentation Skills.

96

k


See sample student lab report (Active Filter Design). Simulation using NI Multisim

96

60

Guidelines/Suggestions for the ECE618 Oral Presentation - Spring 2018

Presentations will be held during the laboratory periods in room S220 (there will be comfortable

chairs for use during this time) during the week of 4/30. Presentations will start at 8:10 a.m. and

2:10 p.m. sharp; everyone in the laboratory section must be present at 8:10 a.m. or 2:10 p.m.

Any student arriving late to presentations will automatically receive zero credit for this as-

signment. All students will be given a grading form to participate in grading presentations. Each

student will have a maximum of 15 minutes to present his/her topic (10-12 minutes for presenta-

tion and 3-5 minutes for questions). The instructor will keep track of time and will stop any

presentation at the 15 minute mark. There will be a 5-10 minute break midway through the

presentations. Please sign up for a topic by Friday, April 27, 2018 using the sign-up sheet on

instructors door (W221).

Take time to plan the presentation. Start with an outline of what is to be presented.

Think about what your audience will be interested in learning about your topic.

Plan the talk so there is a short period of time (2-3 minutes) at the end for questions.

You should have at least three (3) references that you can refer to during the talk.

A PC and projector will be available.

Slides should be readable from a distance and not cluttered.

Use figures and graphics whenever possible to illustrate and support what is being described.

Use examples to illustrate what you are describing.

Do not try to draw figures on the black board, it will waste time.

Being well prepared will help you relax and be enthusiastic.

Practice the talk with your family and friends.

Remember to stick to the topic and don’t try to cram too much information into the talk.

Remember the details of these topics will not be familiar to your audience and they will be

anxious to learn more about each subject.

Suggestions for Organizing the Presentation

I Title of the presentation and who’s presenting it.

II State clearly what you are going to talk about and provide a list of topics to be pre-

sented.

III Introduce the topic in a clear effective way.

IV Main portion of the presentation. In this section the main points are presented. Use slides

to illustrate the points being described. Stick to the point and be careful about presenting

too much detail.

V Conclusion or Summary. This section should tie together all the major points that were

presented. It is important to have a planned ending to your presentation. Review the

61

main points that you were trying to make during the talk. Don’t just say that’s all and ask

for questions. List your references.

VI Questions - Leave enough time (2-3 minutes) and be prepared to answer a few questions

on what was presented.

University of New Hampshire Department of Electrical and Computer Engineering

Introduction

This laboratory exercise will lead the student though the design, simulation, and testing

phases of a two-stage active Butterworth low-pass filter. Each student will receive a set of

requirements for his/her filter design. After simulating the transfer functions in Matlab and

calculating the values for the circuit parameters, the designs will be simulated using

MultiSim. A Monte Carlo analysis will be performed to determine the variation in output

response due to circuit tolerances. The testing stage of the design cycle will be performed

in the laboratory. Measured circuit performance will be compared to specified design

performance. This exercise will be scheduled over a two week period. The first week you

are to complete phase I (Pre-lab procedure) and Phase II during the second week (In-lab

procedure).

Purpose

To design a cascaded Butterworth low pass filter.

To go through the design cycle for creating an active filter.

To measure the frequency response of an active filter circuit.

To observe the link between pole/zero plots of a transfer function and the frequency

response of a system.

To determine the variation in the output response due to the tolerances of circuit ele-

ments (sensitivity analysis).

Reference

Chapter 17 in Microelectronic Circuits by Sedra and Smith, 7th Edition

Phase I Procedure (Pre-Lab)

ECE 618 Laboratory Three – Design of an Active Low-Pass Filter

2/26/18

62

Derive the transfer for the single-stage, two-pole, low-pass filter shown in Figure 1

below and verify that it matches Equation 1. The general form of Equation 1 is

shown with Equation 2 which indicates the relationship of the polynomial

coefficients to the Q and ω0 of the filter.

Figure 1: A single stage, two-pole, low-pass filter

where G = 1/R.

Equation 1: Transfer function for circuit of figure 1

Equation 2: General form of Equation1 showing Q and ω0

21

23

1

3212

21

31

)()(

CCGG

CGGG

ss

CCGG

Vin

VosH

2

002

1)(

wQ

wss

KsH

63

Design a four-pole filter (as shown in Figure 2) by cascading two two-pole filter

circuits using the following 2 steps:

1) Derive the transfer function T(s) for each filter stage of a two-stage four-pole

Butterworth low-pass filter using the assigned cut-off frequency f0 and low

frequency gain G0. Using Matlab’s Bode function and appropriate plotting

routines, plot the magnitude and phase of the four-pole filter transfer function

T(s). Confirm that the transfer function meets the assigned performance

requirements.

2) With reference to the circuit shown in Figure 2, compute the values required for

resistors R1, through R6 in order that the system response be a fourth order

Butterworth function with a voltage gain G0 at low frequencies and a gain of

(.707) Go at f0. Use resistors values that are available in the lab (10% resistors)

for simulation. Use the capacitor values shown (1.0 uF and 0.027 uF).

Figure 2: Four-pole Butterworth Low-pass filter

Verify the calculations with an AC Analysis in Multisim. Print the circuit

schematic and the computed magnitude and phase functions over the range from 10

to 10,000 Hz.

Perform a Monte Carlo analysis (see figures 3, 4, and 5) to determine the variation

in low frequency gain and cut-off frequency f0 due to resistors with a 10% tolerance

64

and capacitors with a 20% tolerance. Run the analysis for 20 runs. Print the plot

showing the variation in magnitude over the twenty Monte Carlo runs.

Figure 3: Device model tolerances selected for Monte Carlo analysis. All six resistors and 4

capacitors should be added for analysis. For example, cc7 is the capacitor with reference ID C7

and rr12 is the resistor with reference ID R12. Your resistor IDs may not be the same as shown.

65

Figure 4: The Add a New Tolerance dialog box for resistor rr10 (reference ID 10). Make sure the

Tolerance Type is set to percent.

Figure 5: Setting of the analysis parameters for Monte Carlo simulation. Your output node

number may not be the same as shown.

Phase II Procedure (In-Lab)

Select the parts to construct the filter.

Build the two-stage filter and record the magnitude over the specified frequency

range. Record more points in areas where the amplitude is changing the most.

Record the phase shift at 50 Hz and at the cut-off frequency fo.

Determine the low frequency gain Vo/Vin .

Using Matlab plot the recorded filter gain data over the range from 50 to 4000 Hz.

Demonstrate working filter to laboratory instructor.

66

Report

Reports are to include the following:

Cover page stating the course, lab title, student name and section, experiment date, and report submission

date.

Abstract summarizing the experiment and results (may be placed on cover page).

Introduction

Procedures/Methods

Results

Summary/Conclusion

Appendix

The list below provides additional guidance in writing your report:

Procedure/Methods

Show the complete derivation for Equation 1

Results

Matlab Plots

Magnitude and Phase of the four pole transfer function

MultiSim plots:

Log frequency plot of the transfer function H(s), scale 10 to 10,000 Hz

Log frequency plot of relative phase shift, scale 10 to 10,000 Hz

Monte Carlo results.

INPUT- OUTPUT phase shift at the 50 HZ and the cut-of frequency

Using Matlab, plot the magnitude of the measured output over the specified

frequency range.

Summary/Conclusion

Discuss the process used to design a Butterworth low pass filter

Discuss the results obtained from this exercise, i.e., any differences observed

between the assigned, calculated, and measured values.

Compare the plot of the measured output's magnitude to the following:

the plot obtained from the transfer function analysis in Matlab

the plot obtained from the schematic simulation.

67

Discuss the effects of the circuit's transfer function produced by the tolerance

of the elements.

Appendix

Matlab Script Files

Assigned performance specifications

Calculations used to determine circuit parameters (resistor values)

Remember that all figures, plots, and tables should be numbered and have descriptive

titles!

Performance Requirements:

Low Frequency Gain (G0): ___________________________

Low Frequency -3 dB cut-off point (fo): ___________________________ Hz

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

ABET Attributes for ECE 633: Signals & Systems I


Meeting Criteria


Problem 2 of final exam, students de-sign a system/transfer function based on the desired freq. response

90%





Graded problem in HW #6 studies the response of a complex mechatronic system

88%



h




Graded problems in HW #6 and #7 presents contemporary engineering application, and modern tools used these problems

85%

k


Graded problem in HW #7 require the use of Matlab and Simulink to predict and analyze system response

85%

86

Final Problem #2: For the following Bode plots and asymptote sketches, provide the corre-

sponding transfer function. SHOW all your work

a) (10 points) Solid lines are the Bode plots, dashed lines are the asymptotes

b) (10 points) Solid lines are the Bode plots, dashed lines are the asymptotes

𝜁 = 0.5

87

HW #6 graded problem: Consider the azimuth antenna position control problem, where a po-

tentiometer angle is the reference input to control the orientation of the antenna. The layout and

schematic drawings of the position control system is shown below.

The simplified block diagram of the antenna position control system is provided below

a) Find the closed-loop transfer function from reference input angle 𝜃𝑖(𝑠) to output angle

𝜃𝑜(𝑠).

b) Find the unit step response (unit step input 𝜃𝑖(𝑡) = 𝑢(𝑡) and zero initial conditions) for

𝐾 = 1. What is the steady state value of the error signal 𝑒(𝑡) = 𝜃𝑜(𝑡) − 𝜃𝑖(𝑡)?

c) Find the unit step response of the closed-loop system (a) using the step command in

Matlab. Transfer functions can be defined using the tf command. Is this the same re-

sponse you found in Part (b)? Plot and compare.

d) Increase the preamplifier gain to 𝐾 = 100 and use the step command to obtain the step

response in Matlab. How did the response change from Part (c)? Plot and compare.

88

HW #7 graded problem: We revisit the azimuth antenna position control problem from HW #5,

where a potentiometer angle is the reference input to control the orientation of the antenna. The

block diagram of the feedback control system is shown below.

Figure 8: Block diagram of azimuth antenna position control system

The closed-loop transfer function for 𝐾 = 100 was found in HW #5 to be

𝑇(𝑠) =𝜃𝑜(𝑠)

𝜃𝑖(𝑠)=

2083

3.142𝑠3 + 319.5𝑠2 + 537𝑠 + 2083

a) Assume that a constant reference input is subjected to sinusoidal external noises. The

noisy reference input is then given as

𝜃𝑖(𝑡) = 1 + 0.2 cos(12𝑡) + 0.4 sin(24𝑡 + 𝜋/4)

Find the output response 𝜃𝑜(𝑡) to the noisy reference input.

b) Plot the Bode plot of the closed-loop system 𝑇(𝑠) in Matlab (hint: bode in Matlab). Mark

on the Bode plots the amplification and phase shift values corresponding to the frequen-

cies of interest in Part (a). Does the amplifications and phase shifts found in Part (a) agree

with the Bode plots? Explain.

c) Construct a Simulink model of the block diagram in Fig. 1. The Simulink toolbox can be

accessed from Matlab using the command simulink. Construct the input 𝜃𝑖(𝑡) to be the

same as in Part (a), and simulate the response. Provide a printout of the Simulink model

and the output response 𝜃𝑜(𝑡). How does the output response compare to your solution to

Part (a)? Explain.

Hint: I provide my Simulink model below for your reference. You should be able to rec-

reate it using Transfer Fcn, Gain, Sum, Scope, Constant, and Sine Wave blocks. Make use

of the search function in the Simulink Library Browser.

89

90

ABET Attributes for ECE 634: Signals & Systems II


Meeting Criteria


Final Exam Problem#1 (DTFT Calcu-lation)

60%


Control Systems design at beginning of semester. See HW#2 and Exam#1 problem 2. Note that this would be a better fit for ABET category C.

60%




As in Category b above, see Exam#1 problem 2. More specifically, part b of the problem asks to explain the bene-fits of the control design.

60%



h




Contemporary issues were discussed in this course but they were not as-sessed.

-

k


Matlab used throughout course.HW#5 and HW#6 are pure Matlab exercises.

95%

91

ECE 634 Assignment #5 Spring 2018 Assigned: Saturday, 2/24/18 Due: Saturday, 3/03/18, 9AM, IN Canvas!

Sequences and Systems using Matlab

1) Read text chapter 3 Again (This week will focus on 3.5-3.10)

2) Generate a Matlab script to accomplish the following steps:

a. Generate 5 cycles of a discrete sinusoid with a frequency of f=1/20 cycles/sample and

an amplitude equal to 1 (5 cyles will be equal to 100 samples in this case). Plot using

stem().

b. Add noise to the sinusoidal signal above using the command 0.2*randn(1,100). This

will generate a Gaussian noise sequence of 100 samples to be added to the sinusoid.

Plot using stem().

c. Generate a unit step signal of 100 samples. Plot using stem().

d. Generate a unit ramp signal of 100 samples. Plot using stem().

e. Filter the noisy sinusoid in (b) using 𝑦(𝑛) = (1/2) ∗ [𝑥(𝑛) + 𝑥(𝑛 − 1)] and plot

using stem().

f. Filter the noisy sinusoid in (b) using 𝑦(𝑛) = (1/3) ∗ [𝑥(𝑛) + 𝑥(𝑛 − 1) + 𝑥(𝑛 − 2)] and plot using stem().

g. Compare your filtered results from e and f.

h. Differentiate your ramp signal in (d) using 𝑦(𝑛) = [𝑥(𝑛) − 𝑥(𝑛 − 1)] and plot using

stem().

i. Integrate your step signal in (c) using 𝑦(𝑛) = [𝑥(𝑛) + 𝑦(𝑛 − 1)] and plot using

stem().

Submit Matlab Code in Canvas as *.m file. Your code will be

run and graded based upon your generated results (plots).

Be sure to label axis and use titles in plots! Part g will be

incorporated in Matlab file as commented lines.

92

%%%%%%HW#5 Solution ECE634 Spring 2018%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%

%%%%%Sinusoid added to White Noise%%%%%%%%%%%%

clear all

N=100;

f=1/20;

n=1:N;

%signal=zeros(1,2*N);

signal(1:N)=sin(2*pi*f*n);

figure

stem(signal)

title('sinusoidal signal')

xlabel('n')

noise=randn(1,N);

noisysignal=signal+0.2*noise;

figure

stem(noisysignal);

title('Noisy Sinusoid');

xlabel('n');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%

stepsignal=ones(1,N)

figure

stem(stepsignal);

title('step');

xlabel('n');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%

rampsignal=n

figure

stem(rampsignal);

title('ramp');

xlabel('n');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%

%%%%%%%%%Part I Moving Average Filtered Sinusoid

x=noisysignal;

for i=2:N

y(i)=0.5*(x(i)+x(i-1));

end

figure

stem(y);

title('Filtered Noisy Sinusoid with MA Length=2');

xlabel('n');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%

x=noisysignal;

for i=3:N

y(i)=(1/3)*(x(i)+x(i-1)+x(i-2));

end

figure

stem(y);

title('Filtered Noisy Sinusoid with MA Length=3');

xlabel('n');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%Part II Differentiate the ramp signal

x=rampsignal

93

ECE 634 Assignment #6 Spring 2018 Assigned: Monday, 3/05/18 Due: Friday, 3/09/18, IN Canvas

LTI Systems Analysis using Matlab

I. LTID Systems Analysis and Convolution

1. Investigate the conv() function using MATLAB help. Determine the convolution for the

following sequence using the conv() command in MATLAB. Note: The “hat” symbol

indicates n=0.

𝑥(𝑛) = 0 , 3,4.5,6 ℎ(𝑛) = 1

3

,

1

3,

1

3

II. LTID Systems Analysis and Difference Equations

As opposed to the above example, if one of the sequences is of infinite duration, MATLAB cannot

compute the convolution directly and must be done by solving the difference equation using the

function filter. That is, instead of conv(x,h), MATLAB utilizes the feedback and feedforward

coefficients in the difference equations to get the output. Investigate the filter function using

MATLAB help and do the following:

1. For the difference equation: 𝑦(𝑛) = 2𝑦(𝑛 − 1) + 𝑥(𝑛)

a. Compute the unit-step response for n=0,…50 using the filter function

b. Compute the impulse response for n=0,…50 using the filter function

c. Is this system stable? Explain.

2. For the difference equation: 𝑦(𝑛) = 0.5𝑦(𝑛 − 1) + 𝑥(𝑛)

a. Compute the unit-step response for n=0,…50 using the filter function

b. Compute the impulse response for n=0,…50 using the filter function

c. Is this system stable? Explain.

Submit Matlab Code in Canvas as *.m file. Your code will be

run and graded based upon your generated results (plots).

Be sure to label axis and use titles in plots! Questions should

be answered as commented lines in Matlab file.

94

%%%%%%ECE634 HW#6 Solution ECE634 Spring 2018

%%%%%%%%%%%%%%%%%Part I

x=[0 3 4 5 6]

h=[1/3 1/3 1/3]

y=conv(x,h);

stem(y)

title('HW#6, Part I');

%%%%%%%%%%%%%%%%%Part II

xstep=ones(1,50);

ximpulse=zeros(1,50);

ximpulse(1)=1;

y=filter(1,[1 -0.5],xstep);

figure

stem(y)

title('HW#6, Part II.1a');

y=filter(1,[1 -0.5],ximpulse);

figure

stem(y)

title('HW#6, Part II.1b');

y=filter(1,[1 -2],xstep);

figure

stem(y)

title('HW#6, Part II.2a');

y=filter(1,[1 -2],ximpulse);

figure

stem(y)

title('HW#6, Part II.2b')

Final Exam

1. (30 points) Consider the following plant and controller:

𝐺𝑝(𝑠) =1

(𝑠+1)(𝑠+7) 𝐺𝑐(𝑠) = 𝐾𝑝

a) Compute the closed-loop poles for Kp =5, 9, 73, and mark their locations on a sketch

of the s-plane.

b) Describe what type of closed-loop response behavior to a unit-step input you will ex-

pect for each of the above selections of Kp (underdamped, critically damped,

overdamped)

c) Calculate the steady-state error to a unit-step input for each of the above selections of

Kp.

95

2. (20 points) For the plant in problem 1, do the following:

a) Design a PD controller (𝐺𝑐(𝑠) = 𝐾𝑝 + 𝐾𝑑𝑠 ) to place the closed loop poles at -8

and -10.

b) Explain the benefit of using this PD controller for a unit step response.

96

97

ABET Attributes for ECE 647: Random Processes


Meeting Criteria


Problem#1 of In-Class Final Exam(Covariance Matrix and Predic-tion)

85


Take-Home Final (Estimating auto-covariance of simulated filtered data)

95




Exam#1 problems 1,3 and 4 60



h




Contemporary issues were discussed in this course but they were not as-sessed.

-

k


Take Home Final (Matlab) 95

98

99

100

101

ECE647 Take-Home Final Spring 2018

Please submit code and all requested plots.

Code must be well commented.

All requested answers to questions and requested explanations should be entered as

comments in your code.

All plots should be titled with axes labeled.

This is 50% of your final exam grade.

For all exercises below, do NOT use Matlab functions mean(), var(), xcorr(),

cov()and xcov(). You can use these routines to verify your code.

DUE: Wednesday, 5/16, 5:00 PM

Part I. Generate a uniform zero-mean white noise process

Generate a 1000 X 50 matrix (1000 rows and 50 columns) representing 1000 sample realizations

of the uniform random process x(n) for n=1,……..N, with N=50, using the MATLAB function

rand(). Make sure the rand() command generates a zero-mean process.

1. Select a time sample, n, and estimate the univariate PDF from the sample realizations using

the MATLAB function histogram() (Modify the number of bins in the histogram to obtain

a reasonable estimate of the uniform PDF). Submit univariate PDF plot.

2. Select two time samples, n and n+1, and estimate the bivariate PDF from the sample real-

izations using the MATLAB function histogram2() (Modify the number of bins in the his-

togram to obtain a reasonable estimate of the uniform PDF). Submit bivariate PDF plot.

Part II. Wide-Sense Stationary (WSS)

Utilize the 1000 X 50 matrix generated in Part I for parts 1, 2, and 3 below.

1. Submit a stem plot ( stem() ) of the ensemble-estimated mean versus n.

2. Generate the ensemble-estimated covariance matrix. Submit a stem plot for the first

row of your covariance matrix.

3. Does this process appear to be WSS? Explain based upon results in 1, 2. You will

need to consider the structure of the covariance matrix to help you answer this ques-

tion. To assist in your explanation, submit 3 more stem plots of selected rows in the

covariance matrix.

Part III. Low-Pass and High-Pass White Gaussian Noise

102

1. Low-Pass filter the process from part I using 𝑦(𝑛) = 0.5 ∗ (𝑥(𝑛) + 𝑥(𝑛 + 1)). 2. Generate the ensemble-estimated covariance matrix. Submit a stem plot for the first row

of your covariance matrix. Compare this plot to that from the unfiltered noise from part

II.2 and explain difference.



a reasonable estimate of the PDF). Submit univariate PDF plot and explain your result.

4. Does the low-pass filtered process appear to be WSS? To assist in your explanation, sub-

mit 3 more stem plots of selected rows in the covariance matrix as you did in part II.

5. High-Pass filter the process from part I using 𝑦(𝑛) = 0.5 ∗ (𝑥(𝑛) − 𝑥(𝑛 + 1)). 6. Generate the ensemble-estimated covariance matrix. Submit a stem plot for the first row

of your covariance matrix. Compare this plot to that from the unfiltered noise from part

II.2 and explain difference.



a reasonable estimate of the PDF). Submit univariate PDF plot and explain your result.

8. Does the high-pass filtered process appear to be WSS? To assist in your explanation,

submit 3 more stem plots of selected rows in the covariance matrix as you did in part II.

%%%%%%ECE647 Final Exam Solutions%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%

clear all

rng('shuffle')

%%%%%Part I

PDFs%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%

%%%%%Get univariate PDF at n=1

X=(rand(1000,50))-0.5;

histogram(X(:,1),20,'normalization','pdf')

title('PDF at n=1')

%%%%Get bivariate PDF

figure

histogram2( X(:,1),X(:,2),20,'normalization','pdf')

title('Joint PDF of X1 and X2 at n=1,n=2')

xlabel('X1')

ylabel('X2')

103

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%

%%%%%%Part II WSS Process

%%%%%%%II.1>Ensemble Estimated Mean

Realizations=1000

for n=1:50

ensemblemeanI(n)=sum(X(:,n))./Realizations;

end

n=1:50;

figure

subplot(2,1,1)

stem(n,ensemblemeanI)

ylabel('E[X(n)]')

xlabel('n')

title('ensemble mean for 1000 realizations vs. time sample n (indicates stationarity)');

ylim([-1 +1])

%Confirm using "mean" function

ensemblemeanII=mean(X);

subplot(2,1,2)

stem(n,ensemblemeanII)

ylabel('E[X(n)]')

xlabel('n')

title('ensemble mean sequence above confirmed with "mean" function');

ylim([-1 +1])

%%%%%%%II.2>Ensemble Estimated Covariance

for n1=1:50

for n2=1:50

ensemblecovI(n1,n2)=sum(X(:,n1).*X(:,n2))./Realizations;

end

end

figure

k=0:49

subplot(2,1,1)

stem(k,ensemblecovI(1,:))

title('First row (n=1) of covariance matrix plotted vs k(indicates stationarity)');

%confirm using "cov" function

subplot(2,1,2)

Cxx=cov(X);

%extract first column to plot

stem(k,Cxx(1,:))

title('First row (n=1) of covariance matrix plotted (using "cov" function)')

%%Now plot at n=3, n=25, and n=40 to visualize stationarity in covariance

figure

subplot(3,1,1)


title('Third row (n=3) of covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,2)


title('25th row (n=25) of covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,3)


title('40th row (n=40) of covariance matrix plotted vs k(indicates stationarity)');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%

%%%%%%%%%Part III Filtered Noise

%%%%%%Low-Pass Filter the white noise process

for i=1:1000

for n=1:49

Y(i,n)=0.5*(X(i,n)+X(i,n+1));

end

104

end

%%%%%%%III.2>Ensemble Estimated Covariance for Low-Pass filtered process

for n1=1:49

for n2=1:49

YensemblecovI(n1,n2)=sum(Y(:,n1).*Y(:,n2))./Realizations;

end

end

figure

k=0:48

subplot(2,1,1)

stem(k,YensemblecovI(1,:))

title('First row (n=1) of low-pass filtered covariance matrix plotted vs k(indicates stationarity)');


subplot(2,1,2)

Cyy=cov(Y);


stem(k,Cyy(1,:))

title('First row (n=1) of low-pass filtered covariance matrix plotted (using "cov" function)')


figure

subplot(3,1,1)


title('Third row (n=3) of low-pass filtered covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,2)


title('25th row (n=25) of low-pass filtered covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,3)


title('40th row (n=40) of low-pass filtered covariance matrix plotted vs k(indicates stationarity)');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%

figure

histogram(Y(:,1),20,'normalization','pdf')

title('PDF of low-pass filtered noise at n=1')

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%High-Pass Filter the white noise process

for i=1:1000

for n=1:49

Z(i,n)=0.5*(X(i,n)-X(i,n+1));

end

end

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%III.4>Ensemble Estimated Covariance for High-Pass filtered process

for n1=1:49

for n2=1:49

ZensemblecovI(n1,n2)=sum(Z(:,n1).*Z(:,n2))./Realizations;

end

end

figure

k=0:48

subplot(2,1,1)

stem(k,ZensemblecovI(1,:))

title('First row (n=1) of high-pass filtered covariance matrix plotted vs k(indicates stationarity)');


subplot(2,1,2)

Czz=cov(Z);


105

stem(k,Czz(1,:))

title('First row (n=1) of high-pass filtered covariance matrix plotted (using "cov" function)')


figure

subplot(3,1,1)


title('Third row (n=3) of high-pass filtered covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,2)


title('25th row (n=25) of high-pass filtered covariance matrix plotted vs k(indicates stationarity)');

subplot(3,1,3)


title('40th row (n=40) of high-pass filtered covariance matrix plotted vs k(indicates stationarity)');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%%%%%

figure

histogram(Z(:,1),20,'normalization','pdf')

title('PDF of high-pass filtered noise at n=1')

106

107

108

ABET Attributes for ECE 651: Electronic Design II

ABET Category Example % Meeting Criteria

(60% or above)


Midterm 1 question #1 81%




In class activity questions 72%


Final exam question #1 97%



h




seminar speaker’s guest lecture. % attending

83%

k


Homework 1 94%

109

Example for Category a 5. (10 pts) For the filter circuit shown on the right, assume that the op-amp is ideal.

If R1 = 28 kΩ, R2 = 63 kΩ, C = 16 pF, find:

(a) the transfer function H(s)

(b) the cut-off frequency (in Hz), and the maximum gain (in dB)

(c) Graph the Bode plot (asymptotes) in the space provided.

(make sure to label the important values.)

Example for Category d

110

Example for Category e 6. (20 pts) The circuit below shows a multi-stage operational amplifier. The values of the circuit

components are given in the table. Assume a diode drop of 0.7 V if the device is in the for-

ward active mode.

111

(d) Find the Q-points (𝐼𝐶 , 𝑉𝐶𝐸) for

the transistors Q1 and Q2.

(e) Find the voltage gain 𝐴𝑣𝑡1 of stage 1 amplifier.

(f) Find the voltage gain 𝐴𝑣𝑡2 of stage 2 amplifier.

(g) Find the voltage gain 𝐴𝑣𝑡3 of stage 3 amplifier.

(h) Find the overall input resistance 𝑅𝑖𝑛 and the output resistance 𝑅𝑜𝑢𝑡.

Example for Category j I have invited a guest speaker on campus and asked my students to attend the seminar. The title of the talk was “Microscale engineering to electromicrobiology.” Attendance was taken.

𝑉𝐶𝐶 15 𝑉

𝑉𝐸𝐸 15 𝑉

𝑅𝐶 9 𝑘Ω

𝑅𝐿 5 𝑘Ω

𝛽1 = 𝛽2 60

𝛽3 = 𝛽4 100

𝑉𝐴1 = 𝑉𝐴2 50 V

𝑉𝐴3 = 𝑉𝐴4 175 V

𝐼1 150 µA

𝐼2 750 µA

𝐼3 2 mA

112

Example for Category k

ECE 651: Electronic Design II

Homework #1 Due: Monday, September 11th, 2017 (5pm)

Student Name: _________________________________

Note: Please include this sheet as a cover page (1 pt) and staple all pages together (1 pt).

Solve the following problems from Jaeger and Blalock (5th Edition):

(5 pts each) Chapter 10: Problems 10.78, 10.79.

(5 pts each) For each problem above, find the expressions for the asymptotes.

(5 pts each) For each problem above, generate a Bode plot (magnitude and phase) using

MATLAB. On the Bode plot, draw the asymptotes and label them properly (gain/phase val-

ues, frequency, slope, etc.).

Grading Method:

Problems from the book: Correct units (1 pt), correct procedure (4 pts)

For asymptote expressions: Correct procedure (5 pts)

113

For Bode plot: MATLAB code (1 pt), correct graph (1 pt), proper labels (1 pt)

with asymptotes (2 pts).

114

ABET Attributes for ECE 791: Senior Project I


Meeting Criteria


Project Driven: achieved by all stu-dents passing the course

87%



87%



87%



87%



87%


Lecture sequence on both profes-sional responsibility and ethics. Stu-dent assignment on an ethical di-lemma and written and oral response was documented and video taped

100%


Project Teams must submit a detailed written proposal for their projects and orally defend it for approval

100%

h



87%



87%



87%

115

k



87%

116

ABET Attributes for ECE 792: Senior Project II


Meeting Criteria



90%



90%



90%



90%



90%


Lecture sequence on both profes-sional responsibility and ethics. Stu-dent assignment on an ethical di-lemma and written and oral response was documented and video taped

100%


Project Teams must submit detailed written final documentation for their project. This is done by a three draft review cycle with the project advisor Individual projects must present their efforts in a Public poster session and oral presentation in April at an Under-graduate Research Conference

100%

h



90%



90%

117


Project Driven 90%

k


Project Driven 90%

Documents

Assessment of ABET Categories a) Through k) for Core ...unh.edu/ece/Department/ABET/Response to ABET Request for More Information about...Use of Multisim for a digital design problem