Assembly Language for Intel-Based Computers, 4 Edition · registers ALU clock I/O Device #1 I/O Device #2 data bus control bus address bus CU. Irvine, Kip R. Assembly Language for

Assembly Language for IntelAssembly Language for Intel--Based Based Computers, 4Computers, 4thth Edition Edition

Chapter 2: IA-32 Processor Architecture

Kip R. Irvine

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 2

Chapter OverviewChapter Overview

• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System


2.1 General Concepts2.1 General Concepts

• Basic microcomputer design• Instruction execution cycle• Reading from memory• How programs run


Basic Microcomputer DesignBasic Microcomputer Design• The central processor unit (CPU): where all the calculations and

logic operations take place• Clock: synchronizes internal CPU operations with other components• Control unit (CU): coordinates sequence of execution steps• Arithmetic logic Unit (ALU): performs arithmetic and bitwise

processing

Central Processor Unit(CPU)

Memory StorageUnit

registers

ALU clock

I/ODevice

#1

I/ODevice

#2

data bus

control bus

address bus

CU


Basic Microcomputer Design (Cont.)Basic Microcomputer Design (Cont.)

• The memory storage unit: where instructions and data are held while a computer program is running.

• A bus: a group of parallel wires that transfer data from one part of the computer to another.• Data bus

• Transfer instruction and data• Address bus

• Synchronize the actions of all devices• Control bus

• Hold the address of instruction and data


ClockClock• Clock: repeatedly pulses at a constant time

• Synchronizes all CPU and BUS operations• Machine cycle (clock cycle time): the most basic unit of

time for machine instruction• A machine instruction requires at least one clock cycle

to execute.• A few instructions (e.g., the multiply instruction) require in

excess of 50 clocks

one cycle

1

0


Clock (CClock (Coont.)nt.)

• The duration of a clock cycle is the reciprocal of the clock’s speed• 1 GHz ( 1 billion oscillations per second)

=> clock cycle time = 1 ns (nanosecond)

• Synchronous operation: need a clock• Clock is used to trigger events

• Asynchronous operation: does not require a system clock


Instruction Execution CycleInstruction Execution Cycle

• Fetch instruction• Decode• Fetch operands• Execute • Store output

I-1 I-2 I-3 I-4

PC program

I-1instructionregister

op1op2

memory fetch

ALU

registers

writ

e

decode

execute

read

writ

e

(output)

registers

flags

• The execution of a single machine instruction can be divided into a sequence of individual operations.

• Three primary operations: fetch, decode and execute.• Two more steps are required when the instruction uses a

memory operand: fetch operand and store output operand


Instruction Execution Cycle (Cont.)Instruction Execution Cycle (Cont.)

• Fetch• Fetch the instruction indexed by PC (program counter)• Copy it from memory into the CPU• Increment the PC

• Decode• The control unit (CU) determine the type of instruction and

tell the ALU• Fetch operand

• If a memory operand is needed, the CPU retrieve the operand from memory

• Execute• Store output operand

• If the output operand is in memory, write it back• p.s.

• Each step takes at least one clock cycle• Each processor has its own steps, e.g, IA-32 has six stages


MultiMulti--Stage PipelineStage Pipeline• Pipelining makes it possible for processor to execute

instructions in parallel• Instruction execution divided into discrete stages

S 1 S2 S 3 S 4 S51

Cyc

les

S tagesS 6

23456789

101112

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

I-1

I-2

Example of a non-pipelined processor. Many wasted cycles.

For k states and n instructions, the number of required cycles is:

n * k


Pipelined ExecutionPipelined Execution

• More efficient use of cycles, greater throughput of instructions:

S1 S2 S3 S4 S51

Cyc

les

StagesS6

234567

I-1I-2 I-1

I-2 I-1I-2 I-1

I-2 I-1I-2 I-1

I-2


k + (n – 1)


Wasted Cycles (pipelined)Wasted Cycles (pipelined)

• When one of the stages requires two or more clock cycles, clock cycles are again wasted.

S1 S2 S3 S4 S51

Cyc

les

Stages

S6

234567

I-1I-2I-3

I-1I-2I-3

I-1I-2I-3

I-1

I-2 I-1I-1

89

I-3 I-2I-2

exe

1011

I-3I-3

I-1

I-2

I-3


k + (2n – 1)


SuperscalarSuperscalarA superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v).

S1 S2 S3 u S51

Cyc

les

Stages

S6

234567

I-1I-2I-3I-4

I-1I-2I-3I-4

I-1I-2I-3I-4

I-1

I-3 I-1I-2 I-1

v

I-2

I-4

S4

89

I-3I-4

I-2I-3

10 I-4

I-2

I-4

I-1

I-3


k + n


Reading from MemoryReading from Memory• Memory access is a bottleneck and multiple machine cycles

are required when reading from memory• It responds much more slowly than the CPU.

• The steps are:• Address placed on address bus• Read Line (RD) set low to notify memory that a value is to be read• CPU waits one cycle for memory to respond• Read Line (RD) goes to 1, indicating that the data is on the data

busCycle 1 Cycle 2 Cycle 3 Cycle 4

Data

Address

CLK

ADDR

RD

DATA


Cache MemoryCache Memory

• High-speed expensive static RAM both inside and outside the CPU.• Level-1 cache: inside the CPU• Level-2 cache: outside the CPU

• Cache hit: when data to be read is already in cache memory

• Cache miss: when data to be read is not in cache memory.


How a Program RunsHow a Program Runs

Operatingsystem

User

Currentdirectory

Systempath

Directoryentry

sends programname to

gets startingcluster from

searches forprogram in

loads andstarts

Program

returns to


How a Program Runs (Cont.)How a Program Runs (Cont.)

• The user issues a command to run a certain program.• The OS searches for the program’s filename (in the

current directory or predetermined list of directories)• If found, the OS retrieves basic information, like file

size, physical location, about the program’s file from the disk directory.

• The OS loads the program file into memory.• The CPU begins to execute the program (process) by

jumping to the first instruction of the program• Now, the program is called a process

• The process runs by itself• When the process ends, OS removes its handle and

memory


MultitaskingMultitasking

• OS can run multiple programs at the same time.• A process may optionally contains multiple threads of

execution.• Scheduler assigns a given amount of CPU time to

each running program.• Rapid switching of tasks

• Gives illusion that all programs are running at once• The processor must support task switching.

• The processor saves the state (e.g., registers, variables, program counter) of each task before switching to a new one

• OS can assign varying priorities to tasks


2.2 IA2.2 IA--32 Processor Architecture32 Processor Architecture

• Modes of operation• Basic execution environment• Floating-point unit• Intel Microprocessor history


Modes of OperationModes of Operation• Protected mode

• The native mode of the processor and all instructions and features are available

• Used by Windows and Linux• Programs are given separate memory areas (called

segments) with proper protection

• Real-address mode• Native MS-DOS• Implements the programming environment of the Intel 8086

processor• All Intel processors boot in Real-address mode

• Then the OS may switch to another mode


Modes of Operation (cont.)Modes of Operation (cont.)

• System management mode• Provides an operating system with a mechanism for

implementing• power management, system security, diagnostics

• Implemented by computer manufactures

• Virtual-8086 mode• While in Protected mode, the processor can directly execute

Real-address mode program in a safe multitasking environment.• Each program has its own 8086 computer• A special case of Protected Mode, so it is called Virtual


Basic Execution EnvironmentBasic Execution Environment

• Addressable memory• General-purpose registers• Index and base registers• Specialized register uses• Status flags• Floating-point, MMX, XMM registers


Addressable MemoryAddressable Memory

• Protected mode• 4 GB• 32-bit address

• Real-address and Virtual-8086 modes• 1 MB space• 20-bit address

• Protected mode while running program in Virtual-8086 mode• Each program can access its own separate 1MB

memory


RegistersRegisters• Registers are high-speed storage locations directly inside the CPU • Intel registers

• 8 general-purpose registers• 6 segment registers• EFLAGS: processor status flag• EIP: instruction pointer

CS

SS

DS

ES

EIP

EFLAGS

16-bit Segment Registers

EAXEBX

ECX

EDX

32-bit General-Purpose Registers

FS

GS

EBP

ESP

ESI

EDI


GeneralGeneral--Purpose RegistersPurpose Registers

• Used for arithmetic and data movement• EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP

• Use 8-bit name, 16-bit name, or 32-bit name• Applies to EAX, EBX, ECX, and EDX

AH AL

16 bits

8

AX

EAX

8

32 bits

8 bits + 8 bits


Index and Base RegistersIndex and Base Registers

• Some registers have only a 16-bit name for their lower half:


Some Specialized Register Uses Some Specialized Register Uses (1 of 3)(1 of 3)

• EAX – extended accumulator register• Used by multiplication and division instructions)

• ECX – loop counter• ESP – stack pointer, extended stack pointer

register• ESI, EDI – index registers

• Extended source/destination index registers• EBP – extended frame pointer (stack)

• Used by high-level languages to reference function parameters and local variables



• Segment register: as base locations for pre-assigned memory areas• CS – code segment

• Hold instruction• DS – data segment

• Hold variables• SS – stack segment

• Hold local variables and function parameters• ES, FS, GS - additional segments

• EIP – instruction pointer• Containing the address of the next instruction to be executed



• EFLAGS• Status and control flags• Each flag is a single binary bit• Control Flag

• Control the operation of the CPU • Example, IF Flag (interrupt flag)

• Status Flag• Reflect the outcome of some CPU operations• Example

– Carry Flag (CF)– Overflow Flag (OF)– Sign Flag – Zero Flag– Auxiliary Carry Flag– Parity Flag


FlagsFlags• Control Flags

• Direction• Interrupt

• Status Flags• Carry

• unsigned arithmetic out of range• Overflow

• signed arithmetic out of range• Sign

• result is negative• Zero

• result is zero• Auxiliary Carry

• carry from bit 3 to bit 4• Parity

• sum of 1 bits is an even number


FloatingFloating--Point, MMX, XMM RegistersPoint, MMX, XMM Registers

• Floating-point unit: eight 80-bit floating-point data registers• ST(0), ST(1), . . . , ST(7)• arranged in a stack• used for all floating-point arithmetic

• Registers for multimedia programming• Eight 64-bit MMX registers• Eight 128-bit XMM registers for single-

instruction multiple-data (SIMD) operations

ST(0)

ST(1)

ST(2)

ST(3)

ST(4)ST(5)

ST(6)

ST(7)


Intel Microprocessor HistoryIntel Microprocessor History

• Intel 8080• Intel 8086, 80286• IA-32 processor family• P6 processor family• CISC and RISC


Early Intel MicroprocessorsEarly Intel Microprocessors

• Intel 8080• 64K addressable RAM• 8-bit registers• CP/M operating system• S-100 BUS architecture• 8-inch floppy disks!

• Intel 8086/8088• Mark the beginning of the modern Intel Architecture family• IBM-PC Used 8088• 1 MB addressable RAM• 16-bit registers• 16-bit data bus (8-bit for 8088)• separate floating-point unit (8087)


The IBMThe IBM--ATAT

• Intel 80286• 16 MB addressable RAM• Protected memory• several times faster than 8086• introduced IDE bus architecture• 80287 floating point unit


Intel IAIntel IA--32 Family32 Family

• Intel386• 4 GB addressable RAM, 32-bit registers,

paging (virtual memory)• Intel486

• instruction pipelining• Pentium

• superscalar, 32-bit address bus, 64-bit internal data path


Intel P6 FamilyIntel P6 Family

• Pentium Pro• advanced optimization techniques in microcode

• Pentium II• MMX (multimedia) instruction set

• Pentium III• SIMD (streaming extensions) instructions with special 128-

bit registers designed to move large amounts of data quickly

• Pentium 4• NetBurst micro-architecture, tuned for multimedia


CISC and RISCCISC and RISC• CISC – complex instruction set

• large instruction set• high-level operations• High-level language compilers would have less work• requires microcode interpreter• Complex instructions require a long time for the processor

to decode and execute• examples: Intel 80x86 family

• RISC – reduced instruction set• simple, atomic instructions• small instruction set• directly executed by hardware• High-speed engineering and graphics workstation use RISC

processors• examples:

• ARM (Advanced RISC Machines)• DEC Alpha (now Compaq)


2.3 IA2.3 IA--32 Memory Management32 Memory Management

• Real-address mode• Calculating linear addresses• Protected mode• Multi-segment model• Paging


IAIA--32 Memory Management32 Memory Management• Real-address mode

• Processor can run only one program at a time• Each program can address up to 1MB

• 1 MB RAM maximum addressable• (00000~FFFFFh)

• Application programs can access any area of memory• Single tasking• Supported by MS-DOS operating system

• Protected mode• Processor can run multiple program at the same time with

each process a total of 4GB memory• MS-Windows and Linux

• Virtual-8086 mode• Simulate an 80x86 running in real-address mode while in

protected mode• Command windows in MS-Windows


RealReal--Address ModeAddress Model Real-address mode can address up to 1MB memory

(20-bit address)l However, the original 8086 processor had only 16-bit

registers, which can not directly represent a 20-bit address

l Solution: segmented memory addressingl Memory is divided into 64KB (16-bit address) units called

segmentl Segment-offset address: use two 16-bit numbers to calculate

20-bit addressl A 16-bit segment value stored in segment registerl A 16-bit offset value

l Thus, absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset


Segmented Memory Map, RealSegmented Memory Map, Real--address Modeaddress Mode

00000

10000

20000

30000

40000

50000

60000

70000

80000

90000

A0000

B0000

C0000

D0000

E0000

F0000

8000:0000

8000:FFFF

seg ofs

8000:0250

0250

linea

r add

ress

es

one segment


Calculating Linear AddressesCalculating Linear Addresses

• Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset

• Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0Add the offset: 0 1 0 0Linear address: 0 9 0 1 0


Your turn . . .Your turn . . .

What linear address corresponds to the segment/offset address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.


Your turn . . .Your turn . . .

What segment addresses correspond to the linear address 28F30h?

Many different segment-offset addresses can produce the linear address 28F30h. For example:

28F0:0030, 28F3:0000, 28B0:0430, . . .


Protected ModeProtected Mode (1 of 2)(1 of 2)

• 4 GB addressable RAM• (00000000 to FFFFFFFFh)

• Each program assigned a memory partition which is protected from other programs• Described by segment descriptor tables

• Designed for multitasking

• Supported by Linux & MS-Windows


Protected ModeProtected Mode (2 of 2)(2 of 2)

• Program structure• code, data, and stack areas• CS, DS, SS segment descriptors• global descriptor table (GDT)

• Has two memory model• Flat segmentation model• Multi-segment model


Flat Segmentation ModelFlat Segmentation Model• All segments are mapped to the entire 32-bit physical

address space of the computer.• At least two segments: one for program code and one

for data• Each segment is defined by a segment descriptor,

a 64-bit value stored in a table known as the global descriptor table (GDT)


MultiMulti--Segment ModelSegment Model• Each program has a local descriptor table (LDT)

• Holds descriptor for each segment used by the program

3 0 0 0

R A M

0 0 0 0 3 0 0 0

L o c a l D e s c rip to r T a b le

0 0 0 20 0 0 0 8 0 0 0 0 0 0 A0 0 0 2 6 0 0 0 0 0 1 0

b a s e lim it a c c e s s

8 0 0 0

2 6 0 0 0


PagingPaging

• Supported directly by the CPU• A segment is further divided into 4096-byte (4KB)

blocks of memory called pages• Allow the memory used by programs can be larger

than the computer’s actual memory• Virtual memory v.s. physical memory• Part of running program is in memory, part is on disk

• Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages

• Page fault – issued by CPU when a page must be loaded from disk• Page in: bring a requested page into memory• Page out: evict an unused page to the disk


2.4 Components of an IA2.4 Components of an IA--32 Microcomputer32 Microcomputer

• Motherboard• Video output• Memory• Input-output ports


MotherboardMotherboard

• CPU socket• External cache memory slots• Main memory slots• BIOS chips• Sound synthesizer chip (optional)• Video controller chip (optional)• IDE, parallel, serial, USB, video, keyboard, joystick,

network, and mouse connectors• PCI bus connectors (expansion cards)


Intel D850MD MotherboardIntel D850MD Motherboard

dynamic RAM

Intel 486 socket

Speaker

IDE drive connectors

mouse, keyboard, parallel, serial, and USB connectors

AGP slot

Battery

Video

Power connector

memory controller hub

Diskette connector

PCI slots

I/O Controller

Firmware hub

Audo chip

Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification


Video OutputVideo Output• Video controller

• on motherboard, or on expansion card• A special-purpose microcomputer, relieving the

primary CPU of the job of controlling video hardware• Video memory (VRAM)• Video CRT Display

• uses raster scanning• horizontal retrace• vertical retrace

• Direct digital LCD monitors• no raster scanning required


Sample Video Controller (ATI Corp.)Sample Video Controller (ATI Corp.)

• 128-bit 3D graphics performance powered by RAGE™ 128 PRO

• 3D graphics performance

• Intelligent TV-Tuner with Digital VCR

• TV-ON-DEMAND™

• Interactive Program Guide

• Still image and MPEG-2 motion video capture

• Video editing

• Hardware DVD video playback

• Video output to TV or VCR


MemoryMemory• ROM

• read-only memory• EPROM

• erasable programmable read-only memory• Dynamic RAM (DRAM)

• inexpensive; must be refreshed constantly• Static RAM (SRAM)

• expensive; used for cache memory; no refresh required• Video RAM (VRAM)

• dual ported (refreshing+writing)• optimized for constant video refresh

• CMOS RAM• system setup information


InputInput--Output PortsOutput Ports

• USB (universal serial bus)• intelligent high-speed connection to devices• USB hub connects multiple devices• supports hot connections

• Parallel• short cable, high speed• common for printers• bidirectional, parallel data transfer• Intel 8255 controller chip


InputInput--Output Ports Output Ports (cont)(cont)

• Serial• RS-232 serial port• one bit at a time• uses long cables and modems• 16550 UART (universal asynchronous receiver

transmitter) controls the serial ports• programmable in assembly language


2.5 Input2.5 Input--Output SystemsOutput Systems

• Input-output is accomplished via different access levels• A high-level programming languages contains

functions that perform input-output• The OS is at the next level• The BIOS: a collection of functions that communicate

directly with hardware devices


2.5 Input2.5 Input--Output SystemsOutput Systems

• Level 3: Call a library function (C++, Java)• easy to do; abstracted from hardware; details hidden• slowest performance

• Level 2: Call an operating system function• specific to one OS; device-independent

• E.g., writing entire strings to files, reading string from the keyboard, allocating blocks of memory for application programs

• medium performance• Level 1: Call a BIOS (basic input-output system)

function• may produce different results on different systems• knowledge of hardware required• usually good performance


Displaying a String of CharactersDisplaying a String of Characters

• When a HLL program displays a string of characters, the following steps take place:

1. Application program writes the string to standard output.

2. The library function calls OS, passing a string pointer.

3. OS passes the ASCII code and color of each character to BIOS. OS also calls BIOS function to control the cursor.

4. BIOS maps each character to a particular system font and sends it to a hardware port attached to the video controller card.

5. The video controller card generates hardware signals to the video display.

Application Program

OS Function

BIOS Function

Hardware Level 0

Level 1

Level 2

Level 3


ASM Programming levelsASM Programming levels

ASM Program

OS Function

BIOS Function

Hardware Level 0

Level 1

Level 2

ASM programs can perform input-output at each of the following levels:


Playing a WAV File

• At the OS level, you do not have to know what type of device was installed and the card’s features

• At the BIOS level, you would query the sound card and find out whether it belongs to a certain class of sound cards

• At the hardware level, you would fine-tune the program for certain brands of audio cards, to take advantage of each card’s special features• Not all operating system permit user programs to directly

access system hardware


TradeoffTradeoff

• Tradeoff• Control (efficiency) v.s. portability

• However, some OSs, like Windows and Linux, do not permit user programs to directly access system hardware

Documents

Assembly Language for Intel-Based Computers, 4 Edition · registers ALU clock I/O Device #1 I/O Device #2 data bus control bus address bus CU. Irvine, Kip R. Assembly Language for