COEN 6501 Final December 2013

Question 1

a)FPGA’s have several advantages some are:

1. Ease of prototyping2. Fast prototyping3. Low cost of prototyping4. Re-programmability5. Availability of variety of FPGAs with embedded units6. Availability and friendliness of tools7. Fast testing of the circuit

b) F(A,B,C,D,E,F,G,H) = ABC+A BE+BCFGH+CDFH+AC FGF can be implemented with a variety of 2,3 and 4 variable LUT. In here, we give 2 implementations selected due to their lowest delay.

1

DADelay Area

4 4∗3LUT

2 4∗2LUT

3 2∗4 LUT

9ns 124mm2

COEN 6501 Final December 2013

The second implementation has the same delay, but the better area.

A D C F

2

Delay Area2 4∗3LUT

2 4∗2LUT

2 1∗4 LUT

3

9ns 98mm2

Z3

COEN 6501 Final December 2013

Question 2

x . y− z=( x . y )+(−z)

Z=Z3 Z2 Z1 Z0 Z is inverted and it is added to one get its –ve value and NOT XORed since we want is –ve.

Z=Z3 Z2 Z1 Z0

1+ extension …. Z3 Z3 Z3

+1

X3 X2 X1 X 0

Y 3 Y 2 Y 1 Y 0

P03 P02 P01 P00

P13 P12 P11 P10

P23 P22 P21 P20

P33 P32 P31 P30

Z3 Z3 Z3 Z3 Z3 Z2 Z1 Z0

1 ←+1

1

Z0P00

Z1

++++++

+++++

P33

Z3

+

+++

HHHH+

HH

M 0M 1M 2M 3M 4M 5M 6M 7M 8

Z2

Z3

Z3Z3

Critical Path

Z3 Z3 Z3 Z3

Z3 Z2 Z1 Z0

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COEN 6501 Final December 2013

Critical Path=8 τF+ τ ¿

4

COEN 6501 Final December 2013

Question 3

From the table above:

P1+¿=P2¿ y3

+¿= y0¿

P2+¿=P3¿ y2

+¿= y3¿

P3+¿=P4¿ y1

+¿= y2¿

P4+¿=P1¿ y0

+¿= y1¿

y3 y2 y1 y0

00 01 11 10

00 1 X01 X X11 X X10 X X

y3+¿= y0¿

y3 y2 y1 y0

00 01 11 10

000111 X X X X10 1 X X X

y2+¿= y3¿

5

Present State Next Statey3 y2 y1 y0 y3

+¿¿ y2+¿¿ y1

+¿¿ y0+¿¿

0 0 0 1 1 0 0 0 P1+¿¿

1 0 0 0 0 1 0 0 P2+¿¿

0 1 0 0 0 0 1 0 P3+¿¿

0 0 1 0 0 0 0 1 P4+¿¿

COEN 6501 Final December 2013

y3 y2 y1 y0

00 01 11 10

0001 1 X X X11 X X X X10

y1+¿= y2¿

y3 y2 y1 y0

00 01 11 10

00 X 101 X X11 X X10 X X

y0+¿= y1¿

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COEN 6501 Final December 2013

Question 4

a)

There are 6 paths:Path1: u1−u2−u4−u6

Path2: u6−u7−u8

Path3: u8−u10−u12

Path4: u1−u2−u5−u7−u8

Path5: u8−u11−u2−u4−u6

Path6: u8−u11−u2−u5−u7−u8 ←Byinspection∧calculationCritical path

CL6=0.2 (1.5+1.5 )+2+0.25∗1.5+2.5+0.25∗(1.5+1.5 )+2.0+0.25∗1.5+2.5+0.25∗1=11.35 ns

Tmax=3+11.35+1.5=15.85ns

So f max=1

T max= 1

15.85=63.1MHz

b)Path delay at point D, u6 which is path 5.

0.2 (1.5+1.5 )+2+0.25∗1.5+2.5+0.25∗(1.5+1.5 )+2∗0.25∗1=8.47ns+3=11.47=T '

T setup slack=(Tmax−T su )−T '=15.85−1.5−11.47=0.875ns

T hold at point D, u6 isT hmax

<TCQmin+T CLmin

−T CSmax

u8 u11 u2 u5

u7

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COEN 6501 Final December 2013

T CLmin is path 1 delay, T CQmin=3, T CSmax

=0,CL path1=8.65∴T h=3+8.65−0=14.47T h slack=11.65−0.5=11.15 ns

c)When clock skew is introduced between u1 and the rest. We calculate the changes to the path. Path 4 is the longest path.

T path4=0.2 (1.5 )+2+0.25 (1.5+1.5 )+2+0.25∗1.5+2.5+0.25∗1+T∫¿ ff+T su=13.175+3.5=16.67 ns ¿

New critical path has been introduced. This is the added delay at the input of u2 since CLK of other FFs is taken as a reference.

T path4>T path6

New frequency= 116.67

=59.001 MHz

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COEN 6501 Final December 2013

Question 5

a)Typical DelaystNAND=0.25+0.03∗1.5=0.295nstXNOR=0.4+0.05∗2=0.5nstMUX=0.3+0.1∗2=0.5nstFF=0.5+0.07∗1.5=0.605ns

Delay Variations

k v=1

1+0.01 f 0= 1

1±0.01×10=1.11 , 0.909 voltage variation

kT=t a+θJa∗P J

(T 2 )min=−55+30∗3=35℃+273=308 ° K(T 2 )max=125+30∗3=215℃+273=488 ° K

(k T )min=( 30827+273 )

1.5

=+1.05

(k T )max=( 48827+273 )

1.5

=+2.09

Composite De-rating factor K '=K v∗KT

K 'min=0.909∗1.05=0.954

K 'max=1.11∗2.09

Min/Max delaytNAND=0.281ns ,0.684 nstXNOR=0.477ns ,1.16nstMUX=0.477ns ,1.16nstFF=0.58ns ,1.4ns

D-input

Junction Temp Variation

@ Ambient temp of 27℃

De-rating Temp Variation

Min, Max Delay of the Gates used in Figure 2

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COEN 6501 Final December 2013

b)Total Period T=T CQmax

+T CLmax+T sumax

−T CSmin

Tmax=1.4+3.004+0.2−0=4.604 ns

f= 1T

= 14.604

=217 MHz

1.057 3.004Latest arrival←

t s

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COEN 6501 Final December 2013

Question 6

a)There are many ways of writing this piece of code. Here is just a simple example:library IEEE;use IEEE.std_logic_1164.all;

entity exam_circuit isport (A, B : in std_logic; O1,O2 : out std_logic);end exam_circuit

architecture structural of exam_circuit iscomponent decoder2to4port(a, b : in std_logic; d1, d2, d3, d4 : out std_logic);end component decoder2to4;

component AND_gateport(in1, in2 : in std_logic; out1 : out std_logic);end component AND_gate;

component OR_gateport(in1, in2 : in std_logic; out1 : out std_logic);end component OR_gate;

signal d1, d2, d3, d4 : std_logic;

begindecoder1: decoder2to4 portmap (A, B, d1, d2, d3, d4);AND1 : AND_gate portmap (d1, d2, O1);OR1 : OR_gate portmap (d3,d4, O2);

End structural

b)L2: X,Y : I std_logicL4: end Half_A_ConL5: H_A_BehavL7: -signalL8: process(X,Y)L13: problem of conversion X,YL17: endif

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