ASIC Implementation of High SpeedMultiplier Using Redundant BinaryAddition TreeKarthik D.* and Yuvaraj S.**

ABSTRACT

Multiplier plays a vital role in digital world. It is used in arithmetic units of Microprocessors, multimedia anddigital signal processors. Fast multipliers can be designed by using redundant binary addition trees. Redundantbinary representation is used while designing high performance multipliers. The redundant binary multiplier requiresan additional redundant binary partial product (RBPP) row because an error-correcting word (ECW) is generatedby the redundant binary encoding. This incurs in an additional RBPP accumulation stage for the multiplier. In thispaper, a RB modified partial product generator (RBMPPG) is proposed it removes the extra ECW and hence, itsaves one RBPP accumulation stage. Therefore, the expected output is RBMPPG generates fewer partial productrows with less area and power consumption than a conventional RB multiplier.

Keywords: RB multiplier, RB full adder, ASIC, RB booth encoding, redundant binary, RB partial product, carryselect adder.

1. INTRODUCTION

The redundant binary number representation has been introduced by Avizienis to perform signed-digit arithmetic;the RB number has the capability to be represented in different ways. Fast multipliers can be designed usingredundant binary addition trees. The redundant binary representation has also been applied to a floating-pointprocessor and implemented in VLSI. High performance RB multipliers have become popular due to theadvantageous features, such as high modularity and carry-free addition. The redundant binary representation(RBR) is a numeral system that uses more bits than needed to represent a single binary digit so that most numbershave several representations. An RBR is unlike usual binary numeral systems, including two’s complement,which use a single bit for each digit. Many of an RBR’s properties differ from those of regular binary representationsystems. Most importantly RBR allows addition without using a typical carry. When compared to non-redundantrepresentation, an RBR makes bitwise logical operation slower, but arithmetic operations are faster when a greaterbit width is used. Usually, each digit has its own sign that is not necessarily the same as the sign of the numberrepresented. When digits have signs, that RBR is also signed-digit representation.

* M.Tech-VLSI Design, Dept. ECE, SRM University, Kattankulathur, Chennai., Email: karthikdesamuthu@gmail.com

** Assistant professor, Dept. ECE, SRM University, Kattankulathur, Chennai, Email: Yuvaraj.s@ktr.srmuniv.ac.in

Table 1Translation table

Digit Interpreted value

00 -1

01 0

10 0

11 1

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7634 Karthik D. and Yuvaraj S.

1.1. ASIC

Application specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use,rather than intended for general-purpose use.Designers of digital ASICs often use a hardware descriptionlanguage (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

1.1.1. Redundant binary multiplier

A Redundant binary multiplier consists of a redundant binary partial product (RBPP) generator, a RBPPreduction tree and a redundant binary to normal binary converter. A redundant binary Booth encoding isusually used in the partial product generator of parallel multipliers to reduce the number of partial productrows by half. A RBPP row is obtained from two adjacent normal binary partial product rows by invertingone of the pair. Redundant multiplier requires [N/4] RBPP rows. An additional error-correcting word (ECW)is also required by Booth encoding therefore, the number of RBPP accumulation stages (NRBPPAS) requiredby a power-of-two word-length (i.e., 2n-bit) multiplier is given by:

NRBPPAS = [log2 (N/4 + 1)]

1.2. Redundant binary booth encoding

Redundant binary booth encoding technique can reduce the number of partial products. However, thenumber of expensive hard multiples i.e., a multiple that is not a power of two and the operation cannot beperformed by simple shifting and/or complementation increases too. Besli et al. some hard multiples canbe obtained by the differences of two simple power-of-two multiplies.

Redundant binary booth encoding has been proposed to facilitate the multiplication of two’s complementbinary numbers. It was revised as modified Booth encoding. The MBE scheme is summarized in Table 2,where A = a

N-1 a

N-2 … a

2 a

1a

0 stands for the multiplicand, and B = b

N-1 b

N-2 … b

2 b

1b

0 stands for the multiplier.

The multiplier bits are grouped in sets of three adjacent bits. The two side bits are overlapped with neighboringgroups except the first multiplier bits group in which it is {b

1, b

0, 0}.

Table 2MBE scheme

b2i+1,

b2i,

b2i-1

operation

000 0

001 +A

010 +A

011 +2A

100 -2A

101 -A

110 -A

111 0

Table 3RB encoding

ai+ a

i- RB digit

0 0 0

0 1 ~1

1 0 1

1 1 0

ASIC Implementation of High Speed Multiplier Using Redundant Binary Addition Tree 7635

Both MBE and RB coding schemes introduce errors and two correction terms are required:

1) When the NB number is converted to a RB format, -1 must be added to the LSB of the RB number;

2) When the multiplicand is multiplied by -1 or -2 during the Booth encoding, the number is invertedand +1 must be added to the LSB of the partial product.

A single ECW can compensate errors from the RB encoding.

A modified Booth encoding circuit for the partial product are proposed here (Fig. 1.3); an extra 3-inputOR gate is then added to the design. The three inputs of the additional OR gate are ~b

5, ~b

4, and~b

3. When

b5b

4 b

3 = 111, it is clear that ~b

5~b

4 ~b

3= 000.

Figure 2: redundant binary booth encoding simulation result.

Figure 1: redundant binary booth encoding.

7636 Karthik D. and Yuvaraj S.

1.3. Redundant binary full adder

The real advantage of using the RB numbers is that a carry-free addition rule can be used by exploiting theflexibility in representing any numbers. The main goal of formulating a carry-free addition rule is to guaranteethat the carry-out of an RB full adder (RBFA) is made independent of the carry-in. In other words, a parallelarray of adders can add two -bit words without carry propagation. A carry-free addition rule for an RBFA isshown in fig 1.3. The symbol notates the carry-out of the bit RBFA, and the symbol notates the intermediatesum of the bit obtained without relying on the incoming carry.

1.4. Hybrid parallel prefix/carry select adder

Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited forVLSI implementations. A novel framework is introduced, which allows the design of parallel-prefix Lingadders. In this approach saves one-logic level of implementation compared to the parallel-prefix structures

Figure 4: carry select adder.

Figure 3: redundant binary Full adder.

ASIC Implementation of High Speed Multiplier Using Redundant Binary Addition Tree 7637

proposed for the traditional definition of carry look ahead equations and reduces the fan-out requirementsof the design. Experimental results reveal that the proposed adders achieve delay reductions of up to 14%percent when compared to the fastest parallel-prefix architectures presented for the traditional definition ofcarry equations.

1.4.1. 32-bits Redundant binary multiplier

A 32-bit redundant binary multiplier using the proposed RBPP generator is shown in Fig. 5. The multiplierconsists of the proposed RBMPPG three RBPP accumulation stages, and one RB-NB converter. EightRBBE-2 blocks generate the RBPP is are summed up by the RBPP reeduction tree that has three RBPP

Figure 6: redundant binary multiplier simulation result.

Figure 5: 32-bit redundant binary multiplier.

7638 Karthik D. and Yuvaraj S.

accumulation block contains RB full adder.The 64-bit RB-NB converter converts the final accumulationresults into normal representation which uses a carry select adder the are four stages in a conventional32-bit redundant binary multiplier architecture. The proposed design is the of RBPP accumulation stagesis reduced from 4 to 3. These are significant savings in delay, area as well as powes consumption. Alldesigns of RB multipliers use the RBFA and RBHA. An RB-NB converter is required in the final stageof the RB multiplier to convert the summation result in RB form to a two’s complement number. It hasbeen shown that the constant-time converter in does not exist. However, there is a carry-free multiplierthat uses redundant adders in the reduction of partial products by applying on-the-fly conversion inparallel with the reduction and generates the product without a carry-propagate adder. The simulationresults done with model sim tool.

The multiplier designs are described at gate level in Verilog HDL and verified by cadence encountergenerated input patterns; the designs are synthesized by the cadence Design Compiler using the RTL 9.1.

1.4.2. ASIC implementation 32-bits Redundant binary multiplier

Table 4Design results of RB multipliers (Using Cadence encounter 9.1)

32-bit NB and RB multiplier Delay(ns) Area(µm2) Power(µm2)

CRBBE 1.76 13925 3227

RBBE 2.09 14454 5745

Proposed 1.45 12659 2890

Figure 7: 32 bit redundant binary multiplier layout. Active area size is 3.56 X 3.65 mm2.

ASIC Implementation of High Speed Multiplier Using Redundant Binary Addition Tree 7639

2. CONCLUSION

A high speed VLSI multiplier using RB addition tree design eliminates the additional ECW that is introducedby previous designs. Therefore, a RBPP accumulation stage is saved due to the elimination of ECW. Thenew RB partial product generation technique can be applied to 32-bit RB multipliers to reduce the numberof RBPP rows Simulation results have shown that the performance of RB MBE multipliers using theproposed RBMPPG is improved significantly in terms of delay and area. The proposed designs achievesignificant reductions in area and power consumption when the word length is at least 32 bits

Advantages:

Modular multiplication and division.

Application:

• Arithmetic applications.

• Digital signal processing.

• ALU of microprocessors

• Image processing.

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