ASIC and FPGA Translation

Agenda

• ASIC Design Flow• Manufacturing Flow• Synchronous vs. Asynchronous Designs• Design Techniques• Test Vectors• Design Release

CMOS Technology Comparisons

Very High

High

High

High

Very High

High

High

High

Full CustomStandard Products

Low

N/A

Low

Low - Very High

Low - High

Low - High

Low - High

FPGA

> 500K units1K – 1M unitsProduction Levels

~ 9 - 12 months~ 6 - 9 monthsDesign Time

Medium – High6 – 20 weeks

Low4 – 12 weeks

Engineering (Layout)

6 wks / 12 weeks +5 days / 8 weeksFab Time (Protos / Production)

Medium – High$200K - $700K

Low – Medium$30K – 200K

Cost

Medium< 1M bit

Low1K – 256K bits

Memory Capacity

Medium – High100Mhz – 1Ghz +

Low – medium20Mhz – 200Mhz

Performance

High200K – 4M gates

Low – Medium20K – 500K gates

Density

Cell-BasedGate Arrays Embedded Gate Array

ASIC Flow

RTLVHDL/Verilog

SynthesisLibrary

Pre-Layout Verification(check_all)

FunctionalSimulation

Place & Route

Customer Approval

SDF Delay File

Prototype

High-Volume Production

SimulationLibrary Vectors:

ctv, ytv

Low-Volume Production

HW VerificationRapidIteration

Post-Layout Verification

Static Timing

Synthesis

Gate Level Simulation

Gate LevelNetlist

Package File

Manufacturing Flow

Netlist / RTL,Vectors

EDA Tools:CadenceSynopsysExemplarModelTech

Wafer level

Wafer-lot level (2 mask)

few weeksOneMask Process

8-10 weeksTwoMask Process

Single wafer

CustomerApprovedLayout

Few daysOneMask Process

Production Grade Prototypes

Customer

Manufacturing Options

Wafer-lot level8-10 weeks

Hard Array Process

ASIC Vendor

Understand ASIC Vendors Problems

• Guarantees Silicon will match Simulations• Black Box Design • We don’t know what the design is or does

– Unknown design practices• Unknown interconnect, RC- loading of design before Layout

Place&Route • Digital Testers used ---- they have limitations over software simulators

Help from Customer

• Complete understanding of Tester limitations– Periodic – Synchronous machine– Number of timing channels (5)– Tester Memory depth (256K)– Tester I/O pin support (256 pins)– Pin Capacitance (50pf)– Tester Maximum Frequency (40Mhz / 80Mhz)– ASIC vendor Test Frequency (1Mhz)– Bus contention can cause damage to tester over time

• Develop Robust Periodic Functional Vectors

What Vendors are doing to improve

• Pre-Layout SDF• The best Third-party tools

– Synopsys - Synthesis– Verilog XL/NC – Gold Simulator– Cadence / Advent! – Layout tools– HSPICE – SPICE simulations– Test chips to verify models and track Fab process

• Timing driven Place & Route tools

Running Simulations is like:1. Flying a Flight Simulator

2. Football Practice

3. Internet Dating!

IT’S NOT THE REAL THING

• There are limitations to simulations

FPGA Migration

FPGA Migration

• Plan for ASIC migration early• IP – Verify both companies can support (PLL, Memories, etc.)

– Large FPGAs have a lot of small and large Memory Blocks• Don’t use FPGA black box macros

– Always use RTL code• Package compatibility• Synchronous designs only• Write Robust Functional Simulations

Synthesis

Synthesis

• RTL code typically cannot specify timing constraints accurately enough

• Timing constraints can "mislead" synthesis tools• I/O cells are not synthesized - instantiate• Most Memories cannot be synthesized – instantiate• Label cells you don’t want to use as "don't use” i.e.Transmission gates)• IP Cores are foundry specific and must be black boxed

– Hardcore– Soft Core

• The way the RTL code is written can drive the type of logicproduced.

Design Techniques

Synchronous Design

• Clock signal cause change in Data Storage elements.• The Clock signal is asserted at the same exact time on all storage elements of a

design.

Storage Element Logic Storage Element

CLK

Asynchronous Designs

• Process dependency– Speed and Drive Strength of cells vary

• Layout dependency– Capacitance, Resistance, Inductance variations of cell interconnect

Recommended Design PracticesAsynchronous Inputs

External Async Signal

Internal Sync Signal

Clk

Async Data In

1Sync Data

Clk

Reset

Non-Recommended Design Practices

Flip-Flop output driving second F-F clock input

Clock signal is skewed by the clk-q delay

- used in Ripple counters

Non-Recommended Design PracticesGated Clocks

Gated Clock input

xGate

- Glitches Can and will be generated on output of AND gate

- Gating a Clock signal will introduce skew in Clock Tree

- Use with extreme caution, they require very restrictive timingtolerances between the clock and the gate signal.

- Controlling Data instead of Clock is much safer

- The advantages of gated clocks is reduced power dissipation

Non-Recommended Design Practices

Double clocking F-Fs with both edges of Clock

Mux

• NOT a true Sync design practice

•Synchronous Preset and Resetting not available

• Scan insertion very difficult to implement,

•Muxes need to be inserted into Clock path for a single Clk frequency during Scan testing.

• Difficult to determine critical signal paths

• Asymmetrical duty cycle of Clock signal can cause Setup & Hold issues

Non-Recommended Design Practices

Race condition between Clk and Reset signal

Reset

Asynchronous Preset & Reset signals

Non-Recommended Design Practices

Simulation delay models not setup for inputs tied together

Delay Line

Process and Layout dependent

Non-Recommended Design PracticesInternal Tristates

MuxVS.

• Overloading bus

• Un-initialized at startup

• Central Decode Control Logic

•Reduces bus conflicts

• Testable

• Can be Larger and Slower

Recommended Design Practices

LogicLogic

Pipelined Logic

Race Conditions

• The same signal follows two or more paths having different delays to a common circuit element

• Two signals caused by the same event (clock transition) follow different paths to the same circuit element.

Clock Tree

Clock Buffering

• Balanced Clock Tree– Same depth of Clock Buffers to all Clocked Storage

Elements (Flip-flops, Memories).– Balance Skew and Delay

• Clock Driver Grids• Large Clock Drivers

Clock Buffering

Clock Tree is to trade-off and balance Delay and Skew

Un-balanced Clk treeTo reduce Skew – Delay must

increase

Design for Testability

Design Considerations

• Schmitt Trigger Inputs in noisy environments• Duplicate Logic to reduce fanout• BIST for Memory (MBIST) Megacells (ROMs, RAMs,

FIFO)• Imbedded Scan to improve manufacturability• JTAG – Board test and Package Interconnect verification

Bus Contention• Bus contention occurs when a bus is driven from two

different sources at the same time.• Two kinds of bus contention

– Internal• Tri-state buses

– External• Output buffer is enabled, and is outputting a logical

value that differs from that of the external driving source (Tester).

Designing for Testability

• Storage elements require a testing strategy that puts them into known states.– Initialization test vectors– Reset Logic

• Additional wiring and buffering• Reset Tree

– Make Logic Observable by Multiplexing Output Pins– Decode Input Pins (Internal Scan)– Break Up Long Sequential Chains

• One large counter – converted into two smaller counters during test

Test Vectors

• Functional Test– Verify if design meets functional specification– Periodic

• Scan Test– Device is free of manufacturing defects– Fault Coverage 99%+

I/O, Power & Grounds

• Understand ASIC vendors Power/Ground requirements

• Do not place clock signal pins, reset pins, preset pins, or other major control signals

between high-drive output buffers and VSS pads.

• Put a clock signal between two Vss pads (if possible)

• Inputs cause less noise than Output drive cells, due to the load they are driving.

Test Vectors• - Digital Tester are cycle based• - Input waveforms must be periodic• - Maximum (delay + width) = period• - Signal Waveform types WILL NOT CHANGE within the test pattern• - All test patterns must have a period 1MHz (1000ns).• - All Input (Driven) signal types must be driven no closer than 100ns from each other.• - Bidirect I/O

– Digital tester change (or start changing) driven signals at the beginning of a Tester Step (period). The Bidirect (both Control and Output signals) must change from Output to Input mode after the Tester Output Strobe or in a dummy cycle. Tester Output Strobe is used by the tester to capture Output signals, to compare against know-good-data (customer supplied)

– Designs can be adjusted so Bidirect I/O control signals change at the end of a Tester step (period), during Worst Case simulations. The problem occurs when a Bidirect I/O control logic is gated with a System Clock. When this is true, a dummy cycle is needed.

– During switching transitions from output-to-input, there must be a "dummy" cycle inserted. This allows the bidirect pin in question time to transition without causing bus contention with the Digital Tester. All other Input pins must retain last state.

– Signal / Tester Contention occurs when the ASIC and the Tester drive the same node, even for a short amount of time. Tester step is a drive (write) or acquire (read), but never both.

• - Test Vectors supplied to CEC must be in Binary, Tabular, Cycle Based, ASCII format. All Inputs, Outputs and internal Bidirect Control signal must be included. No other signals are allowed in this file.

• - One Bidirect Control signal is needed for each I/O buss it controls.• - Vectors for signals utilizing pull-up or pull-down, must be supplied. Functional simulations can not rely on

these resistors to supply the correct value.

Test Vectors

Function Test Vectors

• Best, Typical, Worst Case simulations• Used for prototype and production testing• Test Freq. = 1 – 5Mhz (CEC = 1Mhz) • At-speed vectors, scaled down to 1Mhz• Clean Test environment – Noise, Cap. Etc• Number of Vectors (CEC = 250K)• Scan Vectors

POC Vectors

00110100000001110011XX01111111111XXXXXXXXXXXXXXXXXXXXXX 0.1ns 00110100000001110011XX01111111111XXXXXX0XXXXXXXXXXXXXXX 0.5ns 00110100000001110011XX01111111111XXXXXX0XXXXXXXXXXXXXXX 0.9ns 00110100000001110011XX01111111111XXXXXX0XXXXXXXXXXXXXXX 200.0ns 00110100000001110010XX01111111111XXXXXX0XXXXXXXXXXXXXXX 200.1ns 00110100000001110010XX01111111111XXXXXX1XXXXXXXXXXXXXXX 201.0ns 00110100000001110010XX01111111111XXX0XX1XXXXXXXXXXXXXXX 201.2ns 00110100000001110010XX01111111111XX00XX1XXXXXXXXXXXXXXX 201.3ns 00110100000001110010XX011111111110X00XX1XXXXXXXXXXXXXXX 201.4ns 00110100000001110010XX011111111110X00XX1XXXXXXXXXXXXXXX 201.5ns 00110100000001110010XX011111111110X0011100XXXXXXXXXXXXX 201.6ns 00110100000001110010XX011111111110X0011100XXXXXXXXXXZZZ 202.2ns 00110100000001110010XX011111111110X0011100XXXXX000X0ZZZ 500.0ns 001101000000011100101101111111111010011100XXXXX000X0ZZZ 600.0ns 001101000000011100111101111111111010011100XXXXX000X0ZZZ 600.1ns

Digital Tester

Digital Tester

• Two stages of test– Wafer probe Test– Package Test

Digital Tester• Max. Pin Count• Clock Frequency• Scan Chains• Max Scan Memory Depth• Number of Time sets

– NRZ Non-Return-to-Zero.– DNRZ Delayed-Non_Return-to-Zero.– RZ Return-to-Zero– RTO Return-to-One

Deliverables from Customer

• Netlist (Verilog, VHDL ,EDIF, RTL, FPGA format)• Simulation (Testbenches, Vector File)• Synthesis constraint file• Critical net file• Pin.dat file• ID file

– contains overall generic information about design and Engineering contact information.

– ASIC vendors have their own version of this form.

Archive Data

• Get backup data of Design from ASIC vendor and keep your own.

– Netlist• Pre and post layout and Scan

– Simulation• Testbenches• Tabular format vectors and header files• Might not get Tester files

– Vendor Synthesis and Simulation libraries• In a few years these libraries won’t be around and to find a copy will

be almost impossible– You won’t get Layout data