Ashenden Designs IEEE Design Automation Standards Committee Plenary, 25 September 2003 Frankfurt, Germany Peter Ashenden [email protected] DASC Interim

Ashenden Designs

IEEE Design AutomationStandards Committee

Plenary, 25 September 2003Frankfurt, Germany

Peter [email protected]

DASC Interim Chair

25 Sep 2003 DASC Plenary 2

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Agenda

1. Welcome and introduction2. Working Group status reports3. Study Group status reports4. Other business5. Close


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IEEE DASC Introduction

• The IEEE DASC is responsible for the standardization of Design Automation related standards in the IEEE. It is part of the Computer Society of the IEEE.

• The biggest center of interest in the DASC has been around language based design and verification standards stemming from the key HDL standards VHDL and Verilog. From these have flowed standards for timing, synthesis, math routines, and test.

• Currently the emphasis of the group is growing to embrace system level requirements with standards being developed in analog-mixed signal and other extensions driven by these needs.


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IEEE DASC Introduction

• Membership application and other info at– www.dasc.org

• Email list: [email protected]– to subscribe, email to [email protected]– subscribe stds-dasc

• Peter Ashenden, Interim Chair– [email protected]


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Working Group Status Reports

• 1029.1: WAVES (Robert Hillman)– approved 1998, imminent admin withdrawal

• 1076: VHDL (Stephen Bailey)– approved 2002

• 1076b: VHDL PLI (Stephen Bailey)– PAR valid to 31-Dec-07

• 1076.1: VHDL-AMS (Tom Kazmierski)– approved 1999

• 1076.1.1: VHDL-AMS - Packages for Energy Domains(Alan Mantooth)– par valid to 31-Dec-06


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P1076 VHDL

• Chair: Steve Bailey• include Steve’s slides here…


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P1076b VHPI

• Chair: Steve Bailey• Paul Menchini quit as editor

– Completed 1st phase of LRM editing work– A couple drafts were circulated and

reviewed– Peter Ashenden will probably step in as

editor• Françoise Martinolle, John Shields and Peter are

determining what work needs to be done

• Planned to submit ballot package year end– Editor change will cause some delay


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1076.1 VHDL-AMS

• Chair: Tom Kazmierzki• 1076.1 due for re-ballot in 2004• Revision PAR to be submitted in Winter

2003/04• Mandatory revisions

– Corrections to LRM documented in errata sheet

– Changes in light of VHDL 200X• Revisions under consideration

– SPICE netlist interface– Mixed nets– Frequency domain review


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P1076.1.1 VHDL-AMS Packages

• Chair: Alan Mantooth• First Draft of proposed standard is with IEEE

for editorial review– response due by 21st September 2003

• Initial Balloting Pool List defined• Paperwork in progress for an e-ballot• Once IEEE review comments are received

– Modifications made to proposed standard– Final review period of 30 days will

commence


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• 1076.2: VHDL Math Packages (Jose Torres)– approved 1996

• 1076.3: VHDL Synthesis Packages (Alex Zamfirescu)– approved 1997, imminent admin withdrawal

• 1076.4: VITAL (Dennis Brophy)– approved 2000

• 1076.6: VHDL RTL Synthesis (J. Bhasker)– PAR expires 31-Dec-07

• 1164: VHDL Std_Logic (Peter Ashenden)– PAR expires 31-Dec-04


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1076.2 VHDL Math Packages

• Chair: Jose Torres• Plan to start reaffirmation activity in Jan 2004


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1076.3 VHDL Synthesis Packages

• Chair: Alex Zamfirescu• Semantic/functionality for

– Signed– unsigned– fixed and floating point real (variable

precision)• Relevant pages:

– http://vhdl.org/vi/vhdlsynth/vhdlsynth.html– http://www.eda.org/fphdl/


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1076.3 VHDL Synthesis Packages• Proposed changes:

– 1 Add "carry" bits.– 2 Logic operations array with bit.– 3 TO_01 operations for numeric_std.– 4 Move "reduce_pack" into std_logic_1164.– 5 Add a "numeric_unsigned" package.– 6 Add min, max, find_left and find_right operations.– 7 Add a "match" command, similar to "std_match" and

compatible with the 1164• "match" command..

– 8 Migrate the functions IEEE.numeric_std.std_match to the package IEEE.std_logic_1164 and provide for backwards compatibility.

– 9 Added the ability to do fixed point arithmetic to 1076.3


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1076.3 VHDL Synthesis Packages

• Floating point task force– Defined useful functionality for VHDL and Verilog– http://www.eda.org/fphdl/

• Work is in progress, some dependent of 1076 changes

• Short term plan– A Re-affirm 1076.3 as is– B Approve new version of 1076.3 with changes

independent of 1076• Future plan

– A. Synchronize dot3 changes with 1076 modifications

– B. Synchronize VHDL FP additions with Verilog new version

– C. Define ontology for numerics


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1076.6 VHDL RTL Synthesis

• Chair: J. Bhasker• Revision ballot successful• Resolution committee addressing comments

– too soon to say whether recirculation needed


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1164 VHDL Std_Logic

• Chair: Peter Ashenden• Several minor enhancements approved by

W/G– scalar/array logical operators– shift/rotate operators– unary logical reduction functions

• Will ballot on std_logic_textio soon• Draft ready for ballot by end-2003

– synch with VHDL-200x Fast Track


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• 1364: Verilog (Michael McNamara)– PAR valid to 31-Dec-07

• 1364.1: Verilog RTL Synthesis (Bhasker)approved 2002

• 1481: OLA (Harry Beatty)– PAR valid to 31-Dec-06

• 1497: SDF (Ted Elkind)– approved 2001

• 1499: OMF (Gabe Moretti)– approved 1998, imminent admin

withdrawal


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1364 Verilog

• Chair: Michael McNamara• Working Group has received nine donations of

technology for next revision• IEEE press announcement at

– standards.ieee.org/announcements/pr_p1364donations.html


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P1364.1 Verilog RTL Synthesis

• Chair: J. Bhasker• Approved as an IEEE standard last year• No new activity since then


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• 1577 OO-VHDL (Peter Ashenden)– PAR valid to 31-Dec-04

• 1603 ALF (Wolfgang Roethig)– approved 2003: congratulations!

• 1604 VHDL Library IEEE (Peter Ashenden)– PAR valid to 31-Dec-05

• 1647 e Verification Language (Yaron Kashai)– PAR valid to 31-Dec-07


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P1577 OO VHDL

• Chair: Peter Ashenden• No activity• OO features for VHDL will be considered as

part of VHDL-200x activity


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P1647 e Working Group

• Chair: Yaron Kashai• First meeting on 2 September, 38 people

attending– minutes on the website (www.ieee1647.org)

• Currently over a 100 registered members– first membership roster passed to IEEE-SA

• Currently preparing a work plan for the WG• Planning to have a next meeting on 27

October


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Study Group Status Reports

• High Performance Modeling (John Willis)• System Level Design (David Barton)• VHDL High Frequency (John Willis)


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VHDL High Frequency

• Chair: John Willis• Name change from VHDL-RF/MW to VHDL-

HF• Approach to be taken addresses need for both

mathematical model and physical model– using a package defined abstractly in terms

of Maxwell’s Equations• Clears the way to submit

– a PAR for Language Extensions for HF Modeling in VHDL

– second par for Verilog extensions

Documents

Ashenden Designs IEEE Design Automation Standards Committee Plenary, 25 September 2003 Frankfurt, Germany Peter Ashenden [email protected] DASC Interim