Art96 Mch G - A New Control Strategy to Achieve Sinusoidal Line Current in a Cascade Buck-Boost Converter-IEEE

7/28/2019 Art96 Mch G - A New Control Strategy to Achieve Sinusoidal Line Current in a Cascade Buck-Boost Converter-IEEE

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO. 3, JUNE 1996 441

A New Control Strategy to Achieve Sinusoidal LineCurrent in a Cascade Buck-Boost ConverterMohamed C. Ghanem, Kamal Al-Haddad, Senior Member, IEEE, and G illes Roy, Member, IEEE

Abstruct- This work presents a detailed theoretical analysisand experimental results of a novel means of obtaining sinusoidalinput current and unity power factor (UPF) via a cascade buck-boost converter. Using the new configuration, sinusoidal linecurrent in phase with the bus voltage is achieved, thanks toa new and simple to implement control strategy. Comparisonbetween the input and output voltages is used to select theinstantaneous operating mode of the converter. Off-line refer-ences are calculated and stored in two EPROM circuits andthen compared to measured currents to generate the gatingsignals of the appropriate switches. Complete theoretical analysis,simulation results and experimental data on a 500 W converterare presented, to demonstrate the superiority of the new controlstrategy. Low order harmonics n the input current are eliminatedand the input power factor is found to be over 0.99.

I. INTRODUCTIONONVENTIONAL off-line switch mode power suppliesC enerate high harmonic current which can interfere withand disturb communication networks. These currents alsoresult in distorted line voltage. Different alternatives of dy-namic switching patterns of power devices andlor passive filterelements have been proposed earlier to improve the quality ofinput current waveform of power converters. Active power fac-tor correction techniques have become increasingly desirablein off-line industrial equipment. Several active schemes havebeen proposed and analyzed for shaping the line current forsingle-phase applications [11, [7]. Power factor correction hasbeen achieved using various power conversion techniques [81,1121. The most popular methods used in the industry todayincorporate the boost topology (Fig. l(a)). The topology isadequate to operate in the continuous conduction mode forhigh power application or in the discontinuous conductionmode for lower output power.The buck regulator (Fig. l(b)) can also be used for thesame purposes, but with reduced efficiency as compared tothe boost converter. The principal drawback of this approachis the noticeable sharp turn-off of power conversion as theinstantaneous line voltage falls below the output voltage which

degrades the power factor and generates high order harmonics.Manuscript received June 20, 1993; revised June 12, 1995, July 3, 1995,and November 12, 1995. This work was supported by the National Scienceand Engineering Council of Canada (NSERC), Hydro Quebec, and the

Government of Quebec via the FCAR Fund.M. C. Ghanem and K. Al-Haddad are with the Department of ElectricalEngineering, Ecole de Technologie SupCrieure, Montreal, QuBbec, Canada,H2T 2C8.G. Roy is with the Department of Electrical and Computer Engineering,Ecole Polytechniqne de MontrCal, Montrkal, QuBbec, Canada, H3C 3A7.Publisher Item Identifier S 0278-0046(96)02378-7.

lR --L0AD

(a)

c 77 0DDS'L A-

vControlCircuit

(b)

*" *D 3 I I I / 1 IControlCircuit

(c)

1Fig. 1.converter scheme. (c) Buck-boost converter scheme.Typical converter schemes. (a) Boost converter scheme. (b) Buck

It is desirable to enforce, in the converter, a nearly sinusoidalinput line current, in phase with the line voltage. This is atimely subject and a number of articles on this topic wererecently published [I]-[3]. In [2], a unity power factor forwardconverter is proposed. The circuit is split in two independentpower stages: the input current shaping and the output voltageregulation. A continuous input current is achieved. However,with this technique only the buck mode is possible.This paper presents a new control strategy applied to theconverter topology which combines the buck and boost modesin one power stage (Fig. l(c)) and provides a simpler solutionfor the unity power factor acldc converter problem (Fig. 2).The proposed topology has two distinct modes of operation.Mode 1 has output voltage less than or equal to the input0278-0046/96$05.00 0 996 IEEE


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442 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO . 3, JUNE 1996

Fig. 2. Unity power factor buck-boost converter with control circuits scheme.

[VI200,an . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0 0.002 0.004 0.006 0.008 0.01 0,012 0.014 0.016t i n sec

Fig. 3. Input voltage and output voltage.rectified voltage and mode 2 has output voltage greater thanor equal to the input rectified voltage as shown in Fig. 3.A discussion on the principles of operation is followed by adetailed analysis showing the static and dynamic characteris-tics of the converter. The converter has boost mode operationwith fixed hysteresis and buck mode operation with variablehysteresis. The control strategy proposed for the unity powerfactor buck-boost converter is described and finally simulationand experimental results are presented.

11. ANALYSIS F THE PROPOSED CIRCUITIn this circuit (Fig. l(c)) both buck and boost modes ofoperation are used in each ac half cycle to achieve an outputdc voltage lower or greater than the maximum rectified inputvoltage. It is found that this technique makes, the Fourier

coefficients of the higher order harmonics of the input currentless dependent on the output voltage. The converter operateswith unity power factor independently of the output voltage.Operation Modes: The two operation modes are indicatedin Fig. 3. For luil 5 U,, the converter operates in boost modeuntil point A, and only switch SWP is controlled (SWS beingkept on). For luil 2 U,, (the operation falls between A andB) , the converter operates in buck mode and the control lawis applied only to switch SWS, (SWP being kept off).A. Sequences in the Boost Operation Mode

Two sequences describing the boost operation with fixedhysteresis and variable switching period are shown in Fig.4. When SWP is on, (sequence 1-Fig. 4(a)), the inductorcurrent i~ rises and when it exceeds a preset upper limiti u l k (Fig. 5(a)) the transistor SWP turns off, (sequence 2-Fig.4(b)) allowing the current to fall. When ZL becomes smallerthan a lower limit i i l k the transistor SWP turns on and thecurrent raises again. In this way, the rectified line currentliil is confined between two boundaries having a peak topeak difference 26 and a mid value centered at the rectifiedfundamental reference input current irefl corresponding to thekth switching period (Fig. 5(a))

When the transistor SWP is on, the state equations arediL 1-dt - I 4

and

luikl is the value of the rectified input voltage at the kthswitching period. 6%nd areflare respectively the amplitudesof the sinusoidal input voltage and the fundamental inputcurrent for the given power level

When the transistor SWP is off, the state equations arediL 1 1d t -~ - -we L-luikIand

(4)

(5)The inductor current i~ and the capacitor voltage vc are takenas state variables and IC is the state vector. The differentialequations associated with sequences 1 and 2 can be expressedin matrix form by (6) and (7)

li: = [" -& [iL], +[ k ] uikl (SWP on) ( 6 )


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- * * -IC

D s swe' c=Correction

Circuit

L0AD-

CorrectionCircuit

i] ower Factor I

Power FactorCorrection

Circuit(C)

ui iic2,

X D 1 k 2 ' IC6 SWP c F qD s -1ED4 f 0 3 I

Fig. 4. Equivalent circuits of buck-boost converter in buck and boost modes.(a) Sequence 1, switch SWP is on. (b) Sequence 2, switch SWP is off. (c)Sequence 3, switch SW S is on. (d) Sequence 4, switch SWS is off.

Power FactorCorrection

B. Sequences in the Buck Operation ModeTwo sequences describing the buck operation with variablehysteresis and fixed switching period are shown in Fig. 4.When SWS is on (sequence 3-Fig. 4(c)), the inductor currentrises. When it exceeds a preset upper limit i uan (which iscalculated in Section 111), the transistor SWS is turned off,and Ds turns on (sequence 4-Fig. 4(d)), and the inductorcurrent falls. When i~ becomes smaller than the lower limit

i / z n (Fig. 5(b) and (c)), SWS turns on and the current startsrising again. In this way, the average line current is confined ina band around the sinusoidal reference irefl which determines

I . I I

/ e f l ( k t 1 )

b tt2(k -1)-I

TP k

+ t

GHANEM et al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT 44 3

the output power.

Aik113n - - - tof f JI + tan k n tcn

(c)Fig. 5 . Input current and inductor current in buck and boost modes. (a)Choke current waveform in case of the boost operation. (b) Input current i;inbuck mode. (c) Inductor current i~ in buck mode.

In the sequence 3, the switch SWS is on (Ds being o f f ) andthe corresponding state equations are

andi L =i, +R (9)

dvci, =c-d tSubstituting (10) and (11) in the (9) gives

(12)dv, 1 , 1-t - Z t L -v, U ,i~ =C- +-d t R thenIn the sequence 4, the switch SWS is off (D s is on) andthe state equations are


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444 E E E TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL. 43 , NO. 3, JUNE 1996

dw, - 1 . 1- 2L - vc.d t C RC (14)The differentiad equations of sequence 3 and 4 can beexpressed in matirix form

111. CONTROLTRATEGYThe purpose of the new control law introduced here is tochange the naturallly non linear impedance of the converter to alinear one. A sinusoidal input current with unity displacementfactor is enforced in order to achieve such an operation. Theboost mode is used when U , 2 /uil.his mode involvesoperation with fixed current hysteresis and variable switchingperiod. The buck mode is used when U , 5 u ; ~ and it involvesoperation with fixed switching period and variable current

hysteresis. A relationship between switching sequence of SWSand SWP and the input current shape is established for thebuck and boost modes of operation. The switching scheme ofthe new control strategy is shown in Fig. 2. A comparisonbetween the measured choke current i~ and the synchronizedreference current!; (boost mode) and ire^ (buck mode)defines the control law of the switches. The variable duty cycleof the switches SW P and SW S is controlled by means of awindow comparator.The reference current waveforms are generated from tablesstored in the memory (EPROM). Regulation of the dc outputvoltage is accomplished by varying the reference currentwaveform. This control selects the appropriate input referencecurrent stored in the memory.An output control loop is used to regulate the output power(variation of the load). This control adjusts the input referencecurrent magnitude by an amount in proportion to the differencebetween the actual and desired values of the power.

A. Duty Cycle Computation in Boost ModeIn boost mode, the inductor current is monitored, and thestate of the switch SWP is controlled in each switching periodto move the line current magnitude in the desired form. Fig.5(a) shows the waveform of the current flowing in the chokeduring one switching period T p k .The upper and lower values of the current boundariesand the fixed current hysteresis are related by the following

expressions where i r e f l k is given by (1)6= i l l i - r e f l k i r e f l k - u l k . (17)

The input power can be controlled by changing 5refl.By solving for (2) and (3), we can write for t o k 5 t 5 t l k :(Fig. 5(4)

(18). IUik/i u l k = iLit=t1,, =Z l l k + ( t l k - O k )L

= r e f l k +6 (19)

andvc(t)=vco exp -~(

where the initial condition of the current isi Z l k = iLlt=tok

and by solving for (4) and assuming that we s fixed we canwrite for t l k 5 5 2 k : (Fig. 5(a)) the inductor current as

i L l t = t Z k = Z l ( k t 1 )= l l k + -( tZkuik - O k ) - (tzrce - l k )L L (23)

and by solving for ( 5 ) ( i ~s fixed) we can write the outputvoltage as

-- r e f l k - 6

The average value of the input rectified current within theswitching period T p k is given by the following integrals:

T p k : switching period in boost mode (see Fig. 5(a)).From (18), ( 2 2 ) , and (25) we obtain

Equation (28) shows the relationship of the power level at thekth switching cycle and a p k

The duty cycle o l p k ( o l p k T p k = l k - O k ) is obtained as

Equation (31) is the basis of the control strategy for the boostmode operation. Once the design assumption on the value of


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GHANEM et al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDALLINE CURRENT 445

[AI 25

t i n msec

1 2 3 4 5 6 7 8t in msec

(b)Fig. 6 . Reference currents for case 1 and case 2 (simulation results). (a) Casel (Uo =50 V and Po =500 W). (b) Case 2 (U , =100 V and Po =50 0 W).the current hysteresis 6 is made the value of a p k is calculable.The switching period of the ( k +1)th cycle is derived on thebasis of the ON/OFF durations in the kth cycle.

T p ( k + l ) = t 2 k - t O k (32)Calculation of the Upper and Low er Reference C urrent sulk

and &: For a given input power which is a function of a r e f l ,after calculating the duty cycle a p k we can compute the upperand the lower current limits i u l k and i l l ( k + ~ ) .B. Duty Cycle Computation in the Buck Mo de

To achieve a sinusoidal input current under buck modeoperation, the duty cycle aSn f switch SWS, referred to oneswitching period T, must be calculated so that the averagevalue of the input current falls proportional to the instan-taneous value of the input voltage as shown in Fig. 5(b)and (c).The average line current iiavn during the nth switchingperiod is given by (33)

[VI 200[AI . . . . . . . .

, . , .

-200 ; : ~ ' ' ' ' '0 0.004 0.008 0.012 0.016(a)

25 I. . . . . . . .[AI

. . . . . . . .I , , , , I , ' t in sec

0 0.004 0.008 0.012 0.016(b)

4.5CAI 4

3210

.........................Hz60 ' 400 800 1200

(C)Fig. 7. Simulation results for case 1 (U, =50 V and P, =500 W). (a)Input voltage U,, utput Uoand line current 2 , . (b) Inductor current confinedbetween the two references. (c) Input current harmonics spectrum.

In continuous inductor current modeT, =tcn- an , and t b n - an=asnTs

where T, is the constant switching period in buck mode (Fig.5(b) and (c)).For tan = 0, (33) can be rewritten as

(34)


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446

43

10 1

I EEETRANSACTIONSON INDUSTNAL ELECTRONICS, VOL. 43 , NO 3 , JUNE 1996

. . . . . , . . . . ....,.........,.....

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

....................... . . . . . .

. . . . . . . . . 1 . . . .,. . . 1 . . ........

............................

. ....,. .......................

. . . . . . . . . . I .. .... .:. ........

. . . . . . . . . . . . . . . . . . . . . . . . . . . .- H z

t . . . . . . . ' . . . . . . . l . .\ \ ..:i, :/:1. . . . . . . .-200 0 0.004 0.008 0.012 0.016

. . . . . . . .- ,-.- . - -I ~ -

[A] 4.5 I , 1

At each switching period, the duty cycle is calculated inorder to obtainiiavnirefl sinwtlt=t,, . (35)

The maximum value of ;reflcan be obtained assuming anUPF operation by

By combining (35) and (36) we can calculate iiavn.

Substitution of (37) into (34) yields(37)

Then, the duty cycle a,, is found by solving (39)

(40)The a,, should be in the range of 0 to 1:0 5 a,, 5 1.Calculation of the U pper and Lower Reference Current i U z nan d i1zn: For a given input power which is function of irefland after calculating the duty cycle a,,, we can compute theupper and lower current limit iuzn and i l z , (Fig. 5(b) and (c)).Fig. 6 shows the typical waveforms of the two referencecurrents i u z n and 212, for two experimental cases. With thevalue of a,, calculated from (40), the references current i U2 ,and i12, can be obtained from the following equation (seeFig. 5(b) and (c))

and(42)(43)

2 .L 2 n =P ' k e f l n - / Z nQ s niz2n=iu2n-a,using (13),

(44)Equation (44) represents the variable current hysteresis for thebuck mode operation.

V C

La, = (1- a,,)T, -.

m. IMPLEMENTATION OF THE CONTROLSTRATEGY TESTCONVERTER

To illustrate the control strategy presented in the previoussection, the design procedures of a sample converter aredetailed for two loading conditions. The purpose of havingtwo sets of dc load voltages is to show the validity of thecontrol law over a wide range of output voltages at a fixedload power.

e Case 1: U , = 50 V ; I , = 10 A ; input voltage = 12 0V(rms).e Case 2: U,= 100 V ; I, = 5 A; input voltage = 120V(rms).

Simulation Studies: As shown in the analysis, the converteris assumed to operate with ideal circuit elements and switches.Simulation studies based on MATLAB software were used toselect the proper hysteresis levels and the switching deviceratings. The state (6), (7), (15), and (16) which describe all theoperating sequences of the converter are solved using Runge-Kutta algorithm. In order to ensure the proper transition ofthe operating modes, the initial condition of state variables at


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GHANEM et al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT 447

m1.1ch4

c h l

ch4

c h im 1 . lch4

m t . i ,100%31.8%10%3.1%

\

I

0.3%

(C) (d)Fig. 9. Experimental results for case l (Uo =50 V and Po =500 W). (a) Input voltage U,,output U , and line current i,. (b) Input voltage U,, utput U ,and filtered input current 2 , . (c) Inductor current confined between the two references. (d) Input current harmonics spectrum.

the beginning of each sequence are computed from the finalconditions of the state variables of the previous one.Solving (42) and (43), the maximum values of the inductorcurrent obtained by simulation (Fig. 6(a) and (b)) arei uZm ax21.7 A for U , =50 V

andiuZmax 12 A for U , =100 V

The peak value of the average input current obtained by (36)is irefl= 5.88 A.The voltage and current limit of switch SWP are 170 Vand 3.45 A . The voltage and current limit for SW S are 170V, 21 A.The output voltage ripple is at a frequency of 120 Hz, andthe dc current through the resistive load is equal to %.Solving(10) for C gives

dt atC = ,- = i-dv, AV for AV=4%, V d =100 V , I, =5 A .C =10000 pFand the inductor size is established by series of simulationswhich yields a value of 0.2 mH.

Prototype Studies: A laboratory prototype was built withIGBT switches, and ultra fast recovery diodes. The per-formance characteristics of the converter were measured as

function of the ac input voltage ui for both cases and atconstant power P, M Pi, = 500 W. Fig. 2 shows the blockdiagram of the controller used for test. The zero crossing signalfrom the line generates a reset signal to the digital counter(used for EPROMs) in each half cycle. The EPROMs have256 kbytes of memory. Reference waveforms irefl (in boostmode), and iren(in buck mode) are stored in EPROM-1 (upperlimits) and in EPROM-2 (lower limits). These waveforms areamplified and compared with current measured to determinethe duty cycle in the boost and buck modes. The first andthe second comparator with dual-J-K Flip-Flop are used todetermine the duty cycle a p k and as n for switches SWP andSWS. The third comparator is used to select the operatingmode.An output control loop is added to regulate the outputvoltage U,, the reference current magnitude is adjusted everyline half cycle as a function of the error between the desiredand the measured output voltage. The control law whichimposes such a change in irefl s given by

;ref (new) =$ref (old) +k p (Uoref - c) (45)where kp is a positive design constant.

Comparison of Simulation and Experimental Results: Figs.7 and 8 show simulation results of two cases of operation ofthe buck-boost converter. Figs. 7(a) and 8(a) show the input


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448 LEEE TRANSACTIONS ON INDUSTFUAL ELECTRONICS, VOL. 43, NO. 3, JUNE 1996

m f . 1

m2.4c h 1

m 1 . 1

c h l

ch 4

m 1 . 4 m l . 1 ,100%31.6%\10%

3.1%

Fig. 10.U , and filtered input current 2; . (c) Inductor current confined between the two references. (d) Input current harmonics spectrum.Experimental results fo r case 2 (U , =10 0 V and Po =500 W). (a) hp ut voltage U ; , output U , and line current 2;. (b) Input voltage U ; , output

current, the input voltage, and the output voltage waveformsof the proposed topology for case 1 and case 2, respectively.The calculated displacement factor was 0.9986 for case 1 and0.999 for case 2. The continuous inductor current ZL confinedbetween the two references irefl(Zul and ill) and irea(iu2ndi l z ) , are shown in Figs. 7(b) and 8(b), respectively, for case 1and case 2. Figs. 7(c) and 8(c) show the input current harmonicspectrum for case 1 and case 2. The calculated distortion factorwas 0.9998 for two cases 1 and 2. The THD of the currentwas found to be 0.02 for both the cases.The input power factor was 0.9984 for case 1 and 0.9988for case 2. The experimental results shown in Figs. 9 and10 confirm the theoretical analysis. It is to be noted thatthe converter presents boost and buck operation. Fig. 9(a)shows the input voltage, output voltage and the input currentwaveforms of the proposed topology in case 1.Fig. 9(b) showsthe filtered input current and the input voltage waveforms ofthe proposed topology in case 1. The input-side filter consistsof a series source inductance which equal to 2.1 mH andshunt capacitor of 0.47 pF (Fig. l(c)). The line current isnearly sinusoidal, and the measured displacement factor was0.9991. Fig. 9(c) shows the inductor current confined betweenthe two references and ires (Zu2 and i l 2 ) for case 1.Fig. 9(d) shows the input current harmonic spectrum for case1. The third, fifth, seventh, ninth, and other harmonics areless than 3% of the fundamental and the rm s value of the

harmonic components (up to 23rd) is 4.9% of the fundamental,the Distortion Factor is equal to 0.9988 and hence the THDof the input current is 4.9%. Fig. 10(a) shows the inputvoltage, output voltage and the input current waveforms ofthe proposed topology in case 2. Fig. lO(b) shows the filteredinput current and the input voltage waveforms of the proposedtopology in case 2. The line current is sinusoidal, and themeasured displacement factor was 0.999. Fig. lO(c) shows theinductor current confined between the two references z,,fl andi , ~nd iz2 for case 2. Fig. lO(d) shows the input currentharmonic spectrum for case 2. The third, fifth, seventh, ninth,and other harmonics are less than 2.6% of the fundamentaland the r ms value of the harmonic components (up to 61st)is 4.0% of the fundamental, the Distortion Factor is equal to0.9992 and hence the THD of the input current was 4.0%.A comparison of the results obtained for two output voltagelevels of the proposed buck-boost converter shows that thepower factor obtained is as good as that possible with a boostconverter. Moreover, the buck mode has near unity powerfactor under all load conditions. The output dc voltage of theproposed circuit can be varied in a broad range maintainingthe unity power factor operation.

V. CONCLUSIONThis paper proposes a new cascade buck-boost topologythat offers a high degree of power factor correction. Using a


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GHANEM er al.: A NEW CONTROL STRATEGY TO ACHIEVE SINUSOIDAL LINE CURRENT 449

simple control strategy, elimination of lower-order harmonicin the input current is achieved and the input power factoris improved to over 0.99, at power levels of 500 W, intypical application. In this strategy both buck and boostmode of operation are used in each ac half cycle to achievean output dc voltage of desired level. A broad range ofoutput voltage and output power are obtained with unitypower factor. The analysis performed and the design equationspresented enable the design to be adapted to a wide range ofoutput power. The effect of the cascade buck-boost inductanceand current ripple on the size and efficiency of converterpower stage have been taken into consideration [l]. Dueto the source impedance and the EM1 filter, the harmonicinterference on adjacent communication systems is expectedto be negligible.

REFERENCES[l] R. Ridley et al., Analysis and design of a wide input range power factor

correction circuit for three-phase application, in APEC 8th, 1993, pp.[2] C. Zhou, R. B. Ridley, and F. C. Lee, Design and analysis of ahysteretic boost power factor correction circuit, in IEEE PESC, Aug.1990, pp. 800-807.[3] D. M. Divan, G. Venkataramanan, and C. Chen, A unity power factorforward converter, in IAS, IEEE, Westin Galleria, Houston, TX, Oct.4 9 , 1992, pp. 666 672.[4] B. Andreycak, Active power factor correction using zero current andzero voltage switching techniques, in HFPC, Proc., June 1991, pp.46-60.[5] K. K. Sen et al. , Unity power factor single phase power conditioning,in IEEE PESC, June 1987[6] I. Takahashi et al. , High power factor switching regulator with no rushcurrent, in IEEE IAS, Jan. 1992, pp. 673-680.[7] M. S. Elmore et al., A power factor enhancement circuit, in IEEEAPEC, June 1991, pp. 407-414.[8] G. Rim and R. Krishnan, AC to DC power converter with unity powerfactor and sinusoidal input current, in IEEE APEC, June 1991, pp.

400406.[9] L. Dixon, High power factor preregulators for off-line power supplies,unitrode switching regulated power supply design, Sem. Man., SEM-700, 1990.[lo ] C. Silva, Power factor correction with the UC3854, Application Note,Unitrode Integrated Circuits.[ll] C. A. Canesin and I. Barbi, A unity power factor multiple isolatedoutputs switching mode power supply using a single switch, in IEEEAPEC, June 1991, pp. 430436.[12] M. Kazerani, P. D. Ziogas, and G. Joos, A novel active currentwaveshaping technique for solid-state input power factor conditioners,IEEE Trans Ind. Electron., vol. 38, no. 1, Feb. 1991.[13] M. Albach, Conducted interference voltage of AC-DC converter, inIEEE, PESC, June 1986, pp. 203-212.

299-305.

Mohamed C. Ghanem received the diploma inelectrical engineering from Ecole PolytechniquedAlger, Algeria, in 1986, and the M.Sc. degreein industrial electronics from University of Quebecin Trois-Rivikres, Canada, in 1990. He is currentlyworking toward the Ph.D. degree in the Departmentof Electrical and Computer Engineering at &olePolytechnique, Montreal University, Canada.His areas of interest include modeling and controlof switching converter, power factor correctionand new circuit configuration of soft switchingconverters.

Kamal AI-Haddad (S82-M88-SM92) was bomin Beirut, Lebanon, in 1954. He received the B.Sc.A.and the M.Sc.A. degrees from the UniversitC duQuCbec 2 Trois-Rivikres, Canada, and the Ph.D.degree from the Institut National Polytechnique,Toulouse, France, in 1982, 1984, and 1988, respec-tively.From June 1987 to June 1990, he was a pro-fessor at the Engineering Department, UniversitCdu QuBbec, Trois-Rivitres. In June 1990, he joinedthe teaching staff as a professor of the ElectricalEngineering Department of the Ecole de Technologie SupCrieure (UniversitCdu Quebec) in Montreal, Canada. His fields of interest are static powerconverters, harmonics and reactive power cont rol, switch mode and resonantconverters, including the modeling, control, and development of industrialprototypes for various applications.Dr. Al-Haddad is a member of the Order of Engineering of Quebec andthe Canadian Institute of Engineers.

Gilles Roy (S70-M75) was bom in Quebec, PQ,Canada, on August 1, 1947. He received the B.E. de-gree in electrical engineering and the M.Eng. degreefrom Ecole Polytechnique de Montreal, Montreal,PQ, Canada, in 1971 and 1975, respectively.From 1971 to 1978, he was a consulting engineerfor the Montreal Transit Office, Metro Department,working on different projects relative to the subwaytransit system. He developed an inboard pressuremonitoring system for the rubber tire wheels subwaycar; he took also an active part in settling thespecifications for the power electronic apparatus of the regenerative chopperdriven subway, in operation since 1976. In 1979, he became assis tant professorat Ecole Polytechnique where he developed a program in power electronicsfor both undergraduate and graduate students. He also established a researchlaboratory in industrial electronics focusing on static converters, simulationmodels for industrial drives and instrumentation for power electronics. Hisresearch activities deal with direct frequency changers, application of fiberoptics in power electronic control and development of software ools for drivesapplications. He currently works at Ecole Polytechnique as a professor in thedepartment of electrical and computer engineering.

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Art96 Mch G - A New Control Strategy to Achieve Sinusoidal Line Current in a Cascade Buck-Boost Converter-IEEE