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DESCRIPTIONREV DATE PAGES
PAGE DESCRIPTION
2Title, Notes, Rev. History1
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A1 All INITIAL REVISION A RELEASE
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Arria 10 SoC FPGA Development Kit Board
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PAGE DESCRIPTION
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Block DiagramClock Block DiagramI2C BUS Block Diagram Arria10 XCVR_1C_1DArria10XCVR1E_1F_1GArria10XCVR1H_1I_1JPCIe x8 Connector10/100/1000 SGMII PHYA10/100/1000 SGMII PHYBSFP+ Port ASFP+ Port BDisplayPort (x4)SD Transmit/ReceiveFMC Port A ConFMC Port B ConArria102K_2J_HPS_DDR3_DDR4Arria102L_HPS_SHAREDIOArria10_DedicatedIO_CONF10/100/1000 RGMII PHYBOOTFLASH_TRACEDebugHPS HILO 40-bitUSB PortsHPS UART PORTArria102A_2I_1V8IOArria103H_3G_FMCA_V57.1AArria103F_3E_FMCA_V57.1BArria103A_FMCB_IOArria103C_3D_HILO_IOAArria103B_HILO_IOBDB9RS232HILO 72-bit5M2210 System Controller
USB Blaster II -1USB Blaster II -2PLLPLL (2)Clock Cleaner
Reset Circuit
User IOClock RES MUX
I2C_MUXPDN DiagramPower Sequence
MAINSwitch_12V_DC_12V12Vto5VM12Vto3V3Blankpage3V3to2V53V3to1V8A10switch_12V_3V3
BLANK
12Vto0V9Blankpage
3V3toHPS0V953V3to0V9
3.3Vto1V0
3V3toHILOHPSVDD3V3toHILOVDD3V3toHILOVDDQ
3V3toFMCAVADJ3V3toFMCBVADJ
FMCSwitch_3V3
2V5_1V8Switch3V3IOSwitch3V3_1V8Discharge LoadCurrentmeasurement
Power DAC_ADCcontroller
Core Power DecouplingIO Power Decoupling
DC3V3currentsensors
Arria10_PowerArria10_GROUND
Blank Page 1MAXV_FPGA_IO
BLANK
A1.1 22 Change RGMII reference clock source, pull up to 1v840 DP clock netname is changed42 LED resitors are changed to 100ohm6,52,57 Change ED8101 I2C address to 0X0E and 0X1055,68,69 Change DMP3098L to DMG2305UX,28 Change netnames 45 Change Header to 0.1inch header55 Add logic to turn off A10 power when MAXV need be reprogrammed. 55,68 Change PMOS to NMOS for reducing ON resistance
ADD two LDOs for U315651 ADD Linear LDOs for U2419 HPS DM_alert bit postions are modified based on Quartus report38 Move Mictor trace JTAG into 1.8 Bank of Max236 Connect 3V3 to BANK405 Update Clock diagram
A2 21 Add 1K PULL UP resistors for MSEL[0..2], HPS,NPOR, HPSNRST ( only in SCH)25 Change R98 and R99 to 1K ohm22 Change R367 and R378 to 4.7K ohm74 Change R646 pull up voltage to I01V8, Change R674 to 100K ohm51 Need Install U74,Install D44, R156, DNI R157 Based on FB 28209945 Change LCD address to 0x2856 Install D4360 Update the sense RC netowrk values based on FB 261730, add +-15% voltage adjustable range59 Update the sense RC netowrk values based on FB 26173066 Update the sense RC netowrk values based on FB 26173064 Update the sense RC netowrk values based on FB 26173063 Update the sense RC netowrk values based on FB 26173062 Update the sense RC netowrk values based on FB 26173054 Update the sense RC netowrk values based on FB 26173057 Change remote senseing point to FGPA pins60 Change R495 value from 240K to 226K for generating 1.03V output57 Change ED8101P01QI to ED8101P04QI for 0.95V output52 Change ED8101P02QI to ED8101P05QI for 0.95V output51,52,56,57 Change R5258, R5243, R5045 & R5055 from 2K to 1.5K based on FB30211822 Change Linear LDO from LTC3026 to LTC3026-1
B 11,12,20,36 MDIOMDICof EMAC1 and EMAC2 are mapped to IO PINS of MAXV_IO CPLD 20,36 MOVE HPS_LED2,3, HPS_PB3 and HPS_DIP3 to Share IO port23,35 Move dedicate UART port to system MAXV51 USE LTM4676A to generate 3.3V power56 USE LTM4677 to generate 0.9V power45 Change J28 to the Linear Header58 Change R655 to 1M ohm 1% resistor for 0.9V output 16 R230, R237= DNI, R229, R236 =10K to enable hardware mode16 Uninstall R253,R238 and install R233 and R23211,12, 22 Change pull up resistor R312,R306,R68,R62 to 1K
C Change U23 to Production Silicon68 Change R5510, R454 to 10K ohm69 Change R393 to 49.9K ohm
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B1 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B1 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B1 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 SoC FPGA Development Kit Board
B2 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B2 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B2 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Title
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Date: Sheet o f
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Arria 10 SoC FPGA Development Kit Board
B3 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B3 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B3 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit Block Diagram
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B4 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B4 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B4 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit Clock Connection
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B5 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B5 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B5 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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Arria 10 Dev Kit I2C bus Connection
Application of two I2C masters in PMVID bus
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B6 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B6 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B6 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
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FMCB (PCIE END-POINT) XCVRs & 2 x SFP + XCVRs
Application
PCIE EP
FMC B Slot DPTransceiver [0:9]
SFP+ 0 and 1
Channel (Bank, number)
(1C,4);(1C,5);(1D,0);(1D,1);(1D,2);(1D,3);(1D,4);(1D,5)
(1C,2);(1C,3);(1C,4);(1C,5);(1D,0);(1D,1);(1D,2);(1D,3);(1D,4);(1D,5);
(1C,0);(1C,1)
RREF_BL
FBD0C2MN18FBD0C2MP18
FBD1C2MN18FBD1C2MP18
FBD2C2MN18FBD2C2MP18
FBD3C2MN18FBD3C2MP18
FBD4C2MN18FBD4C2MP18
FBD5C2MN18FBD5C2MP18
FBD6C2MN18FBD6C2MP18
FBD7C2MN18FBD7C2MP18
FBD0M2CP18FBD0M2CN18
FBD1M2CP18FBD1M2CN18
FBD2M2CP18FBD2M2CN18
FBD3M2CP18FBD3M2CN18
FBD4M2CP18FBD4M2CN18
FBD5M2CP18FBD5M2CN18
FBD6M2CP18FBD6M2CN18
FBD7M2CP18FBD7M2CN18
FBGBTCLK0M2CN18FBGBTCLK0M2CP18
FBD9C2MN18FBD9C2MP18
FBD9M2CP18FBD9M2CN18
FBD8C2MN18FBD8C2MP18
FBD8M2CP18FBD8M2CN18
LMK_SFPCLK_P41LMK_SFPCLK_N41
SFPA_TX_N13SFPA_TX_P13
SFPA_RX_P13SFPA_RX_N13
SFPB_TX_N14SFPB_TX_P14
SFPB_RX_P14SFPB_RX_N14
REFCLK0_FMCB_N40REFCLK0_FMCB_P40
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B7 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B7 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B7 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
PCIE Hard Core with CVPChannel 2,3,4,5,6,7
Tranceiver 1D BanK
A10SOC_1517
U23G
REFCLK_GXBL1D_CHTPAJ29
REFCLK_GXBL1D_CHTNAJ28
GXBL1D_TX_CH5NAM38
GXBL1D_TX_CH5PAM39
GXBL1D_RX_CH5N, GXBL1D_REFCLK5NAH30
GXBL1D_RX_CH5P, GXBL1D_REFCLK5PAH31
GXBL1D_TX_CH4NAN36
GXBL1D_TX_CH4PAN37
GXBL1D_RX_CH4N, GXBL1D_REFCLK4NAJ32
GXBL1D_RX_CH4P, GXBL1D_REFCLK4PAJ33
GXBL1D_TX_CH3NAP38
GXBL1D_TX_CH3PAP39
GXBL1D_RX_CH3N, GXBL1D_REFCLK3NAK34
GXBL1D_RX_CH3P, GXBL1D_REFCLK3PAK35
GXBL1D_TX_CH2NAP34
GXBL1D_TX_CH2PAP35
GXBL1D_RX_CH2N, GXBL1D_REFCLK2NAK30
GXBL1D_RX_CH2P, GXBL1D_REFCLK2PAK31
GXBL1D_TX_CH1NAR36
GXBL1D_TX_CH1PAR37
GXBL1D_RX_CH1N, GXBL1D_REFCLK1NAL32
GXBL1D_RX_CH1P, GXBL1D_REFCLK1PAL33
GXBL1D_TX_CH0NAT38
GXBL1D_TX_CH0PAT39
GXBL1D_RX_CH0N, GXBL1D_REFCLK0NAM34
GXBL1D_RX_CH0P, GXBL1D_REFCLK0PAM35
REFCLK_GXBL1D_CHBPAL29
REFCLK_GXBL1D_CHBNAL28
PCIE Hard Core with CVPChannel 0, 1
Tranceiver 1C BanK
A10SOC_1517
U23H
REFCLK_GXBL1C_CHTPAN29
REFCLK_GXBL1C_CHTNAN28
GXBL1C_TX_CH5NAT34
GXBL1C_TX_CH5PAT35
GXBL1C_RX_CH5N, GXBL1C_REFCLK5NAM30
GXBL1C_RX_CH5P, GXBL1C_REFCLK5PAM31
GXBL1C_TX_CH4NAU36
GXBL1C_TX_CH4PAU37
GXBL1C_RX_CH4N, GXBL1C_REFCLK4NAN32
GXBL1C_RX_CH4P, GXBL1C_REFCLK4PAN33
GXBL1C_TX_CH3NAV38
GXBL1C_TX_CH3PAV39
GXBL1C_RX_CH3N, GXBL1C_REFCLK3NAP30
GXBL1C_RX_CH3P, GXBL1C_REFCLK3PAP31
GXBL1C_TX_CH2NAV34
GXBL1C_TX_CH2PAV35
GXBL1C_RX_CH2N, GXBL1C_REFCLK2NAR32
GXBL1C_RX_CH2P, GXBL1C_REFCLK2PAR33
GXBL1C_TX_CH1NAW36
GXBL1C_TX_CH1PAW37
GXBL1C_RX_CH1N, GXBL1C_REFCLK1NAT30
GXBL1C_RX_CH1P, GXBL1C_REFCLK1PAT31
GXBL1C_TX_CH0NAW32
GXBL1C_TX_CH0PAW33
GXBL1C_RX_CH0N, GXBL1C_REFCLK0NAU32
GXBL1C_RX_CH0P, GXBL1C_REFCLK0PAU33
REFCLK_GXBL1C_CHBPAR29
REFCLK_GXBL1C_CHBNAR28
RREF_BLAW30R4078
2.00k
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B B
A A
PCIE RC XCVRs & 2X SGMII XCVRs & FMCB XCVRs
Application
PCIE RC
FMC B Slot DPTransceiver [10:15]
SGMII A and B
Channel (Bank, number)
(1E,4);(1E,5);(1F,0);(1F,1);(1F,2);(1F,3);(1F,4);(1F,5)
(1G,0);(1G,1);(1G,2);(1G,3);(1G,4);(1G,5);
(1E,0);(1E,1)
PCIE_TX_N210PCIE_TX_P210
PCIE_TX_N310PCIE_TX_P310
PCIE_TX_P410PCIE_TX_N410
PCIE_TX_N510PCIE_TX_P510
PCIE_TX_N610PCIE_TX_P610
PCIE_TX_N710PCIE_TX_P710
PCIE_RX_N210PCIE_RX_P210
PCIE_RX_N310PCIE_RX_P310
PCIE_RX_N410PCIE_RX_P410
PCIE_RX_N510PCIE_RX_P510
PCIE_RX_N610PCIE_RX_P610
PCIE_RX_N710PCIE_RX_P710
PCIE_TX_N110PCIE_TX_P110
PCIE_RX_N110PCIE_RX_P110
PCIE_TX_N010PCIE_TX_P010
PCIE_RX_N010PCIE_RX_P010
PCIE_REFCLK_QR0_P39PCIE_REFCLK_QR0_N39
CLK_ENET_FPGA_N40CLK_ENET_FPGA_P40
ENETA_TX_N11ENETA_TX_P11
ENETA_RX_P11ENETA_RX_N11
ENETB_TX_N12ENETB_TX_P12
ENETB_RX_P12ENETB_RX_N12
FBGBTCLK1M2CN18FBGBTCLK1M2CP18
REFCLK1_FMCB_N40REFCLK1_FMCB_P40
FBD10C2MN43FBD10C2MP43
FBD10M2CP18FBD10M2CN18
FBD11C2MN18FBD11C2MP18
FBD11M2CP18FBD11M2CN18
FBD12C2MN43FBD12C2MP43
FBD12M2CP18FBD12M2CN18
FBD13C2MN18FBD13C2MP18
FBD13M2CP18FBD13M2CN18
FBD14C2MN18FBD14C2MP18
FBD14M2CP18FBD14M2CN18
FBD15C2MN43FBD15C2MP43
FBD15M2CP43FBD15M2CN43
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B8 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B8 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B8 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
PCIE Hard CoreChannel 0, 1
Tranceiver 1E BanK
A10SOC_1517
U23F
REFCLK_GXBL1E_CHTPAE29
REFCLK_GXBL1E_CHTNAE28
GXBL1E_TX_CH5NAF38
GXBL1E_TX_CH5PAF39
GXBL1E_RX_CH5N, GXBL1E_REFCLK5NAD30
GXBL1E_RX_CH5P, GXBL1E_REFCLK5PAD31
GXBL1E_TX_CH4NAG36
GXBL1E_TX_CH4PAG37
GXBL1E_RX_CH4N, GXBL1E_REFCLK4NAE32
GXBL1E_RX_CH4P, GXBL1E_REFCLK4PAE33
GXBL1E_TX_CH3NAH38
GXBL1E_TX_CH3PAH39
GXBL1E_RX_CH3N, GXBL1E_REFCLK3NAF34
GXBL1E_RX_CH3P, GXBL1E_REFCLK3PAF35
GXBL1E_TX_CH2NAJ36
GXBL1E_TX_CH2PAJ37
GXBL1E_RX_CH2N, GXBL1E_REFCLK2NAF30
GXBL1E_RX_CH2P, GXBL1E_REFCLK2PAF31
GXBL1E_TX_CH1NAK38
GXBL1E_TX_CH1PAK39
GXBL1E_RX_CH1N, GXBL1E_REFCLK1NAG32
GXBL1E_RX_CH1P, GXBL1E_REFCLK1PAG33
GXBL1E_TX_CH0NAL36
GXBL1E_TX_CH0PAL37
GXBL1E_RX_CH0N, GXBL1E_REFCLK0NAH34
GXBL1E_RX_CH0P, GXBL1E_REFCLK0PAH35
REFCLK_GXBL1E_CHBPAG29
REFCLK_GXBL1E_CHBNAG28
PCIE Hard Core withChannel 2,3,4,5,6,7
Tranceiver 1F BanK
A10SOC_1517
U23E
REFCLK_GXBL1F_CHTPAA29
REFCLK_GXBL1F_CHTNAA28
GXBL1F_TX_CH5NY38
GXBL1F_TX_CH5PY39
GXBL1F_RX_CH5N, GXBL1F_REFCLK5NY34
GXBL1F_RX_CH5P, GXBL1F_REFCLK5PY35
GXBL1F_TX_CH4NAA36
GXBL1F_TX_CH4PAA37
GXBL1F_RX_CH4N, GXBL1F_REFCLK4NAA32
GXBL1F_RX_CH4P, GXBL1F_REFCLK4PAA33
GXBL1F_TX_CH3NAB38
GXBL1F_TX_CH3PAB39
GXBL1F_RX_CH3N, GXBL1F_REFCLK3NAB34
GXBL1F_RX_CH3P, GXBL1F_REFCLK3PAB35
GXBL1F_TX_CH2NAC36
GXBL1F_TX_CH2PAC37
GXBL1F_RX_CH2N, GXBL1F_REFCLK2NAB30
GXBL1F_RX_CH2P, GXBL1F_REFCLK2PAB31
GXBL1F_TX_CH1NAD38
GXBL1F_TX_CH1PAD39
GXBL1F_RX_CH1N, GXBL1F_REFCLK1NAC32
GXBL1F_RX_CH1P, GXBL1F_REFCLK1PAC33
GXBL1F_TX_CH0NAE36
GXBL1F_TX_CH0PAE37
GXBL1F_RX_CH0N, GXBL1F_REFCLK0NAD34
GXBL1F_RX_CH0P, GXBL1F_REFCLK0PAD35
REFCLK_GXBL1F_CHBPAC29
REFCLK_GXBL1F_CHBNAC28
Tranceiver 1G BanK
A10SOC_1517
U23D
REFCLK_GXBL1G_CHTPU29
REFCLK_GXBL1G_CHTNU28
GXBL1G_TX_CH5NP38
GXBL1G_TX_CH5PP39
GXBL1G_RX_CH5N, GXBL1G_REFCLK5NT34
GXBL1G_RX_CH5P, GXBL1G_REFCLK5PT35
GXBL1G_TX_CH4NR36
GXBL1G_TX_CH4PR37
GXBL1G_RX_CH4N, GXBL1G_REFCLK4NU32
GXBL1G_RX_CH4P, GXBL1G_REFCLK4PU33
GXBL1G_TX_CH3NT38
GXBL1G_TX_CH3PT39
GXBL1G_RX_CH3N, GXBL1G_REFCLK3NV30
GXBL1G_RX_CH3P, GXBL1G_REFCLK3PV31
GXBL1G_TX_CH2NU36
GXBL1G_TX_CH2PU37
GXBL1G_RX_CH2N, GXBL1G_REFCLK2NV34
GXBL1G_RX_CH2P, GXBL1G_REFCLK2PV35
GXBL1G_TX_CH1NV38
GXBL1G_TX_CH1PV39
GXBL1G_RX_CH1N, GXBL1G_REFCLK1NW32
GXBL1G_RX_CH1P, GXBL1G_REFCLK1PW33
GXBL1G_TX_CH0NW36
GXBL1G_TX_CH0PW37
GXBL1G_RX_CH0N, GXBL1G_REFCLK0NY30
GXBL1G_RX_CH0P, GXBL1G_REFCLK0PY31
REFCLK_GXBL1G_CHBPW29
REFCLK_GXBL1G_CHBNW28
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
RXSMA Connector Interface
SMA ConnectorInterface
DP & SDI & FMCA XCVRs & SMA XCVR
Application
SMA
FMC A Slot DPTransceiver [0:9]
SDI
Channel (Bank, number)
(1I,5)
(1H,0);(1H,1);(1H,2);(1H,3];(1H,4);(1H,5);(1I,0);(1I,1);(1I,2);(1I,3);
(1J,5)
Display Port (1J,0);(1J,1);(1J,2);(1J,3)
SMA_XCVR_RX_C_P
SMA_XCVR_RX_C_N
SMA_XCVR_RX_NSMA_XCVR_RX_P
SMA_XCVR_TX_NSMA_XCVR_TX_P
REFCLK_SDI_P39REFCLK_SDI_N39
REFCLK_DP_P40REFCLK_DP_N40
SDI_RX_N16SDI_RX_P16
SDI_TX_N16SDI_TX_P16
FAGBTCLK0M2CP17FAGBTCLK0M2CN17
FAGBTCLK1M2CP17FAGBTCLK1M2CN17
FAD0M2CN17FAD0M2CP17
FAD0C2MN17FAD0C2MP17
FAD1M2CN17FAD1M2CP17
FAD1C2MN17FAD1C2MP17
FAD2M2CN17FAD2M2CP17
FAD2C2MN17FAD2C2MP17
FAD3M2CN17FAD3M2CP17
FAD3C2MN17FAD3C2MP17
FAD4M2CN17FAD4M2CP17
FAD4C2MN17FAD4C2MP17
FAD5M2CN17FAD5M2CP17
FAD5C2MN17FAD5C2MP17
LMK_FMCCLK_P41LMK_FMCCLK_N41
REFCLK_SMA_P40REFCLK_SMA_N40
FAD6M2CN17FAD6M2CP17
FAD6C2MN17FAD6C2MP17
FAD7M2CN17FAD7M2CP17
FAD7C2MN17FAD7C2MP17
FAD8M2CN17FAD8M2CP17
FAD8C2MN17FAD8C2MP17
FAD9M2CN17FAD9M2CP17
FAD9C2MN17FAD9C2MP17
DP_ML_LANE_N115
DP_ML_LANE_N015DP_ML_LANE_P015
DP_ML_LANE_N215DP_ML_LANE_P215
DP_ML_LANE_P115
DP_ML_LANE_N315DP_ML_LANE_P315
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B9 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B9 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B9 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
J61
2 3 4 5
J121
2 3 4 5
Tranceiver 1J BanK
A10SOC_1517
U23A
RREF_TLA28
REFCLK_GXBL1J_CHTPE29
REFCLK_GXBL1J_CHTNE28
GXBL1J_TX_CH5NA32
GXBL1J_TX_CH5PA33
GXBL1J_RX_CH5N, GXBL1J_REFCLK5NB30
GXBL1J_RX_CH5P, GXBL1J_REFCLK5PB31
GXBL1J_TX_CH4NC32
GXBL1J_TX_CH4PC33
GXBL1J_RX_CH4N, GXBL1J_REFCLK4ND30
GXBL1J_RX_CH4P, GXBL1J_REFCLK4PD31
GXBL1J_TX_CH3NB34
GXBL1J_TX_CH3PB35
GXBL1J_RX_CH3N, GXBL1J_REFCLK3NE32
GXBL1J_RX_CH3P, GXBL1J_REFCLK3PE33
GXBL1J_TX_CH2NA36
GXBL1J_TX_CH2PA37
GXBL1J_RX_CH2N, GXBL1J_REFCLK2NF30
GXBL1J_RX_CH2P, GXBL1J_REFCLK2PF31
GXBL1J_TX_CH1NB38
GXBL1J_TX_CH1PB39
GXBL1J_RX_CH1N, GXBL1J_REFCLK1NG32
GXBL1J_RX_CH1P, GXBL1J_REFCLK1PG33
GXBL1J_TX_CH0NC36
GXBL1J_TX_CH0PC37
GXBL1J_RX_CH0N, GXBL1J_REFCLK0NH30
GXBL1J_RX_CH0P, GXBL1J_REFCLK0PH31
REFCLK_GXBL1J_CHBPG29
REFCLK_GXBL1J_CHBNG28
J211
2 3 4 5
C42 0.1uF
Tranceiver 1I BanK
A10SOC_1517
U23B
REFCLK_GXBL1I_CHTPJ29
REFCLK_GXBL1I_CHTNJ28
GXBL1I_TX_CH5ND34
GXBL1I_TX_CH5PD35
GXBL1I_RX_CH5N, GXBL1I_REFCLK5NH34
GXBL1I_RX_CH5P, GXBL1I_REFCLK5PH35
GXBL1I_TX_CH4ND38
GXBL1I_TX_CH4PD39
GXBL1I_RX_CH4N, GXBL1I_REFCLK4NJ32
GXBL1I_RX_CH4P, GXBL1I_REFCLK4PJ33
GXBL1I_TX_CH3NE36
GXBL1I_TX_CH3PE37
GXBL1I_RX_CH3N, GXBL1I_REFCLK3NK30
GXBL1I_RX_CH3P, GXBL1I_REFCLK3PK31
GXBL1I_TX_CH2NF34
GXBL1I_TX_CH2PF35
GXBL1I_RX_CH2N, GXBL1I_REFCLK2NK34
GXBL1I_RX_CH2P, GXBL1I_REFCLK2PK35
GXBL1I_TX_CH1NF38
GXBL1I_TX_CH1PF39
GXBL1I_RX_CH1N, GXBL1I_REFCLK1NL32
GXBL1I_RX_CH1P, GXBL1I_REFCLK1PL33
GXBL1I_TX_CH0NG36
GXBL1I_TX_CH0PG37
GXBL1I_RX_CH0N, GXBL1I_REFCLK0NM30
GXBL1I_RX_CH0P, GXBL1I_REFCLK0PM31
REFCLK_GXBL1I_CHBPL29
REFCLK_GXBL1I_CHBNL28
C43 0.1uF
Tranceiver 1H BanK
A10SOC_1517
U23C
REFCLK_GXBL1H_CHTPN29
REFCLK_GXBL1H_CHTNN28
GXBL1H_TX_CH5NH38
GXBL1H_TX_CH5PH39
GXBL1H_RX_CH5N, GXBL1H_REFCLK5NM34
GXBL1H_RX_CH5P, GXBL1H_REFCLK5PM35
GXBL1H_TX_CH4NJ36
GXBL1H_TX_CH4PJ37
GXBL1H_RX_CH4N, GXBL1H_REFCLK4NN32
GXBL1H_RX_CH4P, GXBL1H_REFCLK4PN33
GXBL1H_TX_CH3NK38
GXBL1H_TX_CH3PK39
GXBL1H_RX_CH3N, GXBL1H_REFCLK3NP30
GXBL1H_RX_CH3P, GXBL1H_REFCLK3PP31
GXBL1H_TX_CH2NL36
GXBL1H_TX_CH2PL37
GXBL1H_RX_CH2N, GXBL1H_REFCLK2NP34
GXBL1H_RX_CH2P, GXBL1H_REFCLK2PP35
GXBL1H_TX_CH1NM38
GXBL1H_TX_CH1PM39
GXBL1H_RX_CH1N, GXBL1H_REFCLK1NR32
GXBL1H_RX_CH1P, GXBL1H_REFCLK1PR33
GXBL1H_TX_CH0NN36
GXBL1H_TX_CH0PN37
GXBL1H_RX_CH0N, GXBL1H_REFCLK0NT30
GXBL1H_RX_CH0P, GXBL1H_REFCLK0PT31
REFCLK_GXBL1H_CHBPR29
REFCLK_GXBL1H_CHBNR28
R40792.00k
J11
2 3 4 5
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCI Express GEN3 X 8 Connector
75-ohm to 100-ohm XCVR traces.
PCIE_TX_CP6PCIE_TX_CN6
PCIE_TX_CP7PCIE_TX_CN7
PCIE_TX_CN5PCIE_TX_CP5
PCIE_TX_CN4PCIE_TX_CP4
PCIE_TX_CP2PCIE_TX_CN2
PCIE_TX_CP3PCIE_TX_CN3
PCIE_TX_CN1PCIE_TX_CP1
PCIE_TX_CP0PCIE_TX_CN0
PCIE_12V49
PCIE_DC_3V372
PCIE_aux3V369
PCIE_RX_P0 8PCIE_RX_N0 8
PCIE_RX_P1 8PCIE_RX_N1 8
PCIE_RX_P2 8PCIE_RX_N2 8
PCIE_RX_P3 8PCIE_RX_N3 8
PCIE_RX_P4 8PCIE_RX_N4 8
PCIE_RX_P5 8PCIE_RX_N5 8
PCIE_RX_P6 8PCIE_RX_N6 8
PCIE_RX_P7 8PCIE_RX_N7 8
PCIE_TX_P08PCIE_TX_N08
PCIE_TX_P18PCIE_TX_N18
PCIE_TX_P28PCIE_TX_N28
PCIE_TX_P38PCIE_TX_N38
PCIE_TX_P48PCIE_TX_N48
PCIE_TX_P58PCIE_TX_N58
PCIE_TX_P68PCIE_TX_N68
PCIE_TX_P78PCIE_TX_N78
PCIE_REFCLK_SYN_P 39PCIE_REFCLK_SYN_N 39
PCIE_WAKE_N36
PCIE_PRSNT2n35,36,37
PCIE_PERSTn 35
PCIE_TCK 37PCIE_TDI 37
PCIE_TRSTN37PCIE_TMS 37
PCIE_TDO 37EXTA_SDA13,17,45
EXTA_SCL45
PCIE_12V
PCIE_DC_3V3
PCIE_12V
PCIE_DC_3V3
PCIE_aux3V3
PCIE_12V PCIE_DC_3V3PCIE_aux3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B10 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B10 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B10 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C1530 0.22uF
C15500.1uF
C1535 0.22uF
R4166 DNI
C1540 0.22uF
C1545 0.22uF
C15470.1uF
C15560.1uF
C1531 0.22uF
C1555
100uF6.3V
C1536 0.22uF
C1541 0.22uF
C15490.1uF
R4163 4.7K
C154622uF
C1532 0.22uF
C1537 0.22uF
C1542 0.22uF
C15480.1uF
C15540.1uF
C15510.1uF
C1533 0.22uF
C1538 0.22uF
C15520.1uF
C1543 0.22uF
C15530.1uF
KEY
X4
X8
X1
J57
PCIE-098-02-F-D-TH
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2_N_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2_N_X4B31
GNDB32
PET4PB33
PET4NB34
GNDB35
GNDB36
PET5PB37
PET5NB38
GNDB39
GNDB40
PET6PB41
PET6NB42
GNDB43
GNDB44
PET7PB45
PET7NB46
GNDB47
PRSNT2_N_X8B48
GNDB49
PRSNT1_NA1
+12VA2
+12VA3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
RSVD5A33
GNDA34
PER4PA35
PER4NA36
GNDA37
GNDA38
PER5PA39
PER5NA40
GNDA41
GNDA42
PER6PA43
PER6NA44
GNDA45
GNDA46
PER7PA47
PER7NA48
GNDA49
C1534 0.22uF
R4165 DNI
C1539 0.22uF
C1544 0.22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet XCVR
SGMII Mode (default)
Place near 88E1111 PHY
88E1111-B2-CAA1C000 EOL88E1111-B2-NDC2C000 Replacement
DVDD = 1.0VDVDD = 1.2V
ENET_DVDD = 1.0V/0.207A
ENETA_LED_RX
ENETA_LED_TX
ENETA_LED_LINK100
ENETA_LED_LINK1000
ENETA_2p5V_MDCENETA_2p5V_INTn
ENETA_2p5V_RESETn
ENETA_RSET
ENETA_2p5V_MDIO
ENETA_LED_LINK10
AMDI_P0AMDI_N0AMDI_P1AMDI_N1AMDI_P2AMDI_N2AMDI_P3AMDI_N3
ENETA_TXC_PENETA_TXC_N
ENETA_RXC_PENETA_RXC_N
IO_3V3 69IO_2V5 36,68IO_5V 50
ENETA_MDC 27ENETA_MDIO 27
ENETA_INTn 36ENETA_RESETn 36
ENETA_TX_P 8
ENETA_TX_N 8
ENETA_RX_P 8ENETA_RX_N 8
ENETA_DVDD
ENETA_DVDD
ENETA_DVDD
IO_3V3IO_2V5IO_5V
IO_2V5
IO_2V5
IO_5V
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B11 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B11 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B11 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C235
0.1uF
D3
GREEN_LED
C320.1uF
R336240
C190
2.2uF
R311 4.7K
C222
0.1uF
C252
0.1uF
U8B
88E1111
NC113
VSS97
DVDD1
DVDD6
DVDD10
DVDD15
DVDD57
DVDD62
DVDD67
DVDD71
DVDD85
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
VD
DO
X26
VD
DO
X48
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H72
VD
DO
H66
VD
DO
H52
NC251
C310.1uF
R309 4.7K
C236
0.1uF
C200 0.01uF
C191
22uF
R4810K
C251
0.1uF
R313 49.9
C300.1uF
C6
10uF
C250
0.1uF
C2425 0.01uF
C221
0.1uF
R27 15K
D1
GREEN_LED
R3350
C224
0.1uF
C183
1uF
C290.1uF
U2
LTC3025-1
BIAS1
GND2
ADJ5
OUT4
SHDN6
EP_GND7
IN3
C249
0.1uF
R353240
R3320
C234
0.1uF
J2
7499111001A
TD0_P1
TD0_N2
TD1_P3
TD1_N6
TD2_P4
TD2_N5
TD3_P7
TD3_N8
VCC9
GND10
GN
D_T
AB
11G
ND
_TA
B12
R314 49.9
C266
0.1uF
R312 1.00K
R310 4.7K
R38 49.9
R359240
U6
25.00MHz
VCC4
GND2
OUT3
EN1
GMII/MII/TBI INTERFACE
TEST
SGMII INTERFACE
JTAG
MDI INTERFACE
MGMT
U8A
88E1111
COMA27
RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22
XTAL155
XTAL254
VSSC53
RSET30
SEL_FREQ56
MDI3_P42
MDI3_N43
MDI2_P39
MDI2_N41
MDI1_P33
MDI1_N34
MDI0_P29
MDI0_N31
MDIO24
MDC25
INT_N23
HSDAC_P37
HSDAC_N38
GTX_CLK8
TX_CLK4
TX_EN9
RXCLK2
RX_DV94
CRS84
COL83
S_CLK_P79
S_CLK_N80
S_IN_P82
S_IN_N81
S_OUT_P77
S_OUT_N75
LED_TX68
LED_RX69
LED_DUPLEX70
LED_LINK100073
LED_LINK10074
LED_LINK1076
RXD095
RXD192
RXD293
RXD391
RXD490
RXD589
RXD687
RXD786
RX_ER3
TXD011
TXD112
TXD214
TXD316
TXD417
TXD518
TXD619
TXD720
TX_ER7
TMS46 TDO50 TDI44 TCK49 TRST_N47
C223
0.1uF
C265
0.1uF
C213
0.01uF
R37 49.9
R346240
R3284.99K
D4
GREEN_LED
D7
GREEN_LED
C199 0.01uFR35 49.9
R345240
R34 49.9
D9
GREEN_LED
R36 49.9
R3294.7K
R21
10K
C7 0.01uF
R33 49.9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet XCVR
SGMII Mode (default)
Place near 88E1111 PHY
88E1111-B2-CAA1C000 EOL88E1111-B2-NDC2C000 Replacement
DVDD = 1.0VDVDD = 1.2V
ENET_DVDD = 1.0V/0.207A
ENETB_LED_RX
ENETB_LED_TX
ENETB_LED_LINK100
ENEB_LED_LINK1000
ENETB_2p5V_MDCENETB_2p5V_INTn
ENETB_2p5V_RESETn
ENETB_RSET
ENETB_2p5V_MDIO
ENETB_LED_LINK10
BMDI_P0BMDI_N0BMDI_P1BMDI_N1BMDI_P2BMDI_N2BMDI_P3BMDI_N3
ENETB_TXC_PENETB_TXC_NENETB_RXC_PENETB_RXC_N
IO_1V8 36,37,68IO_3V3 69IO_2V5 36,68IO_5V 50
ENETB_MDC 27ENETB_MDIO 27
ENETB_INTn 36ENETB_RESETn 36
ENETB_TX_P 8ENETB_TX_N 8
ENETB_RX_P 8ENETB_RX_N 8
ENETB_DVDD
ENETB_DVDD
ENETB_DVDD
IO_1V8
IO_3V3IO_2V5IO_5V
IO_2V5
IO_2V5
IO_5V
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B12 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B12 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B12 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R42 49.9
U3
LTC3025-1
BIAS1
GND2
ADJ5
OUT4
SHDN6
EP_GND7
IN3
R308 49.9
R358240
R343240
D10
GREEN_LED
C212
0.01uF
J3
7499111001A
TD0_P1
TD0_N2
TD1_P3
TD1_N6
TD2_P4
TD2_N5
TD3_P7
TD3_N8
VCC9
GND10
GN
D_T
AB
11G
ND
_TA
B12
D8
GREEN_LED
R40 49.9
R307 49.9
R4910K
R304 4.7K
C35 0.1uF
C189
22uF
C264
0.1uF
GMII/MII/TBI INTERFACE
TEST
SGMII INTERFACE
JTAG
MDI INTERFACE
MGMT
U9A
88E1111
COMA27
RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22
XTAL155
XTAL254
VSSC53
RSET30
SEL_FREQ56
MDI3_P42
MDI3_N43
MDI2_P39
MDI2_N41
MDI1_P33
MDI1_N34
MDI0_P29
MDI0_N31
MDIO24
MDC25
INT_N23
HSDAC_P37
HSDAC_N38
GTX_CLK8
TX_CLK4
TX_EN9
RXCLK2
RX_DV94
CRS84
COL83
S_CLK_P79
S_CLK_N80
S_IN_P82
S_IN_N81
S_OUT_P77
S_OUT_N75
LED_TX68
LED_RX69
LED_DUPLEX70
LED_LINK100073
LED_LINK10074
LED_LINK1076
RXD095
RXD192
RXD293
RXD391
RXD490
RXD589
RXD687
RXD786
RX_ER3
TXD011
TXD112
TXD214
TXD316
TXD417
TXD518
TXD619
TXD720
TX_ER7
TMS46 TDO50 TDI44 TCK49 TRST_N47
R334240
R3310
C218
0.1uF
C263
0.1uF
R344240
R305 4.7K
C233
0.1uF
C197 0.01uF
C34 0.1uF
C232
0.1uF
C217
0.1uF
C182
1uF
C9 0.01uF
C219
0.1uF
C248
0.1uF
C33 0.1uF
D2
GREEN_LED
R28 15K
R306 1.00K
R41 49.9
U9B
88E1111
NC113
VSS97
DVDD1
DVDD6
DVDD10
DVDD15
DVDD57
DVDD62
DVDD67
DVDD71
DVDD85
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
VD
DO
X26
VD
DO
X48
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H72
VD
DO
H66
VD
DO
H52
NC251
R39 49.9
R43 49.9
D6
GREEN_LED
C188
2.2uF
R352240
R3224.99K
U7
25.00MHz
VCC4
GND2
OUT3
EN1
R3330
C231
0.1uF
C36 0.1uF
D5
GREEN_LED
R303 4.7K
C205
0.1uF
C220
0.1uF
C8
10uF
R44 49.9
C211
0.1uF
C247
0.1uF
R22
10K
R3234.7K
C196 0.01uF
C195 0.01uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP) Transceiver Cage & Connector 1I2C Address is 1010000 or 1010001.
Optical (SFP+) Transceiver Cage & Connector 0
Small Form Factor Pluggable Plus (SFP+) Port A
SFPB_VCCR
SFPB_VCCTIO_3V369
SFPA_TX_P 7
SFPA_RX_P7
SFPA_TX_N 7
SFPA_RX_N7SFPA_LOS 35SFPA_TXFAULT 35
SFPA_TXDISABLE35SFPA_RATESEL035SFPA_RATESEL135
EXTA_SCL45SFPA_MOD0_PRSNTn35
EXTA_SDA10,17,45
SFPA_VCCT
SFPA_VCCR
GND_CAGE GND_CAGE
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B13 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B13 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B13 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C270
10uF
C298
10uF
C269
0.1uF
J7
SFP+_AND_CAGE<Agile Part Number>
CAGE_GND21
CAGE_GND22
CAGE_GND23
CAGE_GND24
CAGE_GND25
CAGE_GND26
CAGE_GND27
CAGE_GND28
CAGE_GND29
CAGE_GND30
CAGE_GND31
CAGE_GND32
CAGE_GND33
CAGE_GND34
VEET1
VEET17
VEET20
RS19
VEER10
VEER11
VEER14
TD_P18
TD_N19
RX_LOS8
TX_FAULT2
VCCT16
VCCR15
RD_P13
RD_N12
TX_DISABLE3
RS07
MOD_ABS6
SCL5
SDA4
CAGE_GND35
CAGE_GND36
CAGE_GND37
CAGE_GND38
CAGE_GND39
CAGE_GND40
MH141
MH242
B5
SFP+_CAGE
L20 1.0uH
C291
0.1uF
L19 1.0uHC290
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP+) Transceiver Cage & Connector 0
Small Form Factor Pluggable Plus (SFP+) Port B
Optical (SFP) Transceiver Cage & Connector 1I2C Address is 1010000 or 1010001.
SFPB_VCCR
SFPB_VCCTIO_3V369
SFPB_RX_P7SFPB_RX_N7
SFPB_TXDISABLE35SFPB_RATESEL035SFPB_RATESEL135
EXTB_SCL18,45SFPB_MOD0_PRSNTn35
SFPB_TX_P 7SFPB_TX_N 7
SFPB_LOS 35SFPB_TXFAULT 35
EXTB_SDA18,45
SFPB_VCCT
SFPB_VCCR
GND_CAGE GND_CAGE
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B14 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B14 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B14 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
L17 1.0uHC288
0.1uFC268
10uF
C297
10uF
C267
0.1uF
J8
SFP+_AND_CAGE
CAGE_GND21
CAGE_GND22
CAGE_GND23
CAGE_GND24
CAGE_GND25
CAGE_GND26
CAGE_GND27
CAGE_GND28
CAGE_GND29
CAGE_GND30
CAGE_GND31
CAGE_GND32
CAGE_GND33
CAGE_GND34
VEET1
VEET17
VEET20
RS19
VEER10
VEER11
VEER14
TD_P18
TD_N19
RX_LOS8
TX_FAULT2
VCCT16
VCCR15
RD_P13
RD_N12
TX_DISABLE3
RS07
MOD_ABS6
SCL5
SDA4
CAGE_GND35
CAGE_GND36
CAGE_GND37
CAGE_GND38
CAGE_GND39
CAGE_GND40
MH141
MH242
B6
SFP+_CAGE
L18 1.0uH
C289
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Display Port (x4)
Auxilary Channel -> Bidirctional LVDS 1Mbps/(720Mbps optional).
Quartus IO Standard = BLVDS TX -> DIFF SSTL-1.8 RX -> LVDSFogBugz Case 135234 & 147387
1) TX uses diff sstl18 configuration, which is able to meet peak-to-peak differential voltage and common mode voltage spec for DP.2) RX uses LVDS input, but user need to ensure pin voltage at NF receiver end is <1.9v. a. If the channel is AC couple, then user need to choose the correct Vbias_RX so that Vpin < 1.9v. The spec is 0 – 2v, which is quitewide. Selecting Vbias_Rx at 2v region will cause NF device to have reliability issue. b. If the channel is DC couple, user need to make sure TX common mode voltage + ground reference differences between Tx and Rx will notcause Vpin for NF to be higher than 1.9v.
Usually 3.3V forDP, but Arria 10is 1.8V LVDS.
0.5A maximum current
DP_HOT_PLUG
DP_ML_LANE_P0DP_ML_LANE_N0
DP_ML_LANE_P1DP_ML_LANE_N1
DP_ML_LANE_P2DP_ML_LANE_N2
DP_ML_LANE_P3DP_ML_LANE_N3
DP_AUX_CPDP_AUX_CN
DP_AUX_CHR_PDP_AUX_CHR_N
DP_AUX_CP
DP_3p3V_CONFIG2
VBIAS_DP
DP_ML_LANE_CP1DP_ML_LANE_CN1
DP_ML_LANE_CN3DP_ML_LANE_CP3
DP_ML_LANE_CP2DP_ML_LANE_CN2
DP_ML_LANE_CN0DP_ML_LANE_CP0
DP_RTN
DP_3p3V_CONFIG1
DP_AUX_CHB_PDP_AUX_CHB_N
IO_1V8 36,37,68IO_3V3 69
DP_ML_LANE_P0 9DP_ML_LANE_N0 9
DP_ML_LANE_P1 9DP_ML_LANE_N1 9
DP_ML_LANE_P2 9DP_ML_LANE_N2 9
DP_ML_LANE_P3 9DP_ML_LANE_N3 9
DP_CONFIG136DP_CONFIG236
DP_HOT_PLUG36
DP_ON36
DP_OCn36
DP_AUX_CH_P 27DP_AUX_CH_N 27
DP_AUX_DE 36
DP_AUX_D 36
DP_AUX_REn 36
DP_AUX_R 36
GND_DP
GND_DP GND_DP
IO_1V8
IO_3V3IO_3V3
IO_1V8
DP_3V3
IO_3V3
DP_3V3
DP_3V3
DP_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B15 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B15 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B15 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C1330.1uF
R224 100K
C8784.7nF
C856 0.1uFC855 0.1uF
R225 100K
R211DNI
C137 0.1uF
C893
2.2uF
R793 0
J46
0472720024
ML_LANE_0P1
ML_LANE_0N3
GND5
ML_LANE_2P7
ML_LANE_2N9
GND11
GND2
ML_LANE_1P4
ML_LANE_1N6
GND8
ML_LANE_3P10
ML_LANE_3N12
CONFIG214 CONFIG113
AUX_CH_P15
GND16
HP_DETECT18
DP_PWR20
AUX_CH_N17
RTN19
MH121
MH222 MH3
23
MH424
C848
10uF
R218 22.0
R212DNI
R22010K
C854 0.1uF
R806 100K
VDD GND IO6 IO5
IO3 IO4IO2IO1
D37
824016467
4
81 2 3
56
R7651M
R21949.9
C888
0.1uF
C859 0.1uF
C1340.1uF
U27
DNI
4D
3DE
1R
2RE_n
6 A
7 B
GND5
VCC8
C847
0.1uF
U28
TPD2EUSB30D-
2D+1
GND3
C2453 0.1uF
R750DNI
C138 0.1uF
R21649.9
U71
MAX14523B
IN5
OUT4
ON7 GND
8FLAG2
NC26
SETI3NC1
1
GND_PAD9
R22310K
R790 1M
R792 100K
C830
0.1uF
C860 0.1uF
C858 0.1uFR791 1M
VDD GND IO6 IO5
IO3 IO4IO2IO1
D38
824016467
4
81 2 3
56R217 22.0
R802
280K
1%
C857 0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
SDI Cable Driver, Equalizer, and SMB
75 Ohm Single-Ended Impedance
MODE_SEL = 0 -> HARDWARE MODE
DISABLE SDO1 ->
Layout Notes (M23428) SDI Cable Driver:- The RSET resistor should be located close to pin 5. - Remove GND under pin 5 and the RSET resistor.- The 49.9-ohm resistors should be placed close to device pins 16 and 1 (SDIP/SDIN).
Layout Notes (M22544) SDI Cable Equalizer:- The AGC 33nF capacitor should be located close to the device pins 8 and 9 (AGC+/AGC-). - Clear GND under the AGC 33nF capacitor.
M22468 Pin compatible to:M22428 (Gen2 3G/6G SDI Cable Driver)M23428 (12G Cable Driver)
M22544 Pin Compatible to:M23544 (12G EQ + Reclocker)
Layout Notes:DNI for resistors andcapacitors for GEN2 devices. Minimize stubs in layout.
75 Ohm Single-Ended Impedance
100 Ohm Differential Impedance
100 Ohm Differential Impedance
1uF and 10uF for 12G
75-ohm for 12G
4.7uF for 12G
4.7uF for 12G
DNI for 12G
Pull-down for 12G
ENABLE Hardware Mode
SDI_IN_P1
SDI_EQIN_P1SDI_EQIN_N1
SDI_EQIN_P
SDI_EQIN_N
SDO_NSDO_P
SDI_TXCAP_PSDI_TXCAP_N
MODE_SEL
MF3_xSD
MUTEREF
SDI_TXBNC_P
SDI_TXDRV_PSDI_TXDRV_N
SDI_TX_RSET
MF1_AUTO_SLEEPMF2_MUTE
MF0_BYPASS
IO_2V5 36,68
SDI_TX_P9
SDI_TX_N9
SDI_TX_SD_HDn36
SDI_MF2_MUTE_SCLK36
SDI_RX_P 9SDI_RX_N 9
SDI_SPI_CS0 36SDI_SPI_MOSI 36SDI_SPI_M1SO36
SDI_SPI_CLK 36
SDI_MF3_MOSI36
SDI_MF4_status36
SDI_MF0_BYPASS_present36
SDI_xCS_CS36
SDI_MF1_SLEEP_MISO36
SDI_XHD_RATE36
SDI_AVDD
2.5V_SDI
2.5V_SDI
2.5V_SDI
SDI_AVDD
IO_2V5
IO_2V5
IO_2V5
SDI_AVDD
2.5V_SDI
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B16 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B16 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B16 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C871
0.01uF
R753 0
C158 4.7uF
C156 10uF
R221DNI
R749 10K
SDI CABLE EQUALIZERU30
M23544VEE_PAD
25
SD_xHD9
SDO1N17
SDO0P15
MUTEREF11
MF322
MF48
SDO1P18
MODE_SEL6
SDO0N14
SDIP3
MF010
xCS13
MF119
VCC20
MF221
SDO1_DISABLE7
VEE5VICM2
VCC24
VEE1
VEE23VEE16VEE12
SDIN4
R754 750
C853
0.1uF
C875
0.1uF
R230 DNI
C155 4.7uF
C851
0.01uF
R229 10K
C877
0.01uF
L11 120 Ohm FB
C135 4.7uF
J48
HDBNC1
2 3 4 5
C136 4.7uF
R226 10K
C146 4.7uF
J49
HDBNC1
2345
R222 49.9
L12120 Ohm FB
C159 4.7uF
R247 75
C846
0.1uF
C852
0.1uF
C876
0.01uF
U29
M23428
SDIP16
SDIN1
SDO1N12SDO1P13
SDO2P11
SDO2N10
SD_xHD9
MODE_SEL15 MF0
4
MF16
MF28
MF314
AVDD12
AVDD27
AVSS3
GNDPAD17
RSET5
R236 10K
R248 75
L13 1nH1 2
C154 4.7uF
R237 DNI
D39
GREEN_LED
R764 10K
C145 4.7uF
R23575
C157 1uF
R748 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FMC (V57.1) PORT A
I2C ADDRESS:b'10100010
FAPG_C2M
FMCA_DC_3V372
FMCA_aux3V365 FMCAVADJ 66
FMCA_12V49
FAD0C2MP9FAD0C2MN9FAD1C2MP9FAD1C2MN9FAD2C2MP9FAD2C2MN9FAD3C2MP9FAD3C2MN9FAD4C2MP9FAD4C2MN9
FAD5C2MP9FAD5C2MN9FAD6C2MP9FAD6C2MN9FAD7C2MP9FAD7C2MN9FAD8C2MP9FAD8C2MN9FAD9C2MP9FAD9C2MN9
FAD0M2CP 9FAD0M2CN 9FAD1M2CP 9FAD1M2CN 9FAD2M2CP 9FAD2M2CN 9FAD3M2CP 9FAD3M2CN 9
FAD5M2CP 9FAD5M2CN 9FAD6M2CP 9FAD6M2CN 9FAD7M2CP 9FAD7M2CN 9FAD8M2CP 9FAD8M2CN 9FAD9M2CP 9FAD9M2CN 9
FAD4M2CP 9FAD4M2CN 9
FALAP028FALAN028FALAP143FALAN143FALAP228FALAN228FALAP328FALAN328
FALAP428FALAN428FALAP543FALAN543FALAP628FALAN628FALAP728FALAN728
FALAP828FALAN828FALAP928FALAN928FALAP1028FALAN1028FALAP1128FALAN1128
FALAP1228FALAN1228FALAP1328FALAN1328FALAP1428FALAN1428FALAP1528FALAN1528
FALAP16 28FALAN16 28FALAP17 28FALAN17 28FALAP18 28FALAN18 28FALAP19 28FALAN19 28
FALAP20 28FALAN20 28FALAP21 28FALAN21 28FALAP22 29FALAN22 29FALAP23 29FALAN23 29
FALAP24 29FALAN24 29FALAP25 29FALAN25 29FALAP26 29FALAN26 29FALAP27 29FALAN27 29
FALAP28 29FALAN28 29FALAP29 29FALAN29 29FALAP30 29FALAN30 29FALAP31 29FALAN31 29FALAP32 29FALAN32 29FALAP33 29FALAN33 29
FAHBP029FAHBN029FAHBP129FAHBN129FAHBP229FAHBN229FAHBP329FAHBN329
FAHBP429FAHBN429FAHBP529FAHBN529FAHBP629FAHBN629FAHBP729FAHBN729
FAHBP829FAHBN829FAHBP929FAHBN929FAHBP1029FAHBN1029
FAHBP11 36FAHBN11 36FAHBP12 36FAHBN12 36FAHBP13 29FAHBN13 29FAHBP14 36FAHBN14 36
FAHBP15 36FAHBN15 36
FAHBP16 36FAHBN16 36FAHBP17 36FAHBN17 36FAHBP18 36FAHBN18 36
FAHBP19 36FAHBN19 36FAHBP20 36FAHBN20 36FAHBP21 36FAHBN21 36
FAHAP028FAHAN028FAHAP128FAHAN128FAHAP228FAHAN228FAHAP328FAHAN328
FAHAP428FAHAN428FAHAP528FAHAN528FAHAP628FAHAN628FAHAP728FAHAN728
FAHAP828FAHAN828FAHAP928FAHAN928FAHAP1028FAHAN1028FAHAP1128FAHAN1128
FAHAP12 28FAHAN12 28FAHAP13 28FAHAN13 28FAHAP14 28FAHAN14 28FAHAP15 28FAHAN15 28
FAHAP16 28FAHAN16 28FAHAP17 28FAHAN17 28FAHAP18 28FAHAN18 28FAHAP19 28FAHAN19 28
FAHAP20 28FAHAN20 28FAHAP21 28FAHAN21 28FAHAP22 28FAHAN22 28FAHAP23 28FAHAN23 28
FAGBTCLK0M2CP 9FAGBTCLK0M2CN 9FAGBTCLK1M2CP 9FAGBTCLK1M2CN 9
FACLK0M2CP 43FACLK0M2CN 43FACLK1M2CP 43FACLK1M2CN 43
FACLK2BIDIRP43FACLK2BIDIRN43FACLK3BIDIRP43FACLK3BIDIRN43
FACLKDIR36
FATRST 37FATMS 37FATDO 37FATDI 37FATCK 37
FAC2MPgood35
FAM2CPgood 35
FAPRSNT_N35,36,38,42
FAM2CVIO 36
FAREFBFAREFA
EXTA_SDA10,13,45EXTA_SCL45
FMCA_aux3V3
FMCA_aux3V3
FMCA_aux3V3
FMCA_DC_3V3
FMCA_12V
FMCA_12V
FAM2CVIO
FAM2CVIO
FAREFB
FAREFA
FAREFB
FAREFA
FMCAVADJ
FMCA_DC_3V3
FMCAVADJ
FMCA_DC_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B17 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B17 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B17 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
J29C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
J29F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
R5518DNI
R53811.00K
R690DNI
C5031uF
C813
10uF
C7841uF
C815
10uF
R53781.00k
C825
10uF
C814
10uF
J29A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
C816
10uF
R704DNI
J29B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
J29D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
C2388
10uF
C5021uF
R53821.00K
J29E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
R5517
100K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FMC (16 XCVRS + LAP) PORT B
FBT12PFBT12N
FBT15PFBT15N
FBR15PFBR15N
FBT10PFBT10N
FBT11P
FBT13P
FBR11P
FBR12P
FBR13P
FBT14PFBT14N
FBR14PFBR14N
FBT11N
FBT13N
FBR11N
FBR12N
FBR13N
FBR10PFBR10N
FBPG_C2M
FMCB_DC_3V372
FMCB_aux3V365
FMCB_12V49
FBD0C2MP7FBD0C2MN7FBD1C2MP7FBD1C2MN7FBD2C2MP7FBD2C2MN7FBD3C2MP7FBD3C2MN7FBD4C2MP7FBD4C2MN7
FBD5C2MP7FBD5C2MN7FBD6C2MP7FBD6C2MN7FBD7C2MP7FBD7C2MN7FBD8C2MP7FBD8C2MN7FBD9C2MP7FBD9C2MN7
FBD0M2CP 7FBD0M2CN 7FBD1M2CP 7FBD1M2CN 7FBD2M2CP 7FBD2M2CN 7FBD3M2CP 7FBD3M2CN 7
FBD5M2CP 7FBD5M2CN 7FBD6M2CP 7FBD6M2CN 7FBD7M2CP 7FBD7M2CN 7FBD8M2CP 7FBD8M2CN 7FBD9M2CP 7FBD9M2CN 7
FBD4M2CP 7FBD4M2CN 7
FBLAP030FBLAN030FBLAP143FBLAN143FBLAP230FBLAN230FBLAP330FBLAN330
FBLAP430FBLAN430FBLAP543FBLAN543FBLAP630FBLAN630FBLAP730FBLAN730
FBLAP830FBLAN830FBLAP930FBLAN930FBLAP1030FBLAN1030FBLAP1130FBLAN1130
FBLAP1230FBLAN1230FBLAP1330FBLAN1330FBLAP1430FBLAN1430FBLAP1530FBLAN1530
FBLAP16 30FBLAN16 30FBLAP17 30FBLAN17 30FBLAP18 30FBLAN18 30FBLAP19 30FBLAN19 30
FBLAP20 29FBLAN20 29FBLAP21 29FBLAN21 29FBLAP22 29FBLAN22 29FBLAP23 29FBLAN23 29
FBLAP24 29FBLAN24 29FBLAP25 29FBLAN25 29FBLAP26 29FBLAN26 29FBLAP27 29FBLAN27 29
FBLAP28 36FBLAN28 36FBLAP29 36FBLAN29 36FBLAP30 36FBLAN30 36FBLAP31 36FBLAN31 36FBLAP32 36FBLAN32 36FBLAP33 36FBLAN33 36
FBGBTCLK0M2CP 7FBGBTCLK0M2CN 7FBGBTCLK1M2CP 8FBGBTCLK1M2CN 8
FBCLK0M2CP 30FBCLK0M2CN 30FBCLK1M2CP 43FBCLK1M2CN 43
FBTRST 37FBTMS 37FBTDO 37FBTDI 37FBTCK 37
FBC2MPgood35
FBPRSNT_N35,36,38,42
EXTB_SCL14,45
FBREFA
EXTB_SDA14,45
FBHA_N20 29
FBHA_P22 29FBHA_N22 29
FBHA_P20 29
FBD12M2CP8FBD12M2CN8
FBD13M2CP8FBD13M2CN8
FBD14M2CP 8FBD14M2CN 8
FBD11C2MP8FBD11C2MN8
FBD13C2MP8FBD13C2MN8
FBD14C2MP 8FBD14C2MN 8
FBD11M2CP8FBD11M2CN8
FBD10M2CP8FBD10M2CN8
FBHA_N6M43FBHA_P6M43 FBHA_P17M 43
FBHA_N17M 43
FMB_SYNCN30FMB_SYNCP30
FMB_SYNC_CD 30FMB_SYNC_AB 30
FBHA_P21M 43FBHA_N21M 43
FBHA_P23M 43FBHA_N23M 43
FBHBP18 36FBHBN18 36
FBHBP19 36FBHBN19 36FBHBP20 36FBHBN20 36FBHBP21 36FBHBN21 36
FBM2CVIO 36
FMCBVADJ 67
FMCB_aux3V3
FMCB_aux3V3
FMCB_aux3V3
FMCB_DC_3V3
FMCB_12V
FMCB_12V
FBREFA
FBREFA
FMCBVADJ
FMCB_DC_3V3
FBM2CVIO
FBM2CVIO
FMCBVADJ
FMCB_DC_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B18 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B18 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B18 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C318 0.1uF
R53591.00k
C446
10uF
R464DNI
J19E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
C447
10uF
C393 0.1uF
C274 0.1uF
C434
10uF
J19A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
C283 0.1uF
C394 0.1uF
C301 0.1uF
C2381uF
C406 0.1uF
R5519
100K
C416 0.1uF
C358 0.1uF
R5520DNI
R457DNI
C308 0.1uF
C466
10uF
J19C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
J19D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
C4241uF
J19B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
C448
10uF
C359 0.1uF
C405
10uF
J19F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
C284 0.1uF
R53581.00k
C319 0.1uF
C313 0.1uF
C292 0.1uF
R53551.00k
C329 0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
HPS HILO DDR3/DDR4 IOs
All HPS memory IO pin assignment must be same as Quartus'
RZQ_2K
HMEM_DQS_ADDR_CMD_P24HMEM_DQS_ADDR_CMD_N24
HMEM_DQ_ADDR_CMD024
HMEM_DQ_ADDR_CMD124HMEM_DQ_ADDR_CMD224HMEM_DQ_ADDR_CMD424HMEM_DQ_ADDR_CMD324
HMEM_DQ_ADDR_CMD524
HMEM_DQ_ADDR_CMD624HMEM_DQ_ADDR_CMD724HMEM_DQ_ADDR_CMD824
HMEM_ADDR_CMD2924
HMEM_ADDR_CMD1824HMEM_ADDR_CMD1724HMEM_ADDR_CMD1624
HMEM_ADDR_CMD1524
HMEM_ADDR_CMD1924HMEM_ADDR_CMD2624
HMEM_ADDR_CMD1224
HMEM_ADDR_CMD1424
HMEM_ADDR_CMD1024HMEM_ADDR_CMD924
HMEM_ADDR_CMD624
HMEM_ADDR_CMD824HMEM_ADDR_CMD724
HMEM_ADDR_CMD1324
HMEM_ADDR_CMD1124
HMEM_ADDR_CMD524
HMEM_ADDR_CMD224
HMEM_ADDR_CMD024
HMEM_ADDR_CMD3024
HMEM_ADDR_CMD124
HMEM_ADDR_CMD3124
HMEM_ADDR_CMD424HMEM_ADDR_CMD324
HMEM_CLK_N24HMEM_CLK_P24
HMEM_ADDR_CMD2524
HMEM_ADDR_CMD2124HMEM_ADDR_CMD2024
HMEM_ADDR_CMD2224
HMEM_ADDR_CMD2424HMEM_ADDR_CMD2324
HMEM_ADDR_CMD2724HMEM_ADDR_CMD2824
CLK_HPSEMI_P 40
CLK_HPSEMI_N 40
HMEM_DQA024HMEM_DQA124
HMEM_DQA224HMEM_DQA324
HMEM_DQA424HMEM_DQA524HMEM_DQA624
HMEM_DQA724
HMEM_DQA824
HMEM_DQA924
HMEM_DQA1024HMEM_DQA1124
HMEM_DQA1224
HMEM_DQA1324
HMEM_DQA1424
HMEM_DQA1524
HMEM_DQA1624
HMEM_DQA1724HMEM_DQA1824HMEM_DQA1924
HMEM_DQA2024HMEM_DQA2124
HMEM_DQA2224
HMEM_DQA2324
HMEM_DQA3024HMEM_DQA3124
HMEM_DQSA_P024HMEM_DQSA_N024
HMEM_DQSA_P124HMEM_DQSA_N124
HMEM_DQSA_P224HMEM_DQSA_N224
HPSMEM_DMA024
HPSMEM_DMA124
HPSMEM_DMA224
HPSMEM_DMA324
HMEM_DQA2424
HMEM_DQA2524HMEM_DQA2624
HMEM_DQA2724
HMEM_DQA2824HMEM_DQA2924
HMEM_DQSA_P324HMEM_DQSA_N324
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B19 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B19 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B19 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R651100
IO BANK 2J, HPS Memory BANK
A10SOC_1517
U23K
IO, LVDS2J_1N, DQ8LAV26
IO, LVDS2J_1P, DQ8LAV27
IO, LVDS2J_2N, DQ8LAU27
IO, LVDS2J_2P, DQ8LAU28
IO, LVDS2J_3N, DQ8LAV28
IO, LVDS2J_3P, DQ8LAW28
IO, LVDS2J_4N, DQSN8LAW25
IO, LVDS2J_4P, DQS8LAW26
IO, LVDS2J_5N, DQ8LAV24
IO, LVDS2J_5P, DQ8LAW24
IO, LVDS2J_6N, DQ8LAV23
IO, LVDS2J_6P, DQ8LAW23
IO, LVDS2J_7N, DQ9LAU25
IO, LVDS2J_7P, DQ9LAU26
IO, LVDS2J_8N, DQ9LAR26
IO, LVDS2J_8P, DQ9LAT26
IO, LVDS2J_9N, DQ9LAT23
IO, LVDS2J_9P, DQ9LAU24
IO, PLL_2J_CLKOUT1N, LVDS2J_10N, DQSN9LAT24
IO, PLL_2J_CLKOUT1P, PLL_2J_CLKOUT1, PLL_2J_FB1, LVDS2J_10P, DQS9LAT25
IO, LVDS2J_11N, DQ9LAP25
IO, RZQ_2J, LVDS2J_11P, DQ9LAR25
IO, CLK_2J_1N, LVDS2J_12N, DQ9LAP23
IO, CLK_2J_1P, LVDS2J_12P, DQ9LAP24
IO, CLK_2J_0N, LVDS2J_13N, DQ10LAN26
IO, CLK_2J_0P, LVDS2J_13P, DQ10LAP26
IO, LVDS2J_14N, DQ10LAN23
IO, LVDS2J_14P, DQ10LAN24
IO, PLL_2J_CLKOUT0N, LVDS2J_15N, DQ10LAK26
IO, PLL_2J_CLKOUT0P, PLL_2J_CLKOUT0, PLL_2J_FB0, LVDS2J_15P, DQ10LAL26
IO, LVDS2J_16N, DQSN10LAL25
IO, LVDS2J_16P, DQS10LAM25
IO, LVDS2J_17N, DQ10LAK23
IO, LVDS2J_17P, DQ10LAL23
IO, LVDS2J_18N, DQ10LAM24
IO, LVDS2J_18P, DQ10LAL24
IO, LVDS2J_19N, DQ11LAH25
IO, LVDS2J_19P, DQ11LAJ26
IO, LVDS2J_20N, DQ11LAH23
IO, LVDS2J_20P, DQ11LAH24
IO, LVDS2J_21N, DQ11LAJ23
IO, LVDS2J_21P, DQ11LAJ24
IO, LVDS2J_22N, DQSN11LAJ25
IO, LVDS2J_22P, DQS11LAK25
IO, LVDS2J_23N, DQ11LAF25
IO, LVDS2J_23P, DQ11LAG25
IO, LVDS2J_24N, DQ11LAF24
IO, LVDS2J_24P, DQ11LAG24
R654 240
IO BANK 2K, HPS Memory BANK
A10SOC_1517
U23J
IO, LVDS2K_1N, DQ4LP25
IO, LVDS2K_1P, DQ4LN25
IO, LVDS2K_2N, DQ4LL26
IO, LVDS2K_2P, DQ4LK26
IO, LVDS2K_3N, DQ4LM25
IO, LVDS2K_3P, DQ4LL25
IO, LVDS2K_4N, DQSN4LL24
IO, LVDS2K_4P, DQS4LK25
IO, LVDS2K_5N, DQ4LN24
IO, LVDS2K_5P, DQ4LM24
IO, LVDS2K_6N, DQ4LJ25
IO, LVDS2K_6P, DQ4LJ26
IO, LVDS2K_7N, DQ5LJ24
IO, LVDS2K_7P, DQ5LH24
IO, LVDS2K_8N, DQ5LE25
IO, LVDS2K_8P, DQ5LD25
IO, LVDS2K_9N, DQ5LF23
IO, LVDS2K_9P, DQ5LF24
IO, PLL_2K_CLKOUT1N, LVDS2K_10N, DQSN5LG25
IO, PLL_2K_CLKOUT1P, PLL_2K_CLKOUT1, PLL_2K_FB1, LVDS2K_10P, DQS5LG26
IO, LVDS2K_11N, DQ5LF26
IO, RZQ_2K, LVDS2K_11P, DQ5LE26
IO, CLK_2K_1N, LVDS2K_12N, DQ5LG24
IO, CLK_2K_1P, LVDS2K_12P, DQ5LF25
IO, CLK_2K_0N, LVDS2K_13N, DQ6LD24
IO, CLK_2K_0P, LVDS2K_13P, DQ6LC24
IO, LVDS2K_14N, DQ6LE23
IO, LVDS2K_14P, DQ6LD23
IO, PLL_2K_CLKOUT0N, LVDS2K_15N, DQ6LC23
IO, PLL_2K_CLKOUT0P, PLL_2K_CLKOUT0, PLL_2K_FB0, LVDS2K_15P, DQ6LB22
IO, LVDS2K_16N, DQSN6LB24
IO, LVDS2K_16P, DQS6LC25
IO, LVDS2K_17N, DQ6LC21
IO, LVDS2K_17P, DQ6LC22
IO, LVDS2K_18N, DQ6LC26
IO, LVDS2K_18P, DQ6LB26
IO, LVDS2K_19N, DQ7LA18
IO, LVDS2K_19P, DQ7LA17
IO, LVDS2K_20N, DQ7LB19
IO, LVDS2K_20P, DQ7LB20
IO, LVDS2K_21N, DQ7LA23
IO, LVDS2K_21P, DQ7LA24
IO, LVDS2K_22N, DQSN7LA25
IO, LVDS2K_22P, DQS7LA26
IO, LVDS2K_23N, DQ7LB21
IO, LVDS2K_23P, DQ7LA22
IO, LVDS2K_24N, DQ7LA19
IO, LVDS2K_24P, DQ7LA20
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
HPS Shared IOs
HOSTPROCESSOR_I2C
SH_SDASH_SCL
USB_DATA025USB_DATA125
USB_DATA225USB_DATA325USB_DATA425USB_DATA525USB_DATA625USB_DATA725
USB_CLK25USB_STP25USB_DIR25
USB_NXT25
ENET_HPS_GTX_CLK22ENET_HPS_TX_EN22ENET_HPS_RX_CLK22ENET_HPS_RX_DV22ENET_HPS_TXD022ENET_HPS_TXD122ENET_HPS_RXD022ENET_HPS_RXD122ENET_HPS_TXD222ENET_HPS_TXD322ENET_HPS_RXD222ENET_HPS_RXD322
HPSUARTA_TX35HPSUARTA_RX35
SPIM1_CLK35SPIM1_MOSI35
SPIM1_SS0_N35SPIM1_MISO35
SPIM1_SS1_N35
ENET_HPS_MDIO22ENET_HPS_MDC22
TRACE_D323TRACE_D223TRACE_D123TRACE_D023
TRACE_ClK23
A10SH_GPIO035
A10SH_GPIO135
A10SH_GPIO235A10SH_GPIO335
A10I2CEN 35
A10_2L_SDA 35,45A10_2L_SCL 35,45
IO_3V3 69
IO_1V8 36,37,68
USER_DIPSW_HPS342
USER_LED_HPS342
USER_PB_HPS342
USER_DIPSW_HPS242
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B20 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B20 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B20 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
U55
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
R501
4.7K
C436
0.1uF
R500
4.7K
R40771.00k
IO BANK 2L, 3V0,2V5,1V8 BANK
A10SOC_1517
U23I
IO, DQ0L, GPIO0_IO0,NAND_ADQ0,UART0_CTS_N,USB0_CLK,SDMMC_DATA0,SPIM0_SS1_N,SPIS0_CLKD18
IO, DQ0L, GPIO0_IO1,NAND_ADQ1,UART0_RTS_N,USB0_STP,SDMMC_CMD,SPIM1_SS1_N,SPIS0_MOSIE18
IO, DQ0L, GPIO0_IO2,NAND_WE_N,UART0_TX,USB0_DIR,SDMMC_CCLK,SPIS0_SS0_N,I2C1_SDAC19
IO, DQ0L, GPIO0_IO3,NAND_RE_N,UART0_RX,USB0_DATA0,SDMMC_DATA1,SPIS0_MISO,I2C1_SCLD19
IO, DQ0L, GPIO0_IO4,NAND_WP_N,UART1_CTS_N,QSPI_SS2,USB0_DATA1,SDMMC_DATA2,SPIM0_CLK,I2C0_SDAE17
IO, DQ0L, GPIO0_IO5,NAND_ADQ2,UART1_RTS_N,QSPI_SS3,USB0_NXT,SDMMC_DATA3,SPIM0_MOSI,I2C0_SCLF17
IO, DQSN0L, GPIO0_IO6,NAND_ADQ3,UART1_TX,USB0_DATA2,SDMMC_DATA4,SPIM0_MISO,EMAC2_MDIO,I2C_EMAC2_SDAC17
IO, DQS0L, GPIO0_IO7,NAND_CLE,UART1_RX,USB0_DATA3,SDMMC_DATA5,SPIM0_SS0_N,EMAC2_MDC,I2C_EMAC2_SCLC18
IO, DQ0L, GPIO0_IO8,NAND_ADQ4,USB0_DATA4,SDMMC_DATA6,SPIM1_CLK,SPIS1_CLK,EMAC1_MDIO,I2C_EMAC1_SDAD21
IO, DQ0L, GPIO0_IO9,NAND_ADQ5,USB0_DATA5,SDMMC_DATA7,SPIM1_MOSI,SPIS1_MOSI,EMAC1_MDC,I2C_EMAC1_SCLD20
IO, DQ0L, GPIO0_IO10,NAND_ADQ6,USB0_DATA6,SPIM1_MISO,SPIS1_SS0_N,EMAC0_MDIO,I2C_EMAC0_SDAE21
IO, DQ0L, GPIO0_IO11,NAND_ADQ7,USB0_DATA7,SPIM1_SS0_N,SPIS1_MISO,EMAC0_MDC,I2C_EMAC0_SCLE22
IO, DQ1L, GPIO0_IO12,NAND_ALE,USB1_CLK,EMAC0_TX_CLKH18
IO, DQ1L, GPIO0_IO13,NAND_RB,USB1_STP,EMAC0_TX_CTLH19
IO, DQ1L, GPIO0_IO14,NAND_CE_N,USB1_DIR,EMAC0_RX_CLKF18
IO, DQ1L, GPIO0_IO15,USB1_DATA0,EMAC0_RX_CTLG17
IO, DQ1L, GPIO0_IO16,NAND_ADQ8,USB1_DATA1,EMAC0_TXD0E20
IO, DQ1L, GPIO0_IO17,NAND_ADQ9,USB1_NXT,EMAC0_TXD1F20
IO, PLL_2L_CLKOUT1N, DQSN1L, GPIO0_IO18,NAND_ADQ10,USB1_DATA2,EMAC0_RXD0G20
IO, PLL_2L_CLKOUT1P, PLL_2L_CLKOUT1, PLL_2L_FB1, DQS1L, GPIO0_IO19,NAND_ADQ11,USB1_DATA3,EMAC0_RXD1,SPIM1_SS1_NG21
IO, DQ1L, GPIO0_IO20,NAND_ADQ12,UART0_CTS_N,USB1_DATA4,EMAC0_TXD2,SPIM1_CLK,SPIS0_CLK,I2C1_SDAF19
IO, RZQ_2L, DQ1L, GPIO0_IO21,NAND_ADQ13,UART0_RTS_N,USB1_DATA5,EMAC0_TXD3,SPIM1_MOSI,SPIS0_MOSI,I2C1_SCLG19
IO, CLK_2L_1N, DQ1L, GPIO0_IO22,NAND_ADQ14,UART0_TX,USB1_DATA6,EMAC0_RXD2,SPIM1_MISO,SPIS0_SS0_N,I2C0_SDAF22
IO, CLK_2L_1P, DQ1L, GPIO0_IO23,NAND_ADQ15,UART0_RX,USB1_DATA7,EMAC0_RXD3,SPIM1_SS0_N,SPIS0_MISO,I2C0_SCLG22
IO, CLK_2L_0N, DQ2L, GPIO1_IO0,NAND_ADQ0,UART0_CTS_N,EMAC1_TX_CLK,SPIM1_CLKK18
IO, CLK_2L_0P, DQ2L, GPIO1_IO1,NAND_ADQ1,UART0_RTS_N,EMAC1_TX_CTL,SPIM1_MOSIL19
IO, DQ2L, GPIO1_IO2,NAND_WE_N,UART0_TX,EMAC1_RX_CLK,SPIM1_MISO,I2C0_SDAH22
IO, DQ2L, GPIO1_IO3,NAND_RE_N,UART0_RX,EMAC1_RX_CTL,SPIM1_SS0_N,I2C0_SCLH21
IO, PLL_2L_CLKOUT0N, DQ2L, GPIO1_IO4,NAND_WP_N,UART1_CTS_N,EMAC1_TXD0,SPIM1_SS1_N,SPIS1_CLKJ21
IO, PLL_2L_CLKOUT0P, PLL_2L_CLKOUT0, PLL_2L_FB0, DQ2L, GPIO1_IO5,NAND_ADQ2,UART1_RTS_N,EMAC1_TXD1,SPIS1_MOSIJ20
IO, DQSN2L, GPIO1_IO6,NAND_ADQ3,UART1_TX,EMAC1_RXD0,SPIS1_SS0_N,I2C1_SDAJ18
IO, DQS2L, GPIO1_IO7,NAND_CLE,UART1_RX,EMAC1_RXD1,SPIS1_MISO,I2C1_SCLJ19
IO, DQ2L, GPIO1_IO8,NAND_ADQ4,EMAC1_TXD2,SPIS0_CLK,EMAC2_MDIO,I2C_EMAC2_SDAH23
IO, DQ2L, GPIO1_IO9,NAND_ADQ5,EMAC1_TXD3,SPIS0_MOSI,EMAC2_MDC,I2C_EMAC2_SCLJ23
IO, DQ2L, GPIO1_IO10,NAND_ADQ6,EMAC1_RXD2,SPIS0_SS0_N,EMAC0_MDIO,I2C_EMAC0_SDAK21
IO, DQ2L, GPIO1_IO11,NAND_ADQ7,EMAC1_RXD3,SPIS0_MISO,EMAC0_MDC,I2C_EMAC0_SCLK20
IO, DQ3L, GPIO1_IO12,NAND_ALE,EMAC2_TX_CLK,SDMMC_DATA0,I2C1_SDAL20
IO, DQ3L, GPIO1_IO13,NAND_RB,EMAC2_TX_CTL,SDMMC_CMD,I2C1_SCLM20
IO, DQ3L, GPIO1_IO14,NAND_CE_N,UART1_TX,EMAC2_RX_CLK,SDMMC_CCLKN20
IO, DQ3L, GPIO1_IO15,UART1_RX,TRACE_CLK,EMAC2_RX_CTL,SDMMC_DATA1P20
IO, DQ3L, GPIO1_IO16,NAND_ADQ8,UART1_CTS_N,QSPI_SS2,EMAC2_TXD0,SDMMC_DATA2K23
IO, DQ3L, GPIO1_IO17,NAND_ADQ9,UART1_RTS_N,QSPI_SS3,EMAC2_TXD1,SDMMC_DATA3,SPIM0_SS1_NL23
IO, DQSN3L, GPIO1_IO18,NAND_ADQ10,EMAC2_RXD0,SDMMC_DATA4,SPIM0_MISO,EMAC1_MDIO,I2C_EMAC1_SDAN23
IO, DQS3L, GPIO1_IO19,NAND_ADQ11,TRACE_CLK,EMAC2_RXD1,SDMMC_DATA5,SPIM0_SS0_N,EMAC1_MDC,I2C_EMAC1_SCLN22
IO, DQ3L, GPIO1_IO20,NAND_ADQ12,TRACE_D0,EMAC2_TXD2,SDMMC_DATA6,SPIM0_CLK,SPIS1_CLK,I2C_EMAC2_SDAK22
IO, DQ3L, GPIO1_IO21,NAND_ADQ13,TRACE_D1,EMAC2_TXD3,SDMMC_DATA7,SPIM0_MOSI,SPIS1_MOSI,I2C_EMAC2_SCLL22
IO, DQ3L, GPIO1_IO22,NAND_ADQ14,TRACE_D2,EMAC2_RXD2,SPIM0_MISO,SPIS1_SS0_N,EMAC0_MDIO,I2C_EMAC0_SDAM22
IO, DQ3L, GPIO1_IO23,NAND_ADQ15,TRACE_D3,EMAC2_RXD3,SPIM0_SS0_N,SPIS1_MISO,EMAC0_MDC,I2C_EMAC0_SCLM21
R6610
C437
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Bootsel bits are configured in Bootflash daughter card
64MB, 1.8V Serial Flash MemoryPut the device close to Max V
HPS Dedicated IOs
AS QSPI FLASH
HPS_BOOT_FLASH_PORT
AS_D0AS_D1AS_D2AS_D3
FDCLKR
AS_CSN
NIO_PULLUPNCSO1NCSO2
qspIclkr
SDMMC_CCLK
IO_1V8 36,37,68
A10_JTAG_TMS38A10_JTAG_TDO38
A10_JTAG_TCK38A10_JTAG_TDI38
A10_JTAG_TRST38
MSEL035MSEL135MSEL235
HPS_DIO023
HPS_DIO123
HPS_DIO223
HPS_DIO323HPS_DIO423HPS_DIO523HPS_DIO623HPS_DIO723HPS_DIO823HPS_DIO923HPS_DIO1023HPS_DIO1123HPS_DIO1223HPS_DIO1323
HPS_CLK139HPS_NPOR35HPS_NRST35
NCONFIG35DCLK35
NSTATUS35CONF_DONE35
TEMPDIODE_P45TEMPDIODE_N45
RESERVE135
IO_1V8
IO_1V8
IO_1V8
IO_1V8
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B21 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B21 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B21 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R514 10K
R55271.00K
R517 10K
R448 10K
R534 10
R679 0
R676 22.0
C391
0.1uF
R515 0
OPEN
SW4
TDA04H0SB1
12345
678
U19
EPCQ1024L
S#C2 DQ1
D2
W#/VPP/DQ2C4
VSSB3
DQ0D3
CB2
HOLD#/DQ3D4
VCCB4
NC1A2
NC2A3
NC3A4
NC4A5
NC5B1
NC6B5
NC7C1
NC8C3
NC9C5
NC10D1
NC11D5
NC12E1
NC13E2
NC14E3
NC15E4
NC16E5
R55231.00K
C390
0.1uF
R55241.00K
FPGA CONF, HPS Dedicated IO, 1V8 Bankd
A10SOC_1517
U23W
TDOAW14
TMSAV13
TRSTAR13
TCKAW15
TDIAL15
MSEL0AU15
MSEL1AP15
MSEL2AT15
NIO_PULLUPAT14
NSTATUSAU12
CONF_DONEAT13
NCONFIGAM14
NCEAM15
NCSO0AU14
NCSO1AV12
NCSO2AV14
AS_DATA0, ASDOAP13
AS_DATA1AW11
AS_DATA2AV11
AS_DATA3AW13
DCLKAN14
VSIGP_0A15
VSIGN_0B15
VSIGP_1A14
VSIGN_1B14
TEMPDIODEPC16
TEMPDIODENB16
HPS_CLK1G15
HPS_NPORJ15
HPS_NRSTK15
GPIO2_IO0,NAND_ADQ0,SDMMC_DATA0,QSPI_CLKE16
GPIO2_IO1,NAND_ADQ1,SDMMC_CMD,QSPI_IO0H16
GPIO2_IO2,NAND_WE_N,SDMMC_CCLK,QSPI_SS0,BOOTSEL2K16
GPIO2_IO3,NAND_RE_N,SDMMC_DATA1,QSPI_IO1G16
GPIO2_IO4,NAND_ADQ2,SDMMC_DATA2,QSPI_IO2_WPNH17
GPIO2_IO5,NAND_ADQ3,SDMMC_DATA3,QSPI_IO3_HOLDF15
GPIO2_IO6,NAND_CLE,SDMMC_PWR_ENA,SPIM0_SS1_N,SPIS0_MISO,BOOTSEL1L17
GPIO2_IO7,NAND_ALE,QSPI_SS1,CM_PLL_CLK0,SPIM0_CLK,BOOTSEL0N19
GPIO2_IO8,NAND_RB,UART1_TX,SDMMC_DATA4,CM_PLL_CLK1,SPIM0_MOSI,EMAC1_MDIO,I2C_EMAC1_SDAM19
GPIO2_IO9,NAND_CE_N,UART1_RTS_N,SDMMC_DATA5,CM_PLL_CLK2,SPIM0_MISO,EMAC1_MDC,I2C_EMAC1_SCLE15
GPIO2_IO10,NAND_ADQ4,UART1_CTS_N,SDMMC_DATA6,CM_PLL_CLK3,SPIM0_SS0_N,EMAC2_MDIO,I2C_EMAC2_SDAJ16
GPIO2_IO11,NAND_ADQ5,UART1_RX,SDMMC_DATA7,CM_PLL_CLK4,SPIS0_CLK,EMAC2_MDC,I2C_EMAC2_SCLL18
GPIO2_IO12,NAND_ADQ6,UART1_TX,QSPI_SS2,SPIS0_MOSI,EMAC0_MDIO,I2C_EMAC0_SDAM17
GPIO2_IO13,NAND_ADQ7,UART1_RX,QSPI_SS3,SPIS0_SS0_N,EMAC0_MDC,I2C_EMAC0_SCLK17
R55251.00KR516 10K
R55261.00K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet - HPS
Place near KSZ9021RN PHY
ETHERNET INTERFACE
BOOT-STRAPS
1.2V AVDLL_PLL
PHYAD2
PHYAD1
PHYAD0
NAME Pin
35
15
17
Value
1
1
1
MODE3
MODE2
MODE1
MODE0
27
28
31
32
Description
ID = b"111"
1
1
1
1
RGMII (10/100/1000)
ClK125_EN 33 0 No clockoutput
LED_MODE 41 1singal led mode
MDI_HPS_P1MDI_HPS_N1MDI_HPS_P2MDI_HPS_N2
CT3
MDI_HPS_P3
CT1
CT0
CT2
MDI_HPS_N3
MDI_HPS_N0MDI_HPS_P0
ENET_RSET
ENET_HPS_LED2_LINKENET_HPS_LED1_LINK
ENET_HPS_RXD2ENET_HPS_RXD3
ENET_HPS_RXD1ENET_HPS_RXD0ENET_HPS_RX_DV
CLK125_NDO_LED_MODE
CT0
CT1
CT2
CT3
ENET_HPS_RX_CLK
ENET_HPS_TX_EN 20
ENET_HPS_GTX_CLK 20
ENET_HPS_RX_CLK 20
ENET_HPS_RX_DV 20
ENET_HPS_TXD3 20ENET_HPS_TXD2 20ENET_HPS_TXD1 20ENET_HPS_TXD0 20
ENET_HPS_RXD0 20ENET_HPS_RXD1 20ENET_HPS_RXD2 20ENET_HPS_RXD3 20
ENET_HPS_MDC20ENET_HPS_MDIO20
ENET_HPS_RESETn35
ENET_HPS_INTn35
IO_1V8 36,37,68IO_2V5 36,68IO_5V 50
IO_3V3 69
1.2V_AVDLL_PLL
3.3V_AVDDH
1.8V_DVDDH
1.2V_AVDDL
1.2V_AVDLL_PLL1.2V_AVDDL
1.2V_DVDDL
1.2V_DVDDL
1.8V_DVDDH
3.3V_AVDDH
1.2V_AVDLL_PLL
IO_1V8
IO_3V3
IO_2V5
IO_2V5
IO_3V3
IO_5V
IO_5V
IO_3V3
IO_1V8
IO_3V3
IO_1V8
IO_3V3
IO_1V8
IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B22 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B22 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B22 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R351 DNI
R73 DNI
R341 2.00K
R57 DNI
C24522uF
C261
0.1uF
R76 4.7K
R69 DNI
R80 4.7K
R1241.00K
C1622uF
R67 4.7K
C230
0.1uF
R77 DNI
C22
2.2uF
R81 4.7K
R8
220
C2322uF
R63 4.7K
R61 DNI
C2802.2uF
R342 10KC24
22uF
U72
25.00MHz
VCC4
GND2
OUT3
EN1
C2432.2uF
L2
3A, 30 Ohm FB
L15
3A, 30 Ohm FB
R68 1.00K
R79 DNI
R549710K
R7 220
C2822uF
C281
0.1uF
C242
0.01uF
C2622.2uF
U12B
KSZ9031RN
DVDDL39
DVDDH40
LDO_O43AVDDL_PLL44
NC147
P_GND49
VSS29 NC13
AVDDL9
AVDDL4AVDDH
1 AVDDH12
DVDDL30
DVDDL26
DVDDL23
DVDDL14DVDDH
16DVDDL
18
DVDDH34
L16
3A, 30 Ohm FB
C13 0.01uF
R78 4.7K
C229
0.1uF
C2282.2uF
R70 4.7KR71 DNI
Yellow
Green
Orange
J5
ENET_L829-1J1T-43
TD0_P11
TD0_N10
TD1_P4
TD1_N5
TD2_P3
TD2_N2
TD3_P8
TD3_N9
CT012
GND_TAB19 GND_TAB18
OK15
GOA16
YA14
YK13
GK17
CT16
CT21
CT37
C15 0.01uF
R367 4.7K
C26 1uF
C21022uFC203
10uF
R62 1.00K
C244
0.1uF
R378 4.7K
C14 0.01uF
C37
10uF
R75 DNI
MDI INTERFACE
U12A
KSZ9031RN
TXRXP_A2
LED1_PHYAD0/PME_N117
TXRXP_D10
TXRXP_C7
TXRXM_C8
TXRXP_B5
TXRXM_B6
TXRXM_A3
TXRXM_D11
LED2_PHYAD115
TXD120
TXD019
GTX_CLK24
RXD0_MODE032
RX_DV_CLK125_EN33
TXD322
RXD2_MODE228
TX_EN25
RXD3_MODE327
RXD1_MODE131
TXD221
RX_CLK_PHYAD235
MDC36
MDIO37
INT_N/PME_N238
XO45 XI46
ISET48
RESET_N42
CLK125_NDO_LED_MODE41
U10
LT3026-1
IN11
IN22
GN
D3
GNDS4
BST5
SHDN6
PG7ADJ8
OUT19OUT210
GN
D11
R74 4.7K
L1
3A, 30 Ohm FB
C12 0.01uF
R72 4.7K
R340 12.1K
C21
10uF
C252.2uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
MAXV PS Flash
Mictor Early Trace
Boost Flash SlotFile Flash Slot
Connectors of Boot flash, file flash,early trace and fast trace
Mictor Fast Trace
MICTOR_PWR1
MIC_34
FMICTOR_PWR1
FMIC_30FMIC_32FMIC_34
1V8 35,54
IO_3V3 69
MFD0 35MFD1 35MFD2 35MFD3 35
MFCLK35MFCSN35
IO_1V8 36,37,68
HPS_DIO0 21HPS_DIO121
HPS_DIO221HPS_DIO3 21
HPS_DIO421HPS_DIO5 21
HPS_DIO6 21
HPS_DIO7 21
HPS_DIO821HPS_DIO921
HPS_DIO1021HPS_DIO11 21HPS_DIO1221HPS_DIO13 21
BQSPI_RESETN 35BF_Presentn35
TRACE_D3 20TRACE_D2 20TRACE_D1 20
TRACE_D0 20
TRACE_ClK 20
FILE_RESETN 35File_Presentn35
FILE_DIO0 27FILE_DIO127
FILE_DIO227FILE_DIO3 27
FILE_DIO427FILE_DIO5 27
FILE_DIO6 27
FILE_DIO7 27
FILE_DIO827FILE_DIO927
FILE_DIO1027FILE_DIO11 27FILE_DIO1227FILE_DIO13 27
FTRACE_D0 27,38
FTRACE_D1 27,38FTRACE_D2 27,38FTRACE_D3 27,38FTRACE_D4 27,38FTRACE_D5 27,38FTRACE_D6 27,38FTRACE_D7 27,38
MICTOR_PROC_RESETn38
MICTOR_JTAG_TDI38
MICTOR_JTAG_TCK38MICTOR_JTAG_TMS38
MICTOR_JTAG_TDO38
MICTOR_JTAG_TRSTn38
FTRACE_JTAG_TCK38
FTRACE_JTAG_TRSTn38
FTRACE_JTAG_TMS38FTRACE_JTAG_TDI38
FTRACE_PROC_RESETN38
FTRACE_CLK 27,38
FTRACE_D827,38FTRACE_D927,38
FTRACE_D1027,38FTRACE_D1127,38FTRACE_D1227,38FTRACE_D1327,38FTRACE_D1427,38FTRACE_D1527,38
FTRACE_JTAG_TDO38
dedicated_RX35
dedicated_TX 35
dedicated_OE35
IO_3V3
1V8
1V8
1V8
IO_1V8
IO_1V8
IO_1V8
IO_3V3IO_3V3
IO_3V3
IO_3V3
IO_1V8
IO_1V8
IO_1V8
IO_1V8IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B23 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B23 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B23 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R4150_Ohms
U15
EPCQ1024L
S#C2 DQ1
D2
W#/VPP/DQ2C4
VSSB3
DQ0D3
CB2
HOLD#/DQ3D4
VCCB4
NC1A2
NC2A3
NC3A4
NC4A5
NC5B1
NC6B5
NC7C1
NC8C3
NC9C5
NC10D1
NC11D5
NC12E1
NC13E2
NC14E3
NC15E4
NC16E5
R782 10K
R413 10K
J43
Mictor38P
NC11
NC32
NC23
NC44
GND5
TRACECLK6
TRIGIN7
TRIGOUT8
nSRST9
NC10
TDO/SWO11
VTREF12
RTCK13
Vsupply14
TCK15
TD716
TMS17
TD618
TDI19
TD520
nTRST21
TD422
TD1523
TD324
TD1425
TD226
TD1327
TD128
TD1229
Logic0A30
TD1131
Logic0B32
TD1033
LOGIC134
TD935
TRACECTL36
TD837
TD038
GND139
GND240
GND341
GND442
GND543
R384 10K
MH1
MHOLE4-40
R419 10K
R439 10K
C246
0.1uF
J23
QTH-030-02-L-D-A
2468
1012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
61 62 63 64
R784 DNI
C364
0.1uF
R768 10K
C413
0.1uF
MH2
MHOLE4-40
C374
0.1uF
STDoff1
8mmStandoff
R809 10K
R414 DNI
R769 10K
R435 10K
R416 DNI
R7700_Ohms
R783 10K
C296
0.1uF
J20
Mictor38P
NC11
NC32
NC23
NC44
GND5
TRACECLK6
TRIGIN7
TRIGOUT8
nSRST9
NC10
TDO/SWO11
VTREF12
RTCK13
Vsupply14
TCK15
TD716
TMS17
TD618
TDI19
TD520
nTRST21
TD422
TD1523
TD324
TD1425
TD226
TD1327
TD128
TD1229
Logic0A30
TD1131
Logic0B32
TD1033
LOGIC134
TD935
TRACECTL36
TD837
TD038
GND139
GND240
GND341
GND442
GND543
R772 10K
U77
SN74LVC1G126
2 A 4Y
1 OE
GND3
VCC5
C350
0.1uF
R418 10K
R771 DNI
C295
0.1uF
R417 10K
STDoff2
8mmStandoff
J11
QTH-030-02-L-D-A
2468
1012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
61 62 63 64
C204
0.1uF
R420 10K
U78
SN74LVC1G126
2 A 4Y
1 OE
GND3
VCC5
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
External Memory Interface - HPS 40-bit 1GB HiLo connector
VDDQ_1.1V_SET and VDDQ_1.8V_SET NOT USEDOnly support DDR3 and DDR4
Place nearHILO connectorJ14 VDD pins
Place nearHILO connectorJ14 VDDQ pins
HMEM_DQSB_N0
HMEM_DQSB_N1
HMEM_DQSB_N2
HMEM_DQSB_N3
HMEM_DQSB_P0
HMEM_DQSB_P1
HMEM_DQSB_P2
HMEM_DQSB_P3
IO_2V5 36,68
IO_3V3 69
HILOHPS_VDD62
HMEM_CLK_P 19HMEM_CLK_N 19
HMEM_DQS_ADDR_CMD_P 19HMEM_DQS_ADDR_CMD_N 19
HMEM_DQ_ADDR_CMD0 19HMEM_DQ_ADDR_CMD1 19HMEM_DQ_ADDR_CMD2 19HMEM_DQ_ADDR_CMD3 19HMEM_DQ_ADDR_CMD4 19HMEM_DQ_ADDR_CMD5 19HMEM_DQ_ADDR_CMD6 19HMEM_DQ_ADDR_CMD7 19HMEM_DQ_ADDR_CMD8 19
HPSMEM_DMA019HPSMEM_DMA119HPSMEM_DMA219HPSMEM_DMA319
HMEM_ADDR_CMD019HMEM_ADDR_CMD119HMEM_ADDR_CMD219HMEM_ADDR_CMD319HMEM_ADDR_CMD419HMEM_ADDR_CMD519HMEM_ADDR_CMD619HMEM_ADDR_CMD719HMEM_ADDR_CMD819HMEM_ADDR_CMD919HMEM_ADDR_CMD1019HMEM_ADDR_CMD1119HMEM_ADDR_CMD1219HMEM_ADDR_CMD1319HMEM_ADDR_CMD1419HMEM_ADDR_CMD1519HMEM_ADDR_CMD1619HMEM_ADDR_CMD1719HMEM_ADDR_CMD1819HMEM_ADDR_CMD1919HMEM_ADDR_CMD2019HMEM_ADDR_CMD2119HMEM_ADDR_CMD2219HMEM_ADDR_CMD2319HMEM_ADDR_CMD2419HMEM_ADDR_CMD2519HMEM_ADDR_CMD2619HMEM_ADDR_CMD2719HMEM_ADDR_CMD2819HMEM_ADDR_CMD2919HMEM_ADDR_CMD3019HMEM_ADDR_CMD3119
HILOHPS_1V2_SETn62
HILOHPS_1V35_SETn62HILOHPS_1V5_SETn62
HMEM_DQA019HMEM_DQA119HMEM_DQA219HMEM_DQA319HMEM_DQA419HMEM_DQA519HMEM_DQA619HMEM_DQA719HMEM_DQA819HMEM_DQA919
HMEM_DQA1019HMEM_DQA1119HMEM_DQA1219HMEM_DQA1319HMEM_DQA1419HMEM_DQA1519HMEM_DQA1619HMEM_DQA1719HMEM_DQA1819HMEM_DQA1919HMEM_DQA2019HMEM_DQA2119HMEM_DQA2219HMEM_DQA2319HMEM_DQA2419HMEM_DQA2519HMEM_DQA2619HMEM_DQA2719HMEM_DQA2819HMEM_DQA2919HMEM_DQA3019HMEM_DQA3119
HMEM_DQSA_P019HMEM_DQSA_N019HMEM_DQSA_P119HMEM_DQSA_N119HMEM_DQSA_P219HMEM_DQSA_N219HMEM_DQSA_P319HMEM_DQSA_N319
HILOHPS_VDD IO_2V5
IO_3V3HILOHPS_VDD
HILOHPS_VDD
HILOHPS_VDD
HILOHPS_VDD
HILOHPS_VDD
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B24 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B24 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B24 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R5492 240
R53361.00k
R5493 240
R53381.00k
R53371.00k
R5332 1.00k
C596
1uF
R5333 1.00k
R53391.00k
R53351.00k
C595
0.1uFR5334
1.00k
C562
1uF
HiLo EMI - POWER
VDD = 1.1(DEFAULT)
VDDQ = 1.1(DEFAULT))
VEXT = 2.5V
J26B
HLS-180324-B-12
VDDC7
VDDC9
VDDC11
VDDC13
VDDD6
VDDD8
VDDD10
VDDD12
VDDD14
VDDE7
VDDE9
VDDE11
VDDE13
VDDF6
VDDF8
VDDF10
VDDQF12
VDDQF14
VDDQG7
VDDQG9
VDDQG11
VDDQG13
VDDQH6
VDDQH8
VDDQH10
VDDQH12
VEXTL11
VEXTL13
VEXTM8
VEXTM10
VEXTM12
VEXTM14
VEXTN7
VEXTN9
VEXTN11
VEXTN13
VEXTP8
VEXTP10
VEXTP12
VEXTP14
2.5V/3.3V (VTT)J7
2.5V/3.3V (VTT)J9
2.5V/3.3V (VTT)K6
2.5V/3.3V (VTT)K8
2.5V/3.3V (VTT)L7
2.5V/3.3V (VTT)L9
VREFH14
2.5V/3.3V (VTT)J11
VREFJ13
2.5V/3.3V (VTT)K10
2.5V/3.3V (VTT)K12
VREFK14
VDD_1.2V_SETG15
VDD_1.25V_SETD5
VDD_1.35V_SETJ15
VDD_1.5V_SETL15
VDD_1.8V_SETN16
VDDQ_1.8V_SETR11
VDDQ_1.35V_SETR14
VDDQ_1.25V_SETF5 VDDQ_1.2V_SET
P16
VDDQ_1.5V_SETR12
VDDQ_1.1V_SETN15
VDD_1.30V_SETE15
VDDQ_1.30V_SETR15
C1558
0.1uF
C512
10uF
C511
10uF
HiLo EMI - GNDJ26C
HLS-180324-B-12
GNDA1
GNDA5
GNDA9
GNDA13
GNDA17
GNDB3
GNDB7
GNDB11
GNDB15
GNDC1
GNDC5
GNDC6
GNDC8
GNDC10
GNDC12
GNDC14
GNDC17
GNDD3
GNDD7
GNDD9
GNDD11
GNDD13
GNDD15
GNDE1
GNDE5
GNDE6
GNDE8
GNDE10
GNDE12
GNDE14
GNDE17
GNDF3
GNDF7
GNDF9
GNDF11
GNDF13
GNDF15
GNDG1
GNDG5
GNDG6
GNDG8
GNDG10
GNDG12
GNDG14
GNDG17
GNDH3
GNDH7
GNDH9
GNDH11
GNDH13
GNDH15
GNDJ1
GNDJ5
GNDJ6
GNDJ8
GNDJ10
GNDJ12
GNDJ14
GNDJ17
GNDK3
GNDK7
GNDK9
GNDK11
GNDK13
GNDK15
GNDL1
GNDL5
GNDL8
GNDL10
GNDL12
GNDL14
GNDL17
GNDM3
GNDM7
GNDM9
GNDM11
GNDM13
GNDM15
GNDN1
GNDN5
GNDN8
GNDN10
GNDN12
GNDN14
GNDN17
GNDP3
GNDP6
GNDP7
GNDP9
GNDP11
GNDP13
GNDP15
GNDR1
GNDR5
GNDR9
GNDR10
GNDR13
GNDR17
GNDT3
GNDT7
GNDT11
GNDT15
GNDU1
GNDU5
GNDU9
GNDU13
GNDU17
GNDV3
GNDV7
GNDV11
GNDV15
HiLo EMI - EMI SIGNALSJ26A
HLS-180324-B-12
MEM_CLK_PV1
MEM_CLK_NV2
MEM_ADDR_CMD0F1
MEM_ADDR_CMD1H1
MEM_ADDR_CMD2F2
MEM_ADDR_CMD3G2
MEM_ADDR_CMD4H2
MEM_ADDR_CMD5J2
MEM_ADDR_CMD6K2
MEM_ADDR_CMD7G3
MEM_ADDR_CMD8J3
MEM_ADDR_CMD9L3
MEM_ADDR_CMD10E4
MEM_ADDR_CMD11F4
MEM_ADDR_CMD12G4
MEM_ADDR_CMD13H4
MEM_ADDR_CMD14J4
MEM_ADDR_CMD15K4
MEM_ADDR_CMD16M1
MEM_ADDR_CMD17M2
MEM_ADDR_CMD18N2
MEM_ADDR_CMD19L4
MEM_ADDR_CMD20P5
MEM_ADDR_CMD21M5
MEM_ADDR_CMD22P1
MEM_ADDR_CMD23R4
MEM_ADDR_CMD24M4
MEM_ADDR_CMD25R3
MEM_ADDR_CMD26L2
MEM_ADDR_CMD27K1
MEM_ADDR_CMD28P2
MEM_ADDR_CMD29N4
MEM_ADDR_CMD30P4
MEM_DQS_ADDR_CMD_PV4
MEM_DQS_ADDR_CMD_NV5
MEM_DQ_ADDR_CMD0R6
MEM_DQ_ADDR_CMD1T1
MEM_DQ_ADDR_CMD2R2
MEM_DQ_ADDR_CMD3T2
MEM_DQ_ADDR_CMD4U2
MEM_DQ_ADDR_CMD5U3
MEM_DQ_ADDR_CMD6T4
MEM_DQ_ADDR_CMD7U4
MEM_DQ_ADDR_CMD8T5
MEM_DMA0B10
MEM_DMA1C4
MEM_DMA2B17
MEM_DMA3F17
MEM_DQA0A4
MEM_DQA1B4
MEM_DQA2B5
MEM_DQA3B6
MEM_DQA4A8
MEM_DQA5B8
MEM_DQA6B9
MEM_DQA7A10
MEM_DQA8B1
MEM_DQA9B2
MEM_DQA10C2
MEM_DQA11C3
MEM_DQA12E3
MEM_DQA13D4
MEM_DQA14D1
MEM_DQA15D2
MEM_DQA16A12
MEM_DQA17B12
MEM_DQA18B13
MEM_DQA19B14
MEM_DQA20C15
MEM_DQA21A16
MEM_DQA22B16
MEM_DQA23A18
MEM_DQA24C16
MEM_DQA25D16
MEM_DQA26E16
MEM_DQA27F16
MEM_DQA28D17
MEM_DQA29C18
MEM_DQA30D18
MEM_DQA31E18
MEM_DQA32E2
MEM_DQA33G16
MEM_DQSA_P0A6
MEM_DQSA_P1A2
MEM_DQSA_P2A14
MEM_DQSA_P3F18
MEM_DQSA_N0A7
MEM_DQSA_N1A3
MEM_DQSA_N2A15
MEM_DQSA_N3G18
MEM_QKA_N0A11
MEM_DQSB_N0J18
MEM_DQSB_N1V18
MEM_DQSB_N2V17
MEM_DQSB_N3V9
MEM_DQSB_P0H18
MEM_DQSB_P1U18
MEM_DQSB_P2V16
MEM_DQSB_P3V8
MEM_QKB_N0M18
MEM_DMB0M16
MEM_DMB1U16
MEM_DMB2U11
MEM_DMB3U6
MEM_DQB0H16
MEM_DQB1J16
MEM_DQB2K16
MEM_DQB3L16
MEM_DQB4H17
MEM_DQB5K17
MEM_DQB6K18
MEM_DQB7L18
MEM_DQB8M17
MEM_DQB9N18
MEM_DQB10P17
MEM_DQB11P18
MEM_DQB12R18
MEM_DQB13T16
MEM_DQB14T17
MEM_DQB15T18
MEM_DQB16U15
MEM_DQB17T14
MEM_DQB18U14
MEM_DQB19V14
MEM_DQB20T13
MEM_DQB21T12
MEM_DQB22U12
MEM_DQB23V12
MEM_DQB24T10
MEM_DQB25U10
MEM_DQB26V10
MEM_DQB27T9
MEM_DQB28T8
MEM_DQB29U8
MEM_DQB30U7
MEM_DQB31V6
MEM_DQB32R16
MEM_DQB33T6
CONFIG0L6
CONFIG1M6
RFU2H5
RFU3K5
RFU4N6
RFU5R7
MEM_ADDR_CMD31N3
MEM_QKA_N1B18
MEM_QKB_N1V13
RFU6R8
C563
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
USB Ports
PLACE NEAR USB3320
USB 2.0 OTG
USB INTERFACE
Current limit for Rseti of 137k is 1.013A
USB FPGA INTERFACE
MAX USB
USB HPS Port
USB TI GUI Port
REFSEL[2:0] = 0X7, Reference Frequency = 24Mhz
USB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7
USB_IDUSB_D_PUSB_D_N
USB_CLKRUSB_NXTRUSB_DIRR
USB_RBIAS
USB_XIUSB_XO
USB_CPEN
USB_VBUS
USB_VFlagn
USB_RESET_PHY
USB_RESET_PHY
USB_STP
5V_F_USB
USB_F_RESET_PHY
USB_F_D_PUSB_F_D_N
reg_out
USB_DATA020USB_DATA120USB_DATA220USB_DATA320USB_DATA420USB_DATA520USB_DATA620USB_DATA720
IO_3V3 69
IO_5V 50
USB_RESET35
USB_CLK20
USB_NXT20
USB_DIR20
USB_STP20
USB_MAXV_RESET36USB_MAXV_TXEn 36USB_MAXV_RXFn 36
USB_MAXV_RDn36
USB_MAXV_WR36
USB_MAXV_D336
USB_MAXV_D036USB_MAXV_D136USB_MAXV_D236
USB_MAXV_D436USB_MAXV_D536USB_MAXV_D636USB_MAXV_D736
IO_1V8 36,37,68
USB_VFlagn35
USB_5.0V
USB_5.0V
USB_5.0V
IO_3V3
IO_5V
IO_5V
IO_3V3
IO_3V3
IO_3V3
USB_FPGA_2.5V
USB_FPGA_3.3V
USB_FPGA_1.8V
USB_FPGA_5.0V USB_FPGA_1.8V
USB_FPGA_1.8V
USB_FPGA_5.0V
USB_FPGA_5.0V
IO_1V8
IO_1V8
IO_1V8
USB_1V8
USB_1V8IO_1V8
USB_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B25 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B25 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B25 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Y4
24MHz13
24
C473
0.1uF
C4
0.1uF
R268 10K
R567
R563
R2275.23K
C471
0.1uF
C10
2.2uF
R103 0
R565
C485
0.1uF
R259
R45DNI
C61 30pF
R267
U22
USB3320
NC
12
VBUS22
CPEN17
ID23
REFSEL111REFSEL08
DATA03
DATA14
DATA25
DATA36
DATA47
DATA59
DATA610
DATA713
DP18DM19
RESET27
SPK_r16
NXT2
DIR31
STP29
CLKOUT1
VD
D1.
830
VB
AT
21V
DD
3.3
20
VD
D1.
828
SPK_L15
XO25
REFCLK26
VD
DIO
32
REFSEL214
GND_FLAG33
RBIAS24
C5 4.7uF
VBUSD-
D+ID
J4MICRO_USB_CONN
12345
6 7 8 9
C881
1uF
R100 1.00K
R246
C4834.7uF
C4584.7uF
R2284.7K
C460
0.1uF
R766 0
R561
C62 30pF
R564
R266 0
R102 10
R264
C1530.01uF
U4
MAX14523B
IN5
OUT4
ON7 GND
8FLAG2
NC26
SETI3NC1
1
GND_PAD9
C171 0.01uF
R265
C459
0.1uF
R263
R17
137K
1%
L143A, 30 Ohm FB
R1018.06K
R566
C889
1uF
C168 4.7uF
R513DNI
R98 1.00K
R104 10
R24510K
R105 10
R30210K
R56010K
VBUSD-
D+ID
J47MICRO_USB_CONN
12345
6 7 8 9
C484
0.1uF
U33
FT245RQ
GND17GND4
DATA030
DATA12
DATA232
DATA38
DATA431
DATA56
DATA67
DATA73
USBDP14USBDM15
RESET#18
OSCO28
RXF#22TXE#21
OSCI27
NC
429
VC
C19
3V3V
OU
T16
WR11 PWREN#
9
VC
CIO
1
GND_PAD33
NC
05
NC
112
NC
213
NC
325
NC
523
GND20
AGND24
TEST26
RD#10
C472
0.1uF
R1061M
R562
R991.00K
R7672.21K
U32
LT3010
OUT1
SENSE2
NC33
GND4
SHDNn5 NC66 NC77 IN8
EPAD9
R262
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
UART to USB PORT
UART
DMA_N
PWR_ENA
UARTA_TX_LEDUARTA_RX_LED
DPA_P
RESET_HPS_UARTA_N
UARTA_TX35UARTA_RX35
RESET_HPS_UARTA_N35
IO_3V369
3.3V_USB_UARTA
3.3V_USB_UARTA
VIO_USB_UARTA
5V_USB_UARTA
3.3V_USB_UARTA VIO_USB_UARTA 5V_USB_UARTA
5V_USB_UARTA
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B26 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B26 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B26 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C275
39pF
J18
DNI
12
TP43
XJ2
881545-2
D12Green_LED
R82 0L4
742792780
C286
4.7uF
R368220
C257
39pF
C293
2.2uF
R83DNI
C27
2.2uF
C285
0.1uF
C294
0.1uFR64 10K
U13
FT232R
VCCIO1RXD
2
RI3
GN
D1
4
NC35
DSR6
DCD7
CTS8
CBUS49
CBUS210
USBDP14
NC513NC412
CBUS311
GN
D2
17
USBDM15
3V3OUT16
RESET18
VCC19
CBUS022 NC2
23
AG
ND
24
CBUS121
GN
D3
20
NC125
OSCO28
NC629
TXD30
DTR31
RTS32
OSCI27
TES
T26
EP
AD
_GN
D33
U41
TPD4S012DRYR
VB
US
6
ID3
D+
1
D-
2
NC
5G
ND
4
R356 10K
C276
0.1uF
D11Green_LED
R56 0
J10
USB MINI-B-SMT
12345
6 7 8 9
10 11
R366220
R357
4.7K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPBA 1.8V IOs for File Flash and Debug port
UART_TX
UART_RX
FPGA_PMVIDTSENSE_FAN_CNTL
VID_SCL_1V8VID_SDA_1V8
FPGA_IO0FPGA_IO1
FPGA_IO3
FPGA_IO2
FPGA_IO0FPGA_IO1FPGA_IO2FPGA_IO3
FPGA_IO[3:0]
MAIN_12V 49
FAN_EN 35
PCIE1V8_PERSTn35,36
PCIE1V8_PERST1n35,36
DEV_CLRN35CRCERROR35
IO_1V8 36,37,68
CVP_CONFDONE35
CLKUSR39
CLK_50M_FPGA35USB_FPGA_CLK37
DP_AUX_CH_P15DP_AUX_CH_N15
PS_D035FILE_DIO023
FILE_DIO1023
FILE_DIO1223FILE_DIO1123
FILE_DIO1323
FILE_DIO123FILE_DIO223
FILE_DIO423FILE_DIO323
FILE_DIO523
FILE_DIO823FILE_DIO923
FILE_DIO623FILE_DIO723
IO_3V3 69
PMbus_SDA_3V3 45,51,56,73PMbus_SCL_3V3 45,51,56,73
A10PMBUSEN 35
FPGAIO_N36FPGAIO_P36
FPGAIO1_N36FPGAIO1_P36
FTRACE_D1123,38
FTRACE_D823,38
FTRACE_D1023,38FTRACE_D923,38
FTRACE_D1323,38FTRACE_D1223,38
FTRACE_D1523,38FTRACE_D1423,38
FTRACE_D323,38
FTRACE_D023,38
FTRACE_D223,38FTRACE_D123,38
FTRACE_D523,38FTRACE_D423,38
FTRACE_D723,38
FTRACE_D623,38
FPGA_IO435
FPGA_IO535
FTRACE_CLK23,38
FPGAIO10_N36FPGAIO10_P36
FPGAIO11_N36FPGAIO11_P36
FPGAIO12_N36FPGAIO12_P36
ENETA_MDIO11ENETA_MDC11ENETB_MDIO12ENETB_MDC12
IO_2V5 36,68
ENET_DISABLE_N35
IO_1V8
IO_1V8
IO_3V3
IO_3V3
IO_1V8
IO_1V8
IO_2V5
IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B27 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B27 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B27 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R325 4.7K
R550 10K
C208
0.1uF
R324 4.7K
J41
22_23_2021
12
C209
0.1uF
B3
FAN_2pin_Conn
C482
0.1uF
R40761.00kC470
0.1uF
IO BANK 2A, 1V8 BANK
A10SOC_1517
U23L
IO, LVDS2A_1N, DQ28L, DATA0AH18
IO, LVDS2A_1P, DQ28L, DATA1AJ18
IO, LVDS2A_2N, DQ28L, DATA2AH17
IO, LVDS2A_2P, DQ28L, DATA3AJ16
IO, LVDS2A_3N, DQ28L, DATA4AK17
IO, LVDS2A_3P, DQ28L, DATA5AK16
IO, LVDS2A_4N, DQSN28L, DATA6AK18
IO, LVDS2A_4P, DQS28L, DATA7AL17
IO, LVDS2A_5N, DQ28L, DATA8AH19
IO, LVDS2A_5P, DQ28L, DATA9AJ19
IO, LVDS2A_6N, DQ28L, DATA10AL19
IO, LVDS2A_6P, DQ28L, DATA11AL18
IO, LVDS2A_7N, DQ29L, DATA12AM17
IO, LVDS2A_7P, DQ29L, DATA13AN17
IO, LVDS2A_8N, DQ29L, DATA14AM20
IO, LVDS2A_8P, DQ29L, DATA15AM19
IO, LVDS2A_9N, DQ29L, DATA16AM16
IO, LVDS2A_9P, DQ29L, DATA17AN16
IO, PLL_2A_CLKOUT1N, LVDS2A_10N, DQSN29L, DATA18AP16
IO, PLL_2A_CLKOUT1P, PLL_2A_CLKOUT1, PLL_2A_FB1, LVDS2A_10P, DQS29L, DATA19AR16
IO, LVDS2A_11N, DQ29L, NCEOAN19
IO, RZQ_2A, LVDS2A_11P, DQ29LAP19
IO, CLK_2A_1N, LVDS2A_12N, DQ29L, DATA20AN18
IO, CLK_2A_1P, LVDS2A_12P, DQ29L, DATA21AP18
IO, CLK_2A_0N, LVDS2A_13N, DQ30L, DATA22AR18
IO, CLK_2A_0P, LVDS2A_13P, DQ30L, DATA23AT18
IO, LVDS2A_14N, DQ30L, DATA24AR17
IO, LVDS2A_14P, DQ30L, DATA25AT17
IO, PLL_2A_CLKOUT0N, LVDS2A_15N, DQ30L, DATA26AT19
IO, PLL_2A_CLKOUT0P, PLL_2A_CLKOUT0, PLL_2A_FB0, LVDS2A_15P, DQ30L, DATA27AU19
IO, LVDS2A_16N, DQSN30L, DATA28AT20
IO, LVDS2A_16P, DQS30L, DATA29AU20
IO, LVDS2A_17N, DQ30L, DATA30AU17
IO, LVDS2A_17P, DQ30L, DATA31AU16
IO, LVDS2A_18N, DQ30L, CLKUSRAP20
IO, LVDS2A_18P, DQ30L, PR_REQUESTAR20
IO, LVDS2A_19N, DQ31L, PR_READYAV16
IO, LVDS2A_19P, DQ31L, NPERSTL0AW16
IO, LVDS2A_20N, DQ31L, PR_DONEAV19
IO, LVDS2A_20P, DQ31L, NPERSTL1AV18
IO, LVDS2A_21N, DQ31L, PR_ERRORAV17
IO, LVDS2A_21P, DQ31LAW18
IO, LVDS2A_22N, DQSN31L, CVP_CONFDONEAV22
IO, LVDS2A_22P, DQS31LAW21
IO, LVDS2A_23N, DQ31L, INIT_DONEAW20
IO, LVDS2A_23P, DQ31L, DEV_OEAW19
IO, LVDS2A_24N, DQ31L, CRCERRORAU21
IO, LVDS2A_24P, DQ31L, DEV_CLRNAV21
C207
0.1uF
Q43
FDV305N
D
G
S
U58
FXMA2102UMX
A02
A13B0
7
B16
VCCA1
GND4
OE5
VCCB8
R327 4.7K
2I IO BANK, 1V8 BANK
A10SOC_1517
U23X
DNU1AV29
DNU2AV30
IO, LVDS2I_7N, DQ13LAT22
IO, LVDS2I_7P, DQ13LAU22
IO, LVDS2I_8N, DQ13LAR22
IO, LVDS2I_8P, DQ13LAR23
IO, LVDS2I_9N, DQ13LAL22
IO, LVDS2I_9P, DQ13LAM22
IO, PLL_2I_CLKOUT1N, LVDS2I_10N, DQSN13LAP21
IO, PLL_2I_CLKOUT1P, PLL_2I_CLKOUT1, PLL_2I_FB1, LVDS2I_10P, DQS13LAR21
IO, LVDS2I_11N, DQ13LAN22
IO, RZQ_2I, LVDS2I_11P, DQ13LAN21
IO, CLK_2I_1N, LVDS2I_12N, DQ13LAL20
IO, CLK_2I_1P, LVDS2I_12P, DQ13LAM21
DNU3AG16
DNU4AG17
DNU5AF17
NC1A2
NC2A3
NC3AE20
NC4AF20
NC5AG20
NC6AG21
NC7AG22
NC8AH21
NC9AH22
NC10AJ20
NC11AJ21
NC12AK20
NC13AK21
NC14AK22
NC15AV1
NC16AV2
NC17AV3
NC18AW2
NC19AW3
NC20B1
NC21P19
NC22W15
NC23W16
R326 4.7K
R525 10K
U37
MAX3378
VL1
IO VL12
IO VL23
IO VL34
IO VL45
NC16
GND7
VCC14
IO VCC113
IO VCC212
IO VCC311
IO VCC410
NC29
/TS8
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA IOs for LVDS links of FMC A Port
RZQ_3G
RZQ_3H
FALAP017FALAN017
FALAP217FALAN217FALAP317FALAN317
FALAP417
FALAN417
FALAP617FALAN617
FALAP717FALAN717
FALAP817FALAN817
FALAP917FALAN917
FALAP1017FALAN1017
FALAP1117FALAN1117
FALAP1617FALAN1617
FAHAP017FAHAN017
FAHAP117FAHAN117
FAHAP217FAHAN217
FAHAP317FAHAN317
FAHAP417FAHAN417
FAHAP517FAHAN517
FAHAP617FAHAN617
FAHAP717FAHAN717
FAHAP817FAHAN817
FAHAP917FAHAN917
FAHAP1017FAHAN1017
FAHAP1117FAHAN1117
FA_LA_DEVCLK_P43FA_LA_DEVCLK_N43
FA_LA_SYSREF_N43FA_LA_SYSREF_P43
FPGA_RCLK_3Gp43FPGA_RCLK_3Gn43
FA_EMI_CLKN43
FA_EMI_CLKP43
FALAP1817FALAN1817FALAP1917FALAN1917
FAHAP2017FAHAN2017
FAHAP2117FAHAN2117
FAHAP2317FAHAN2317
FAHAP1817FAHAN1817
FALAP1217FALAN1217FALAP1317FALAN1317
FALAP1417FALAN1417
FAHAP1917FAHAN1917
FALAP1717FALAN1717
FALAP2017FALAN2017
FALAP2117FALAN2117
FAHAP2217FAHAN2217
FALAP1517FALAN1517
FAHAP1217FAHAN1217
FAHAP1317FAHAN1317
FAHAP1417FAHAN1417
FAHAP1517FAHAN1517
FAHAP1617FAHAN1617
FAHAP1717FAHAN1717
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B28 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B28 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B28 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
IO BANK 3G, 1V8 BANK
A10SOC_1517
U23N
IO, LVDS3G_1N, DQ36RF8
IO, LVDS3G_1P, DQ36RE8
IO, LVDS3G_2N, DQ36RC7
IO, LVDS3G_2P, DQ36RB7
IO, LVDS3G_3N, DQ36RD8
IO, LVDS3G_3P, DQ36RC8
IO, LVDS3G_4N, DQSN36RC6
IO, LVDS3G_4P, DQS36RB6
IO, LVDS3G_5N, DQ36RB5
IO, LVDS3G_5P, DQ36RA5
IO, LVDS3G_6N, DQ36RB4
IO, LVDS3G_6P, DQ36RA4
IO, LVDS3G_7N, DQ37RC4
IO, LVDS3G_7P, DQ37RC3
IO, LVDS3G_8N, DQ37RD3
IO, LVDS3G_8P, DQ37RC2
IO, LVDS3G_9N, DQ37RF7
IO, LVDS3G_9P, DQ37RE7
IO, PLL_3G_CLKOUT1N, LVDS3G_10N, DQSN37RD5
IO, PLL_3G_CLKOUT1P, PLL_3G_CLKOUT1, PLL_3G_FB1, LVDS3G_10P, DQS37RD4
IO, LVDS3G_11N, DQ37RE6
IO, RZQ_3G, LVDS3G_11P, DQ37RD6
IO, CLK_3G_1N, LVDS3G_12N, DQ37RF5
IO, CLK_3G_1P, LVDS3G_12P, DQ37RE5
IO, CLK_3G_0N, LVDS3G_13N, DQ38RH9
IO, CLK_3G_0P, LVDS3G_13P, DQ38RH8
IO, LVDS3G_14N, DQ38RG9
IO, LVDS3G_14P, DQ38RF9
IO, PLL_3G_CLKOUT0N, LVDS3G_15N, DQ38RK8
IO, PLL_3G_CLKOUT0P, PLL_3G_CLKOUT0, PLL_3G_FB0, LVDS3G_15P, DQ38RJ8
IO, LVDS3G_16N, DQSN38RG6
IO, LVDS3G_16P, DQS38RG5
IO, LVDS3G_17N, DQ38RH7
IO, LVDS3G_17P, DQ38RG7
IO, LVDS3G_18N, DQ38RJ6
IO, LVDS3G_18P, DQ38RH6
IO, LVDS3G_19N, DQ39RL10
IO, LVDS3G_19P, DQ39RK10
IO, LVDS3G_20N, DQ39RK11
IO, LVDS3G_20P, DQ39RJ11
IO, LVDS3G_21N, DQ39RN13
IO, LVDS3G_21P, DQ39RM12
IO, LVDS3G_22N, DQSN39RN11
IO, LVDS3G_22P, DQS39RM10
IO, LVDS3G_23N, DQ39RJ10
IO, LVDS3G_23P, DQ39RJ9
IO, LVDS3G_24N, DQ39RN12
IO, LVDS3G_24P, DQ39RM11
R653100
IO BANK 3H, 1V8 BANK
A10SOC_1517
U23M
IO, LVDS3H_1N, DQ32RP15
IO, LVDS3H_1P, DQ32RP14
IO, LVDS3H_2N, DQ32RN14
IO, LVDS3H_2P, DQ32RM14
IO, LVDS3H_3N, DQ32RJ14
IO, LVDS3H_3P, DQ32RJ13
IO, LVDS3H_4N, DQSN32RL15
IO, LVDS3H_4P, DQS32RL14
IO, LVDS3H_5N, DQ32RL13
IO, LVDS3H_5P, DQ32RL12
IO, LVDS3H_6N, DQ32RK13
IO, LVDS3H_6P, DQ32RK12
IO, LVDS3H_7N, DQ33RH14
IO, LVDS3H_7P, DQ33RG14
IO, LVDS3H_8N, DQ33RD14
IO, LVDS3H_8P, DQ33RC14
IO, LVDS3H_9N, DQ33RD13
IO, LVDS3H_9P, DQ33RC13
IO, PLL_3H_CLKOUT1N, LVDS3H_10N, DQSN33RE13
IO, PLL_3H_CLKOUT1P, PLL_3H_CLKOUT1, PLL_3H_FB1, LVDS3H_10P, DQS33RE12
IO, LVDS3H_11N, DQ33RH13
IO, RZQ_3H, LVDS3H_11P, DQ33RH12
IO, CLK_3H_1N, LVDS3H_12N, DQ33RF14
IO, CLK_3H_1P, LVDS3H_12P, DQ33RF13
IO, CLK_3H_0N, LVDS3H_13N, DQ34RC12
IO, CLK_3H_0P, LVDS3H_13P, DQ34RC11
IO, LVDS3H_14N, DQ34RE11
IO, LVDS3H_14P, DQ34RD11
IO, PLL_3H_CLKOUT0N, LVDS3H_15N, DQ34RG12
IO, PLL_3H_CLKOUT0P, PLL_3H_CLKOUT0, PLL_3H_FB0, LVDS3H_15P, DQ34RF12
IO, LVDS3H_16N, DQSN34RG10
IO, LVDS3H_16P, DQS34RF10
IO, LVDS3H_17N, DQ34RE10
IO, LVDS3H_17P, DQ34RD10
IO, LVDS3H_18N, DQ34RH11
IO, LVDS3H_18P, DQ34RG11
IO, LVDS3H_19N, DQ35RB10
IO, LVDS3H_19P, DQ35RA10
IO, LVDS3H_20N, DQ35RB9
IO, LVDS3H_20P, DQ35RA9
IO, LVDS3H_21N, DQ35RB12
IO, LVDS3H_21P, DQ35RB11
IO, LVDS3H_22N, DQSN35RA13
IO, LVDS3H_22P, DQS35RA12
IO, LVDS3H_23N, DQ35RA8
IO, LVDS3H_23P, DQ35RA7
IO, LVDS3H_24N, DQ35RD9
IO, LVDS3H_24P, DQ35RC9
R658DNI
R6700
R6710
R659DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA IOs for LVDS links of FMC A Port and FMC B Port
RZQ_3F
RZQ_3E
FALAP2217FALAN2217
FALAP2317FALAN2317
FALAP2417FALAN2417
FALAP2517FALAN2517
FALAP2617FALAN2617
FALAP2717FALAN2717
FAHBP017FAHBN017
FAHBP117FAHBN117
FAHBP217FAHBN217
FAHBP317FAHBN317
FAHBP417
FAHBN417
FAHBP517FAHBN517
FAHBP617FAHBN617
FAHBP717FAHBN717
FAHBP817FAHBN817
FAHBP917FAHBN917
FAHBP1017FAHBN1017
FAHBP1317FAHBN1317
Refclk_3En43
Refclk_3Ep43
FBLAP2018FBLAN2018
FBLAP2118FBLAN2118
FBLAP2218FBLAN2218
FBLAP2318FBLAN2318
FBLAP2418FBLAN2418
FBLAP2518FBLAN2518
FBLAP2618FBLAN2618
FBLAP2718FBLAN2718
FPGA_Refsys_3Ep43FPGA_Refsys_3En43
FBHA_P643FBHA_N643
FBHA_P1743
FBHA_N1743
FPGAIO2_N36FPGAIO2_P36
FPGAIO3_N36FPGAIO3_P36
FPGAIO6_N36FPGAIO6_P36
FPGAIO7_N36FPGAIO7_P36
FPGAIO4_N36FPGAIO4_P36
FPGAIO5_N36FPGAIO5_P36
FPGAIO8_N36FPGAIO8_P36
FPGAIO9_N36FPGAIO9_P36
FBHA_N2018
FBHA_P2143FBHA_N2143
FBHA_P2218FBHA_N2218
FBHA_P2018
FBHA_P2343FBHA_N2343
FALAP2917FALAN2917
FALAP3017FALAN3017
FALAP3117FALAN3117
FALAP3217FALAN3217FALAP3317FALAN3317
FALAP2817FALAN2817
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B29 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B29 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B29 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R6280
R629DNI
IO BANK 3E, 1V8 BANK
A10SOC_1517
U23P
IO, LVDS3E_1N, DQ44RM2
IO, LVDS3E_1P, DQ44RM1
IO, LVDS3E_2N, DQ44RN4
IO, LVDS3E_2P, DQ44RN3
IO, LVDS3E_3N, DQ44RR3
IO, LVDS3E_3P, DQ44RR2
IO, LVDS3E_4N, DQSN44RN2
IO, LVDS3E_4P, DQS44RN1
IO, LVDS3E_5N, DQ44RR1
IO, LVDS3E_5P, DQ44RP1
IO, LVDS3E_6N, DQ44RP4
IO, LVDS3E_6P, DQ44RP3
IO, LVDS3E_7N, DQ45RP6
IO, LVDS3E_7P, DQ45RP5
IO, LVDS3E_8N, DQ45RT5
IO, LVDS3E_8P, DQ45RR5
IO, LVDS3E_9N, DQ45RU7
IO, LVDS3E_9P, DQ45RT7
IO, PLL_3E_CLKOUT1N, LVDS3E_10N, DQSN45RU6
IO, PLL_3E_CLKOUT1P, PLL_3E_CLKOUT1, PLL_3E_FB1, LVDS3E_10P, DQS45RU5
IO, LVDS3E_11N, DQ45RV7
IO, RZQ_3E, LVDS3E_11P, DQ45RV6
IO, CLK_3E_1N, LVDS3E_12N, DQ45RW6
IO, CLK_3E_1P, LVDS3E_12P, DQ45RW5
IO, CLK_3E_0N, LVDS3E_13N, DQ46RU4
IO, CLK_3E_0P, LVDS3E_13P, DQ46RT4
IO, LVDS3E_14N, DQ46RT3
IO, LVDS3E_14P, DQ46RT2
IO, PLL_3E_CLKOUT0N, LVDS3E_15N, DQ46RU2
IO, PLL_3E_CLKOUT0P, PLL_3E_CLKOUT0, PLL_3E_FB0, LVDS3E_15P, DQ46RU1
IO, LVDS3E_16N, DQSN46RV2
IO, LVDS3E_16P, DQS46RV1
IO, LVDS3E_17N, DQ46RW4
IO, LVDS3E_17P, DQ46RW3
IO, LVDS3E_18N, DQ46RV4
IO, LVDS3E_18P, DQ46RV3
IO, LVDS3E_19N, DQ47RU10
IO, LVDS3E_19P, DQ47RU9
IO, LVDS3E_20N, DQ47RV9
IO, LVDS3E_20P, DQ47RV8
IO, LVDS3E_21N, DQ47RT9
IO, LVDS3E_21P, DQ47RT8
IO, LVDS3E_22N, DQSN47RW10
IO, LVDS3E_22P, DQS47RW9
IO, LVDS3E_23N, DQ47RV11
IO, LVDS3E_23P, DQ47RU11
IO, LVDS3E_24N, DQ47RR7
IO, LVDS3E_24P, DQ47RR6
R609100
IO BANK 3F, 1V8 BANK
A10SOC_1517
U23O
IO, LVDS3F_1N, DQ40RG4
IO, LVDS3F_1P, DQ40RF4
IO, LVDS3F_2N, DQ40RD1
IO, LVDS3F_2P, DQ40RC1
IO, LVDS3F_3N, DQ40RE2
IO, LVDS3F_3P, DQ40RE1
IO, LVDS3F_4N, DQSN40RF3
IO, LVDS3F_4P, DQS40RE3
IO, LVDS3F_5N, DQ40RG2
IO, LVDS3F_5P, DQ40RF2
IO, LVDS3F_6N, DQ40RH2
IO, LVDS3F_6P, DQ40RG1
IO, LVDS3F_7N, DQ41RJ5
IO, LVDS3F_7P, DQ41RJ4
IO, LVDS3F_8N, DQ41RJ1
IO, LVDS3F_8P, DQ41RH1
IO, LVDS3F_9N, DQ41RH4
IO, LVDS3F_9P, DQ41RH3
IO, PLL_3F_CLKOUT1N, LVDS3F_10N, DQSN41RK2
IO, PLL_3F_CLKOUT1P, PLL_3F_CLKOUT1, PLL_3F_FB1, LVDS3F_10P, DQS41RK1
IO, LVDS3F_11N, DQ41RL3
IO, RZQ_3F, LVDS3F_11P, DQ41RL2
IO, CLK_3F_1N, LVDS3F_12N, DQ41RK3
IO, CLK_3F_1P, LVDS3F_12P, DQ41RJ3
IO, CLK_3F_0N, LVDS3F_13N, DQ42RN7
IO, CLK_3F_0P, LVDS3F_13P, DQ42RN6
IO, LVDS3F_14N, DQ42RK6
IO, LVDS3F_14P, DQ42RK5
IO, PLL_3F_CLKOUT0N, LVDS3F_15N, DQ42RL7
IO, PLL_3F_CLKOUT0P, PLL_3F_CLKOUT0, PLL_3F_FB0, LVDS3F_15P, DQ42RK7
IO, LVDS3F_16N, DQSN42RM7
IO, LVDS3F_16P, DQS42RM6
IO, LVDS3F_17N, DQ42RM4
IO, LVDS3F_17P, DQ42RL4
IO, LVDS3F_18N, DQ42RM5
IO, LVDS3F_18P, DQ42RL5
IO, LVDS3F_19N, DQ43RP10
IO, LVDS3F_19P, DQ43RN9
IO, LVDS3F_20N, DQ43RM9
IO, LVDS3F_20P, DQ43RN8
IO, LVDS3F_21N, DQ43RR10
IO, LVDS3F_21P, DQ43RP9
IO, LVDS3F_22N, DQSN43RR8
IO, LVDS3F_22P, DQS43RP8
IO, LVDS3F_23N, DQ43RR11
IO, LVDS3F_23P, DQ43RP11
IO, LVDS3F_24N, DQ43RL9
IO, LVDS3F_24P, DQ43RL8
R6410
R642DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA IOs for LVDS links of FMC B Port
RZQ_3A
FBLAP018FBLAN018
FBLAP218FBLAN218
FBLAP318FBLAN318
FBLAP418FBLAN418
FBLAP618FBLAN618
FBLAP718FBLAN718
FBLAP818FBLAN818
FBLAP918FBLAN918
FBLAP1018
FBLAN1018
FBLAP1118FBLAN1118
FBLAP1218FBLAN1218
FBLAP1318FBLAN1318
FBLAP1418FBLAN1418
FBLAP1518FBLAN1518
FBLAP1618FBLAN1618
FBLAP1718FBLAN1718
FBLAP1818FBLAN1818
FBLAP1918FBLAN1918
FBCLK0M2CN18
FBCLK0M2CP18
Refclk_3An43
Refclk_3Ap43
FMB_SYNC_CD18FMB_SYNC_AB18
FMB_SYNCP18FMB_SYNCN18
FB_LA_DEVCLK_P43FB_LA_DEVCLK_N43
FB_LA_SYSREF_P43FB_LA_SYSREF_N43
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B30 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B30 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B30 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R5330
R570DNI
R569100
IO BANK 3A, 1V8 BANK
A10SOC_1517
U23V
IO, LVDS3A_1N, DQ60RAU7
IO, LVDS3A_1P, DQ60RAV7
IO, LVDS3A_2N, DQ60RAT8
IO, LVDS3A_2P, DQ60RAT7
IO, LVDS3A_3N, DQ60RAT10
IO, LVDS3A_3P, DQ60RAT9
IO, LVDS3A_4N, DQSN60RAV8
IO, LVDS3A_4P, DQS60RAW8
IO, LVDS3A_5N, DQ60RAU9
IO, LVDS3A_5P, DQ60RAV9
IO, LVDS3A_6N, DQ60RAW10
IO, LVDS3A_6P, DQ60RAW9
IO, LVDS3A_7N, DQ61RAP8
IO, LVDS3A_7P, DQ61RAR8
IO, LVDS3A_8N, DQ61RAU11
IO, LVDS3A_8P, DQ61RAU10
IO, LVDS3A_9N, DQ61RAN9
IO, LVDS3A_9P, DQ61RAP9
IO, PLL_3A_CLKOUT1N, LVDS3A_10N, DQSN61RAP10
IO, PLL_3A_CLKOUT1P, PLL_3A_CLKOUT1, PLL_3A_FB1, LVDS3A_10P, DQS61RAR10
IO, LVDS3A_11N, DQ61RAR12
IO, RZQ_3A, LVDS3A_11P, DQ61RAT12
IO, CLK_3A_1N, LVDS3A_12N, DQ61RAP11
IO, CLK_3A_1P, LVDS3A_12P, DQ61RAR11
IO, CLK_3A_0N, LVDS3A_13N, DQ62RAL10
IO, CLK_3A_0P, LVDS3A_13P, DQ62RAM10
IO, LVDS3A_14N, DQ62RAK12
IO, LVDS3A_14P, DQ62RAK11
IO, PLL_3A_CLKOUT0N, LVDS3A_15N, DQ62RAL12
IO, PLL_3A_CLKOUT0P, PLL_3A_CLKOUT0, PLL_3A_FB0, LVDS3A_15P, DQ62RAM12
IO, LVDS3A_16N, DQSN62RAM11
IO, LVDS3A_16P, DQS62RAN11
IO, LVDS3A_17N, DQ62RAL14
IO, LVDS3A_17P, DQ62RAL13
IO, LVDS3A_18N, DQ62RAN13
IO, LVDS3A_18P, DQ62RAN12
IO, LVDS3A_19N, DQ63RAJ15
IO, LVDS3A_19P, DQ63RAK15
IO, LVDS3A_20N, DQ63RAH13
IO, LVDS3A_20P, DQ63RAH12
IO, LVDS3A_21N, DQ63RAJ13
IO, LVDS3A_21P, DQ63RAK13
IO, LVDS3A_22N, DQSN63RAF14
IO, LVDS3A_22P, DQS63RAG14
IO, LVDS3A_23N, DQ63RAH14
IO, LVDS3A_23P, DQ63RAJ14
IO, LVDS3A_24N, DQ63RAF15
IO, LVDS3A_24P, DQ63RAG15
R573100
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA IOs for FPGA Memory Interface
RZQ_3CRZQ_3D
MEM_DMB034MEM_DQB134
MEM_DQB034
MEM_DMB334
MEM_DMB234
MEM_DMB134
MEM_DQB734
MEM_DQB634MEM_DQB534
MEM_DQB434
MEM_DQB334MEM_DQB234
MEM_DQB934MEM_DQB834
MEM_DQB1434
MEM_DQB1334
MEM_DQB1234
MEM_DQB1134MEM_DQB1034
MEM_DQB1934MEM_DQB1834MEM_DQB1734
MEM_DQB1634
MEM_DQB1534
MEM_DQB2134
MEM_DQB2034
MEM_DQB2634MEM_DQB2534
MEM_DQB2434
MEM_DQB2334
MEM_DQB2234
MEM_DQB2934MEM_DQB2834
MEM_DQB2734
MEM_DQB3234
MEM_DQB3134MEM_DQB3034MEM_DQB3334
MEM_DQSB_N034MEM_DQSB_P034
MEM_DQSB_P334
MEM_DQSB_N234MEM_DQSB_P234
MEM_DQSB_N134MEM_DQSB_P134
MEM_DQSB_N334
MEM_QKB_P134
MEM_QKB_P034
MEM_ADDR_CMD1734MEM_ADDR_CMD1634
MEM_ADDR_CMD1534
MEM_ADDR_CMD1934MEM_ADDR_CMD2634
MEM_ADDR_CMD1234
MEM_ADDR_CMD1434
MEM_ADDR_CMD1034MEM_ADDR_CMD934
MEM_ADDR_CMD634
MEM_ADDR_CMD834MEM_ADDR_CMD734
MEM_ADDR_CMD1334
MEM_ADDR_CMD1134
MEM_ADDR_CMD534
MEM_ADDR_CMD234
MEM_ADDR_CMD034
MEM_ADDR_CMD3034
MEM_ADDR_CMD134
MEM_ADDR_CMD3134
MEM_ADDR_CMD434MEM_ADDR_CMD334
MEM_CLK_N34MEM_CLK_P34
MEM_ADDR_CMD2534
MEM_ADDR_CMD2134MEM_ADDR_CMD2034
MEM_ADDR_CMD2234
MEM_ADDR_CMD2434MEM_ADDR_CMD2334
MEM_ADDR_CMD2734MEM_ADDR_CMD2834
MEM_DQS_ADDR_CMD_P34MEM_DQS_ADDR_CMD_N34
MEM_DQ_ADDR_CMD034
MEM_DQ_ADDR_CMD134MEM_DQ_ADDR_CMD234
MEM_DQ_ADDR_CMD434MEM_DQ_ADDR_CMD334
MEM_DQ_ADDR_CMD534
MEM_DQ_ADDR_CMD634MEM_DQ_ADDR_CMD734MEM_DQ_ADDR_CMD834
MEM_ADDR_CMD2934MEM_ADDR_CMD1834
CLK_EMI_P40
CLK_EMI_N40
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B31 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B31 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B31 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
IO BANK 3D, 1V8 BANK
A10SOC_1517
U23R
IO, LVDS3D_1N, DQ48RW8
IO, LVDS3D_1P, DQ48RY8
IO, LVDS3D_2N, DQ48RY10
IO, LVDS3D_2P, DQ48RAA9
IO, LVDS3D_3N, DQ48RAB11
IO, LVDS3D_3P, DQ48RAA10
IO, LVDS3D_4N, DQSN48RAA8
IO, LVDS3D_4P, DQS48RAA7
IO, LVDS3D_5N, DQ48RAB10
IO, LVDS3D_5P, DQ48RAB9
IO, LVDS3D_6N, DQ48RAB7
IO, LVDS3D_6P, DQ48RAC7
IO, LVDS3D_7N, DQ49RY7
IO, LVDS3D_7P, DQ49RY6
IO, LVDS3D_8N, DQ49RY5
IO, LVDS3D_8P, DQ49RAA5
IO, LVDS3D_9N, DQ49RAD5
IO, LVDS3D_9P, DQ49RAD4
IO, PLL_3D_CLKOUT1N, LVDS3D_10N, DQSN49RAE6
IO, PLL_3D_CLKOUT1P, PLL_3D_CLKOUT1, PLL_3D_FB1, LVDS3D_10P, DQS49RAE5
IO, LVDS3D_11N, DQ49RAC6
IO, RZQ_3D, LVDS3D_11P, DQ49RAD6
IO, CLK_3D_1N, LVDS3D_12N, DQ49RAB6
IO, CLK_3D_1P, LVDS3D_12P, DQ49RAB5
IO, CLK_3D_0N, LVDS3D_13N, DQ50RY3
IO, CLK_3D_0P, LVDS3D_13P, DQ50RY2
IO, LVDS3D_14N, DQ50RW1
IO, LVDS3D_14P, DQ50RY1
IO, PLL_3D_CLKOUT0N, LVDS3D_15N, DQ50RAA4
IO, PLL_3D_CLKOUT0P, PLL_3D_CLKOUT0, PLL_3D_FB0, LVDS3D_15P, DQ50RAB4
IO, LVDS3D_16N, DQSN50RAA3
IO, LVDS3D_16P, DQS50RAA2
IO, LVDS3D_17N, DQ50RAB2
IO, LVDS3D_17P, DQ50RAB1
IO, LVDS3D_18N, DQ50RAC4
IO, LVDS3D_18P, DQ50RAC3
IO, LVDS3D_19N, DQ51RAC1
IO, LVDS3D_19P, DQ51RAD1
IO, LVDS3D_20N, DQ51RAD3
IO, LVDS3D_20P, DQ51RAC2
IO, LVDS3D_21N, DQ51RAF2
IO, LVDS3D_21P, DQ51RAG2
IO, LVDS3D_22N, DQSN51RAG1
IO, LVDS3D_22P, DQS51RAH1
IO, LVDS3D_23N, DQ51RAE2
IO, LVDS3D_23P, DQ51RAE1
IO, LVDS3D_24N, DQ51RAE3
IO, LVDS3D_24P, DQ51RAF3
R582100
R590DNI
R583 240
IO BANK 3C, 1V8 BANK
A10SOC_1517
U23S
IO, LVDS3C_1N, DQ52RAC9
IO, LVDS3C_1P, DQ52RAC8
IO, LVDS3C_2N, DQ52RAE11
IO, LVDS3C_2P, DQ52RAE10
IO, LVDS3C_3N, DQ52RAD9
IO, LVDS3C_3P, DQ52RAD8
IO, LVDS3C_4N, DQSN52RAE8
IO, LVDS3C_4P, DQS52RAF8
IO, LVDS3C_5N, DQ52RAC11
IO, LVDS3C_5P, DQ52RAD10
IO, LVDS3C_6N, DQ52RAF10
IO, LVDS3C_6P, DQ52RAF9
IO, LVDS3C_7N, DQ53RAG4
IO, LVDS3C_7P, DQ53RAH4
IO, LVDS3C_8N, DQ53RAF5
IO, LVDS3C_8P, DQ53RAF4
IO, LVDS3C_9N, DQ53RAE7
IO, LVDS3C_9P, DQ53RAF7
IO, PLL_3C_CLKOUT1N, LVDS3C_10N, DQSN53RAH3
IO, PLL_3C_CLKOUT1P, PLL_3C_CLKOUT1, PLL_3C_FB1, LVDS3C_10P, DQS53RAJ3
IO, LVDS3C_11N, DQ53RAG7
IO, RZQ_3C, LVDS3C_11P, DQ53RAH7
IO, CLK_3C_1N, LVDS3C_12N, DQ53RAG6
IO, CLK_3C_1P, LVDS3C_12P, DQ53RAG5
IO, CLK_3C_0N, LVDS3C_13N, DQ54RAH6
IO, CLK_3C_0P, LVDS3C_13P, DQ54RAJ5
IO, LVDS3C_14N, DQ54RAJ4
IO, LVDS3C_14P, DQ54RAK3
IO, PLL_3C_CLKOUT0N, LVDS3C_15N, DQ54RAJ6
IO, PLL_3C_CLKOUT0P, PLL_3C_CLKOUT0, PLL_3C_FB0, LVDS3C_15P, DQ54RAK6
IO, LVDS3C_16N, DQSN54RAK5
IO, LVDS3C_16P, DQS54RAL5
IO, LVDS3C_17N, DQ54RAL4
IO, LVDS3C_17P, DQ54RAL3
IO, LVDS3C_18N, DQ54RAM4
IO, LVDS3C_18P, DQ54RAN3
IO, LVDS3C_19N, DQ55RAH2
IO, LVDS3C_19P, DQ55RAJ1
IO, LVDS3C_20N, DQ55RAK2
IO, LVDS3C_20P, DQ55RAK1
IO, LVDS3C_21N, DQ55RAN1
IO, LVDS3C_21P, DQ55RAM1
IO, LVDS3C_22N, DQSN55RAR2
IO, LVDS3C_22P, DQS55RAR1
IO, LVDS3C_23N, DQ55RAL2
IO, LVDS3C_23P, DQ55RAM2
IO, LVDS3C_24N, DQ55RAN2
IO, LVDS3C_24P, DQ55RAP1
R5890
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA IOs for FPGA Memory Interface
RZQ_3B
MEM_DQA034
MEM_DMA334
MEM_DMA234
MEM_DMA134
MEM_DMA034
MEM_DQA534MEM_DQA434
MEM_DQA334
MEM_DQA234MEM_DQA134
MEM_DQA1134MEM_DQA1034
MEM_DQA934MEM_DQA834
MEM_DQA734
MEM_DQA634
MEM_DQA1634
MEM_DQA1534
MEM_DQA1434
MEM_DQA1334
MEM_DQA1234
MEM_DQA2134
MEM_DQA2034MEM_DQA1934
MEM_DQA1834
MEM_DQA1734
MEM_DQA2734
MEM_DQA2634MEM_DQA2534
MEM_DQA2434
MEM_DQA2334
MEM_DQA2234
MEM_DQA3234
MEM_DQA3134
MEM_DQA3034MEM_DQA2934
MEM_DQA2834
MEM_DQSA_N134MEM_DQSA_P134
MEM_DQSA_N034MEM_DQSA_P034
MEM_DQA3334
MEM_QKA_P134
MEM_QKA_P034
MEM_DQSA_N334MEM_DQSA_P334
MEM_DQSA_N234MEM_DQSA_P234
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B32 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B32 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B32 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R572DNI
IO BANK 3B, 1V8 BANK
A10SOC_1517
U23U
IO, LVDS3B_1N, DQ56RAH8
IO, LVDS3B_1P, DQ56RAJ8
IO, LVDS3B_2N, DQ56RAH9
IO, LVDS3B_2P, DQ56RAJ9
IO, LVDS3B_3N, DQ56RAF12
IO, LVDS3B_3P, DQ56RAG12
IO, LVDS3B_4N, DQSN56RAG10
IO, LVDS3B_4P, DQS56RAG9
IO, LVDS3B_5N, DQ56RAG11
IO, LVDS3B_5P, DQ56RAH11
IO, LVDS3B_6N, DQ56RAJ11
IO, LVDS3B_6P, DQ56RAJ10
IO, LVDS3B_7N, DQ57RAK7
IO, LVDS3B_7P, DQ57RAL7
IO, LVDS3B_8N, DQ57RAM6
IO, LVDS3B_8P, DQ57RAN6
IO, LVDS3B_9N, DQ57RAK8
IO, LVDS3B_9P, DQ57RAL8
IO, PLL_3B_CLKOUT1N, LVDS3B_10N, DQSN57RAM7
IO, PLL_3B_CLKOUT1P, PLL_3B_CLKOUT1, PLL_3B_FB1, LVDS3B_10P, DQS57RAN7
IO, LVDS3B_11N, DQ57RAM9
IO, RZQ_3B, LVDS3B_11P, DQ57RAN8
IO, CLK_3B_1N, LVDS3B_12N, DQ57RAK10
IO, CLK_3B_1P, LVDS3B_12P, DQ57RAL9
IO, CLK_3B_0N, LVDS3B_13N, DQ58RAM5
IO, CLK_3B_0P, LVDS3B_13P, DQ58RAN4
IO, LVDS3B_14N, DQ58RAP3
IO, LVDS3B_14P, DQ58RAR3
IO, PLL_3B_CLKOUT0N, LVDS3B_15N, DQ58RAP5
IO, PLL_3B_CLKOUT0P, PLL_3B_CLKOUT0, PLL_3B_FB0, LVDS3B_15P, DQ58RAP4
IO, LVDS3B_16N, DQSN58RAP6
IO, LVDS3B_16P, DQS58RAR5
IO, LVDS3B_17N, DQ58RAU2
IO, LVDS3B_17P, DQ58RAU1
IO, LVDS3B_18N, DQ58RAT3
IO, LVDS3B_18P, DQ58RAT2
IO, LVDS3B_19N, DQ59RAT5
IO, LVDS3B_19P, DQ59RAT4
IO, LVDS3B_20N, DQ59RAR7
IO, LVDS3B_20P, DQ59RAR6
IO, LVDS3B_21N, DQ59RAU4
IO, LVDS3B_21P, DQ59RAV4
IO, LVDS3B_22N, DQSN59RAV6
IO, LVDS3B_22P, DQS59RAW6
IO, LVDS3B_23N, DQ59RAU6
IO, LVDS3B_23P, DQ59RAU5
IO, LVDS3B_24N, DQ59RAW5
IO, LVDS3B_24P, DQ59RAW4
R5320
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
UART Port B
DB9_TX
DB9_RXIO_3V369
UART1_TX35
UART1_RX35
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B33 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B33 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B33 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C598
0.1uF
C670
0.1uFC597
0.1uFJ25
61800925023
594837261
10 11
U61
MAX3221
EN_n1
FORCEOFF_N16
C1+2
C1-4
C2+5
C2-6
V+3
V-7
RIN8
ROUT9
DIN11
DOUT13
INVALID10
FORCEON12
GND14
VCC15
C635
0.1uF
C669
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
External Memory Interface - HiLo connector
Place nearHILO connectorJ14 VDD pins
Place nearHILO connectorJ14 VDDQ pins
HILO_VDD63
HILO_VDDQ64
HILOQ_1V2_SETn64HILOQ_1V25_SETn64
HILOQ_1V35_SETn64HILOQ_1V5_SETn64HILOQ_1V8_SETn64
HILO_1V2_SETn63
HILO_1V5_SETn63HILO_1V35_SETn63
HILO_1V25_SETn63
HILO_1V8_SETn63
MEM_CLK_P 31MEM_CLK_N 31
MEM_DQS_ADDR_CMD_P 31MEM_DQS_ADDR_CMD_N 31
MEM_DQ_ADDR_CMD0 31MEM_DQ_ADDR_CMD1 31MEM_DQ_ADDR_CMD2 31MEM_DQ_ADDR_CMD3 31MEM_DQ_ADDR_CMD4 31MEM_DQ_ADDR_CMD5 31MEM_DQ_ADDR_CMD6 31MEM_DQ_ADDR_CMD7 31MEM_DQ_ADDR_CMD8 31
MEM_DMB0 31MEM_DMB1 31MEM_DMB2 31MEM_DMB3 31
MEM_DQB0 31MEM_DQB1 31MEM_DQB2 31MEM_DQB3 31MEM_DQB4 31MEM_DQB5 31MEM_DQB6 31MEM_DQB7 31MEM_DQB8 31MEM_DQB9 31MEM_DQB10 31MEM_DQB11 31MEM_DQB12 31MEM_DQB13 31MEM_DQB14 31MEM_DQB15 31MEM_DQB16 31MEM_DQB17 31MEM_DQB18 31MEM_DQB19 31MEM_DQB20 31MEM_DQB21 31MEM_DQB22 31MEM_DQB23 31MEM_DQB24 31MEM_DQB25 31MEM_DQB26 31MEM_DQB27 31MEM_DQB28 31MEM_DQB29 31MEM_DQB30 31MEM_DQB31 31MEM_DQB32 31MEM_DQB33 31
MEM_DQSB_P0 31MEM_DQSB_N0 31MEM_DQSB_P1 31MEM_DQSB_N1 31MEM_DQSB_P2 31MEM_DQSB_N2 31MEM_DQSB_P3 31MEM_DQSB_N3 31
MEM_QKB_P0 31MEM_QKB_P1 31
MEM_ADDR_CMD031MEM_ADDR_CMD131MEM_ADDR_CMD231MEM_ADDR_CMD331MEM_ADDR_CMD431MEM_ADDR_CMD531MEM_ADDR_CMD631MEM_ADDR_CMD731MEM_ADDR_CMD831MEM_ADDR_CMD931MEM_ADDR_CMD1031MEM_ADDR_CMD1131MEM_ADDR_CMD1231MEM_ADDR_CMD1331MEM_ADDR_CMD1431MEM_ADDR_CMD1531MEM_ADDR_CMD1631MEM_ADDR_CMD1731MEM_ADDR_CMD1831MEM_ADDR_CMD1931MEM_ADDR_CMD2031MEM_ADDR_CMD2131MEM_ADDR_CMD2231MEM_ADDR_CMD2331MEM_ADDR_CMD2431MEM_ADDR_CMD2531MEM_ADDR_CMD2631MEM_ADDR_CMD2731MEM_ADDR_CMD2831MEM_ADDR_CMD2931MEM_ADDR_CMD3031MEM_ADDR_CMD3131
MEM_DMA032MEM_DMA132MEM_DMA232MEM_DMA332
MEM_DQA032MEM_DQA132MEM_DQA232MEM_DQA332MEM_DQA432MEM_DQA532MEM_DQA632MEM_DQA732MEM_DQA832MEM_DQA932
MEM_DQA1032MEM_DQA1132MEM_DQA1232MEM_DQA1332MEM_DQA1432MEM_DQA1532MEM_DQA1632MEM_DQA1732MEM_DQA1832MEM_DQA1932MEM_DQA2032MEM_DQA2132MEM_DQA2232MEM_DQA2332MEM_DQA2432MEM_DQA2532MEM_DQA2632MEM_DQA2732MEM_DQA2832MEM_DQA2932MEM_DQA3032MEM_DQA3132MEM_DQA3232MEM_DQA3332
MEM_DQSA_P032MEM_DQSA_N032MEM_DQSA_P132MEM_DQSA_N132MEM_DQSA_P232MEM_DQSA_N232MEM_DQSA_P332MEM_DQSA_N332
MEM_QKA_P032MEM_QKA_P132
IO_2V5 36,68
IO_3V3 69
HILO_1V30_SETn63
HILOQ_1V30_SETn64
HILO_VDDQ
HILO_VDD
HILO_VDD
HILO_VDDQ
IO_2V5
IO_3V3
HILO_VDDQ
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B34 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B34 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B34 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C531
1uF
HiLo EMI - POWER
VDD = 1.1(DEFAULT)
VDDQ = 1.1(DEFAULT))
VEXT = 2.5V
J27B
HLS-180324-B-12
VDDC7
VDDC9
VDDC11
VDDC13
VDDD6
VDDD8
VDDD10
VDDD12
VDDD14
VDDE7
VDDE9
VDDE11
VDDE13
VDDF6
VDDF8
VDDF10
VDDQF12
VDDQF14
VDDQG7
VDDQG9
VDDQG11
VDDQG13
VDDQH6
VDDQH8
VDDQH10
VDDQH12
VEXTL11
VEXTL13
VEXTM8
VEXTM10
VEXTM12
VEXTM14
VEXTN7
VEXTN9
VEXTN11
VEXTN13
VEXTP8
VEXTP10
VEXTP12
VEXTP14
2.5V/3.3V (VTT)J7
2.5V/3.3V (VTT)J9
2.5V/3.3V (VTT)K6
2.5V/3.3V (VTT)K8
2.5V/3.3V (VTT)L7
2.5V/3.3V (VTT)L9
VREFH14
2.5V/3.3V (VTT)J11
VREFJ13
2.5V/3.3V (VTT)K10
2.5V/3.3V (VTT)K12
VREFK14
VDD_1.2V_SETG15
VDD_1.25V_SETD5
VDD_1.35V_SETJ15
VDD_1.5V_SETL15
VDD_1.8V_SETN16
VDDQ_1.8V_SETR11
VDDQ_1.35V_SETR14
VDDQ_1.25V_SETF5 VDDQ_1.2V_SET
P16
VDDQ_1.5V_SETR12
VDDQ_1.1V_SETN15
VDD_1.30V_SETE15
VDDQ_1.30V_SETR15
HiLo EMI - GNDJ27C
HLS-180324-B-12
GNDA1
GNDA5
GNDA9
GNDA13
GNDA17
GNDB3
GNDB7
GNDB11
GNDB15
GNDC1
GNDC5
GNDC6
GNDC8
GNDC10
GNDC12
GNDC14
GNDC17
GNDD3
GNDD7
GNDD9
GNDD11
GNDD13
GNDD15
GNDE1
GNDE5
GNDE6
GNDE8
GNDE10
GNDE12
GNDE14
GNDE17
GNDF3
GNDF7
GNDF9
GNDF11
GNDF13
GNDF15
GNDG1
GNDG5
GNDG6
GNDG8
GNDG10
GNDG12
GNDG14
GNDG17
GNDH3
GNDH7
GNDH9
GNDH11
GNDH13
GNDH15
GNDJ1
GNDJ5
GNDJ6
GNDJ8
GNDJ10
GNDJ12
GNDJ14
GNDJ17
GNDK3
GNDK7
GNDK9
GNDK11
GNDK13
GNDK15
GNDL1
GNDL5
GNDL8
GNDL10
GNDL12
GNDL14
GNDL17
GNDM3
GNDM7
GNDM9
GNDM11
GNDM13
GNDM15
GNDN1
GNDN5
GNDN8
GNDN10
GNDN12
GNDN14
GNDN17
GNDP3
GNDP6
GNDP7
GNDP9
GNDP11
GNDP13
GNDP15
GNDR1
GNDR5
GNDR9
GNDR10
GNDR13
GNDR17
GNDT3
GNDT7
GNDT11
GNDT15
GNDU1
GNDU5
GNDU9
GNDU13
GNDU17
GNDV3
GNDV7
GNDV11
GNDV15
C639
10uF
HiLo EMI - EMI SIGNALSJ27A
HLS-180324-B-12
MEM_CLK_PV1
MEM_CLK_NV2
MEM_ADDR_CMD0F1
MEM_ADDR_CMD1H1
MEM_ADDR_CMD2F2
MEM_ADDR_CMD3G2
MEM_ADDR_CMD4H2
MEM_ADDR_CMD5J2
MEM_ADDR_CMD6K2
MEM_ADDR_CMD7G3
MEM_ADDR_CMD8J3
MEM_ADDR_CMD9L3
MEM_ADDR_CMD10E4
MEM_ADDR_CMD11F4
MEM_ADDR_CMD12G4
MEM_ADDR_CMD13H4
MEM_ADDR_CMD14J4
MEM_ADDR_CMD15K4
MEM_ADDR_CMD16M1
MEM_ADDR_CMD17M2
MEM_ADDR_CMD18N2
MEM_ADDR_CMD19L4
MEM_ADDR_CMD20P5
MEM_ADDR_CMD21M5
MEM_ADDR_CMD22P1
MEM_ADDR_CMD23R4
MEM_ADDR_CMD24M4
MEM_ADDR_CMD25R3
MEM_ADDR_CMD26L2
MEM_ADDR_CMD27K1
MEM_ADDR_CMD28P2
MEM_ADDR_CMD29N4
MEM_ADDR_CMD30P4
MEM_DQS_ADDR_CMD_PV4
MEM_DQS_ADDR_CMD_NV5
MEM_DQ_ADDR_CMD0R6
MEM_DQ_ADDR_CMD1T1
MEM_DQ_ADDR_CMD2R2
MEM_DQ_ADDR_CMD3T2
MEM_DQ_ADDR_CMD4U2
MEM_DQ_ADDR_CMD5U3
MEM_DQ_ADDR_CMD6T4
MEM_DQ_ADDR_CMD7U4
MEM_DQ_ADDR_CMD8T5
MEM_DMA0B10
MEM_DMA1C4
MEM_DMA2B17
MEM_DMA3F17
MEM_DQA0A4
MEM_DQA1B4
MEM_DQA2B5
MEM_DQA3B6
MEM_DQA4A8
MEM_DQA5B8
MEM_DQA6B9
MEM_DQA7A10
MEM_DQA8B1
MEM_DQA9B2
MEM_DQA10C2
MEM_DQA11C3
MEM_DQA12E3
MEM_DQA13D4
MEM_DQA14D1
MEM_DQA15D2
MEM_DQA16A12
MEM_DQA17B12
MEM_DQA18B13
MEM_DQA19B14
MEM_DQA20C15
MEM_DQA21A16
MEM_DQA22B16
MEM_DQA23A18
MEM_DQA24C16
MEM_DQA25D16
MEM_DQA26E16
MEM_DQA27F16
MEM_DQA28D17
MEM_DQA29C18
MEM_DQA30D18
MEM_DQA31E18
MEM_DQA32E2
MEM_DQA33G16
MEM_DQSA_P0A6
MEM_DQSA_P1A2
MEM_DQSA_P2A14
MEM_DQSA_P3F18
MEM_DQSA_N0A7
MEM_DQSA_N1A3
MEM_DQSA_N2A15
MEM_DQSA_N3G18
MEM_QKA_N0A11
MEM_DQSB_N0J18
MEM_DQSB_N1V18
MEM_DQSB_N2V17
MEM_DQSB_N3V9
MEM_DQSB_P0H18
MEM_DQSB_P1U18
MEM_DQSB_P2V16
MEM_DQSB_P3V8
MEM_QKB_N0M18
MEM_DMB0M16
MEM_DMB1U16
MEM_DMB2U11
MEM_DMB3U6
MEM_DQB0H16
MEM_DQB1J16
MEM_DQB2K16
MEM_DQB3L16
MEM_DQB4H17
MEM_DQB5K17
MEM_DQB6K18
MEM_DQB7L18
MEM_DQB8M17
MEM_DQB9N18
MEM_DQB10P17
MEM_DQB11P18
MEM_DQB12R18
MEM_DQB13T16
MEM_DQB14T17
MEM_DQB15T18
MEM_DQB16U15
MEM_DQB17T14
MEM_DQB18U14
MEM_DQB19V14
MEM_DQB20T13
MEM_DQB21T12
MEM_DQB22U12
MEM_DQB23V12
MEM_DQB24T10
MEM_DQB25U10
MEM_DQB26V10
MEM_DQB27T9
MEM_DQB28T8
MEM_DQB29U8
MEM_DQB30U7
MEM_DQB31V6
MEM_DQB32R16
MEM_DQB33T6
CONFIG0L6
CONFIG1M6
RFU2H5
RFU3K5
RFU4N6
RFU5R7
MEM_ADDR_CMD31N3
MEM_QKA_N1B18
MEM_QKB_N1V13
RFU6R8
C600
10uF
C640
0.1uF
C1557
0.1uF
C532
1uF
R5494 240
R5495 240
C601
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
5M2210 System Controller
VCCINT 3V3 VCCIO 2V5 VCCIO1V8 VCCIO
UART_TX
UART_RX
MDCLKR
EN0
EN7EN6EN5
EN1
EN3EN4
EN2
EN8
1V8 23,38,39,55
3V3 37,38,44,53,54,55,65,69,71
2V5 38,68,71
A10_EN 55A10_0V9_EN 56
A10_0V95_EN 58,59A10_1V0_EN 60A10_1V8_EN 68
IO_EN 62,63,64,68,69PCIE_auxEN 69
PCIE_EN 49,69FMCA_AUXEN 65FMCA_EN 49,65,66FMCB_AUXEN 65FMCB_EN 49,65,67
LTWDI_RESETN 73
LTCNTRL0 73LTCNTRL1 73
IO3V3_Discharge 70PLL1V8_discharge 70
HILOHPS_VDDPGood62HILO_VDDPGood63
HILO_VDDQPGood64FMCAVADJPGood66FMCBVADJPGood6710V_Fail_n5510V_good55
EXT_INTn42
M5A_JTAG_TCK 38M5A_JTAG_TDI 38
M5A_JTAG_TMS 38M5A_JTAG_TDO 38
SFPA_LOS13SFPA_TXFAULT13
SFPB_TXDISABLE14SFPB_RATESEL014SFPB_RATESEL114
SFPB_LOS14SFPB_TXFAULT14
USB_RESET 25
SPIM1_CLK20
SPIM1_MISO20
NCONFIG 21DCLK 21
PS_D0 27
PCIE_PERSTn 10
CRCERROR 27DEV_CLRN 27
CLK_50M_MAX39
ENET_HPS_RESETn 22
RESET_HPS_UARTA_N 26
HPS_NRST 21HPS_NPOR 21
BF_Presentn23
BQSPI_RESETN 23
File_Presentn23
FAM2CPgood17
A10_PMBUSDIS_N45
A10_2L_SDA20,45A10_2L_SCL20,45
PMbus_ALTERTn 45,51,56,73
1V0_Pgood60
HPS_Pgood59
3V3_Pgood512V5_Pgood531V8_Pgood54
P0V95Pgood58
P0V9Pgood56
5V0_Pgood50
LTFAUL073LTPWRGD73
LMK_RESET 41
SPIM1_MOSI20SPIM1_SS0_N20SPIM1_SS1_N20
FAC2MPgood17FBC2MPgood18
Logic_RESETn42
PGM_LED042
PGM_LED1 42
PGM_LED242
FAN_EN27
PGM_SEL42
PGM_CONFIG 42SECURITY_MODE 42
MSEL021MSEL121MSEL221
NSTATUS 21CONF_DONE 21
A10I2CEN20
TSENSE_ALERTn45OVERTEMPn45
CLK_50M_FPGA27
FILE_RESETN 23
MAX_ERROR42MAX_LOAD42
MAX_CONF_DONE42
FACTORY_LOAD42
SFPA_MOD0_PRSNTn13SFPB_MOD0_PRSNTn14
ENET_HPS_INTn22
CVP_CONFDONE 27
SFPA_TXDISABLE13SFPA_RATESEL013SFPA_RATESEL113
USER_DIPSW_HPS042USER_DIPSW_HPS142
USER_DIPSW_FPGA042USER_DIPSW_FPGA142USER_DIPSW_FPGA242USER_DIPSW_FPGA342
MFD023MFD123MFD223MFD323
MFCLK23MFCSN23
USER_PB_HPS0 42USER_PB_HPS1 42USER_PB_HPS2 42
USER_PB_FPGA0 42USER_PB_FPGA1 42USER_PB_FPGA2 42USER_PB_FPGA3 42
UART1_TX 33UART1_RX 33
FPGA_IO4 27FPGA_IO5 27
MAXVtoMAXV036MAXVtoMAXV136MAXVtoMAXV236
MAXVtoMAXV3 36
USER_LED_HPS142USER_LED_HPS042
USER_LED_FPGA042USER_LED_FPGA142USER_LED_FPGA242USER_LED_FPGA342
MAX2toMAXV10 37MAX2toMAXV11 37MAX2toMAXV12 37
MAX2toMAXV6 37MAX2toMAXV7 37MAX2toMAXV8 37MAX2toMAXV9 37
MAX2toMAXV13 37
HPS_cold_RESETn 44HPS_warm_RESETn 44HPS_warm_RESET1n 37
MAX2toMAXV0 37MAX2toMAXV1 37MAX2toMAXV2 37MAX2toMAXV3 37MAX2toMAXV4 37MAX2toMAXV5 37
PCIE_PRSNT2n10
MAXV_USB_CLK37
A10SH_GPIO020A10SH_GPIO120A10SH_GPIO220A10SH_GPIO320
PCIE1V8_PERSTn 27PCIE1V8_PERST1n 27
FAPRSNT_N 17FBPRSNT_N 18
DC_POWER_CTRL 42I2C_flag 42
UARTA_RX26UARTA_TX26
MAXVtoMAXV11 36
MAXVtoMAXV8 36MAXVtoMAXV9 36
MAXVtoMAXV10 36
MAXVtoMAXV13 36MAXVtoMAXV12 36
HPSUARTA_TX20HPSUARTA_RX20
MAXVtoMAXV7 36
MAXVtoMAXV4 36MAXVtoMAXV5 36MAXVtoMAXV6 36
USB_VFlagn 25
USER_DIPSW_HPS242
USER_LED_HPS242
dedicated_TX 23dedicated_RX 23
dedicated_OE 23
A10PMBUSEN27
MAX_IO_CLK36USER_DIPSW_HPS342 USER_PB_HPS3 42
USER_LED_HPS342
ENET_DISABLE_N 27RESERVE1 21
1V8
1V8 2V51V8
1V8
1V8
3V3
2V5
2V5
3V3 MV_3V3
MV_3V3
MV_3V3
MV_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B35 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B35 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B35 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C362
0.1uF
C388
0.1uF
C356
0.1uF
C15591uF
R479 49.9
MAX VBANK2
U16B
5M2210ZF256
DIFFIO_T9PB8
DIFFIO_T9NA8
DIFFIO_T8PD8
DIFFIO_T8NA7
DIFFIO_T7PC8
DIFFIO_T7NB7
DIFFIO_T6PB6
DIFFIO_T6NE7
DIFFIO_T5PA5
DIFFIO_T5ND7
DIFFIO_T4PE6
DIFFIO_T4NB5
DIFFIO_T3PB4
DIFFIO_T3ND6
DIFFIO_T2PC5
DIFFIO_T2NC4
DIFFIO_T1PD4
DIFFIO_T1NB1
DIFFIO_T18PC13
DIFFIO_T18NB16
DIFFIO_T17PD12
DIFFIO_T17NB14
DIFFIO_T16PC11
DIFFIO_T16NB13
DIFFIO_T15PE11
DIFFIO_T15NB12
DIFFIO_T14PB11
DIFFIO_T14NA12
DIFFIO_T13PE10
DIFFIO_T13NA11
DIFFIO_T12PA10
DIFFIO_T12NC9
DIFFIO_T11PB9
DIFFIO_T11ND9
DIFFIO_T10PA9
DIFFIO_T10NE9
IOB2_6A13
IOB2_7A15
IOB2_8A2
IOB2_9A4
IOB2_10A6
IOB2_11B10
IOB2_12B3
IOB2_13C10
IOB2_14C12
IOB2_15C6
IOB2_16C7
IOB2_17D10
IOB2_18D11
IOB2_19D5
IOB2_20E8
C383
0.1uF
C398
0.1uF
C389
0.1uF
R482 49.9
Q45DMG2305UX
S D
G
MAX VBANK3
U16C
5M2210ZF256
IOB3/CLK2J12
IOB3/CLK3H12
DIFFIO_R9PG12
DIFFIO_R9NG16
DIFFIO_R8PG13
DIFFIO_R8NG15
DIFFIO_R7PG14
DIFFIO_R7NF16
DIFFIO_R6PE16
DIFFIO_R6NF15
DIFFIO_R5PF13
DIFFIO_R5NE15
DIFFIO_R4PF14
DIFFIO_R4ND16
DIFFIO_R3PE12
DIFFIO_R3ND15
DIFFIO_R2PC15
DIFFIO_R2NE13
DIFFIO_R22PP15
DIFFIO_R22NP14
DIFFIO_R21PN15
DIFFIO_R21NN14
DIFFIO_R20PN16
DIFFIO_R20NM13
DIFFIO_R1PE14
DIFFIO_R1NC14
DIFFIO_R19PM15
DIFFIO_R19NL14
DIFFIO_R18PM16
DIFFIO_R18NL13
DIFFIO_R17PL15
DIFFIO_R17NL12
DIFFIO_R16PL16
DIFFIO_R16NL11
DIFFIO_R15PK15
DIFFIO_R15NK14
DIFFIO_R14PK16
DIFFIO_R14NK13
DIFFIO_R13PJ14
DIFFIO_R13NJ15
DIFFIO_R12PJ13
DIFFIO_R12NJ16
DIFFIO_R11PH13
DIFFIO_R11NH16
DIFFIO_R10PH14
DIFFIO_R10NH15
IOB3_21D13
IOB3_22D14
IOB3_23F11
IOB3_24F12
IOB3_25K12
IOB3_26M14
IOB3_27N13
R492 10KMAX VBANK4
U16D
5M2210ZF256
DIFFIO_B13N/DEV_CLRnM9
DIFFIO_B13P/DEV_OEM8
DIFFIO_B9PP8
DIFFIO_B9NT7
DIFFIO_B8PM7
DIFFIO_B8NR7
DIFFIO_B7PR6
DIFFIO_B7NN7
DIFFIO_B6PT5
DIFFIO_B6NP7
DIFFIO_B5PR5
DIFFIO_B5NM6
DIFFIO_B4PP6
DIFFIO_B4NN6
DIFFIO_B3PR3
DIFFIO_B3NN5
DIFFIO_B2PT2
DIFFIO_B2NP5
DIFFIO_B22PR16
DIFFIO_B22NP13
DIFFIO_B21PP12
DIFFIO_B21NT15
DIFFIO_B20PN12
DIFFIO_B20NR14
DIFFIO_B1PR1
DIFFIO_B1NP4
DIFFIO_B19PT13
DIFFIO_B19NR13
DIFFIO_B18PR12
DIFFIO_B18NP11
DIFFIO_B17PT12
DIFFIO_B17NN11
DIFFIO_B16PP10
DIFFIO_B16NR11
DIFFIO_B15PN10
DIFFIO_B15NT11
DIFFIO_B14PM10
DIFFIO_B14NR10
DIFFIO_B12PR9
DIFFIO_B12NP9
DIFFIO_B11PT8
DIFFIO_B11NT9
DIFFIO_B10PN8
DIFFIO_B10NR8 IOB4_28
M11
IOB4_29M12
IOB4_30N9
IOB4_31R4
IOB4_32T10
IOB4_33T4
C417
0.1uF
R480 49.9
C386
0.1uF
C387
0.1uF
R485 49.9
R481 49.9R453 49.9
C438
0.1uF
R446 10
R483 49.9
C401
0.1uF
C355
0.1uF
C402
0.1uF
C399
0.1uF
C384
0.1uF
R486 49.9
R487 49.9
C385
0.1uF
C412
0.1uF
C363
0.1uF
MAX VBANK1
U16A
5M2210ZF256
DIFFIO_L19PN1
IOB1/CLK0H5
IOB1/CLK1J5
DIFFIO_L9PG1
DIFFIO_L9NG4
DIFFIO_L8PG2
DIFFIO_L8NG3
DIFFIO_L7PF1
DIFFIO_L7NF6
DIFFIO_L6PF4
DIFFIO_L6NF2
DIFFIO_L5PF3
DIFFIO_L5NE1
DIFFIO_L4PD1
DIFFIO_L4NE5
DIFFIO_L3PD2
DIFFIO_L3NE4
DIFFIO_L2PC3
DIFFIO_L2NE3
DIFFIO_L21PN3
DIFFIO_L21NP2
DIFFIO_L20PN2
DIFFIO_L20NM3
DIFFIO_L1PD3
DIFFIO_L1NC2
DIFFIO_L19NM4
DIFFIO_L18PL4
DIFFIO_L18NL3
DIFFIO_L17PM1
DIFFIO_L17NM2
DIFFIO_L16PL2
DIFFIO_L16NK3
DIFFIO_L15PK5
DIFFIO_L15NL1
DIFFIO_L14PJ3
DIFFIO_L14NK2
DIFFIO_L13PJ4
DIFFIO_L13NK1
DIFFIO_L12PH4
DIFFIO_L12NJ2
DIFFIO_L11PH3
DIFFIO_L11NJ1
DIFFIO_L10PH2
DIFFIO_L10NG5
IOB1_1E2
IOB1_2F5
IOB1_3H1
IOB1_4K4
IOB1_5L5
TMSN4TDOM5TDIL6TCKP3
C400
0.1uF
R484 10K
C411
0.1uF
R549910
MAX VPower
U16E
5M2210ZF256
GNDINTF7
GNDINTG6
GNDINTH7
GNDINTH9
GNDIOA1
GNDIOA16
GNDIOB15
GNDIOB2
GNDIOG10
GNDIOG7
GNDIOG8
GNDIOG9
GNDIOK10
GNDIOK7
GNDIOK8
GNDIOK9
GNDIOR15
GNDIOR2
GNDIOT1
GNDIOT16
VCCINTH8VCCINTH10VCCINTG11VCCINTF10
VCCIO1C1
VCCIO1H6
VCCIO1J6
VCCIO1P1
VCCIO2A14
VCCIO2A3
VCCIO2F8
VCCIO2F9
VCCIO3C16
VCCIO3H11
VCCIO3J11
VCCIO3P16
VCCIO4L8
VCCIO4L9
VCCIO4T14
VCCIO4T3
GNDINTJ10
VCCINTJ7
VCCINTL7
GNDINTJ8
GNDINTK11
VCCINTK6VCCINTJ9
GNDINTL10
GNDIOT6
R54984.7K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGAIO for DP_IO, SDI_IO and FMC_3V3IO
VCCINT 3V3 VCCIO 2V5 VCCIO1V8 VCCIO
IO_1V815,20,21,22,23,25,27,39,40,42,74,77
IO_2V511,12,16,22,24,27,34,39,41,45
M5B_JTAG_TCK 38M5B_JTAG_TDI 38
M5B_JTAG_TMS 38M5B_JTAG_TDO38
FBLAP29 18FBLAN29 18
FBLAP31 18FBLAN31 18FBLAP32 18FBLAN32 18
FBLAP30 18FBLAN30 18
FBLAP33 18FBLAN33 18
FBLAP28 18FBLAN28 18
FBHBP1818FBHBN1818FBHBP1918FBHBN1918FBHBP2018FBHBN2018FBHBP2118FBHBN2118
FAHBP1817FAHBN1817FAHBP1917FAHBN1917FAHBP2017FAHBN2017FAHBP2117FAHBN2117
FPGAIO2_N 29FPGAIO2_P 29
FPGAIO3_N 29FPGAIO3_P 29
FPGAIO_N 27FPGAIO_P 27
FPGAIO1_N 27FPGAIO1_P 27
FPGAIO6_N 29FPGAIO6_P 29
FPGAIO7_N 29FPGAIO7_P 29
FPGAIO4_N 29FPGAIO4_P 29
FPGAIO5_N 29FPGAIO5_P 29
SDI_SPI_M1SO16SDI_SPI_CLK16
SDI_SPI_MOSI16SDI_SPI_CS016
SDI_MF3_MOSI16SDI_MF2_MUTE_SCLK16
SDI_xCS_CS16
SI516_FS39
SDI_MF1_SLEEP_MISO16
SDI_TX_SD_HDn16SDI_CLK148_DOWN39SDI_CLK148_UP39
SDI_MF0_BYPASS_present16SDI_MF4_status16SDI_XHD_RATE16
DP_AUX_DE 15DP_AUX_D 15
DP_AUX_R 15DP_AUX_REn 15
DP_CONFIG1 15DP_CONFIG2 15
PCIE1V8_PERSTn 27PCIE1V8_PERST1n 27
FAPRSNT_N 17 FBPRSNT_N 18
PCIE_WAKE_N 10PCIE_PRSNT2n 10
DP_OCn 15
FACLKDIR 17
DP_HOT_PLUG 15
DP_ON 15
FMCAVADJ66FAM2CVIO
17
FMCBVADJ67
FBM2CVIO 18
MAXVtoMAXV035
MAXVtoMAXV1 35MAXVtoMAXV2 35
MAXVtoMAXV3 35
USB_MAXV_D325
USB_MAXV_D025USB_MAXV_D125USB_MAXV_D225
USB_MAXV_D425
USB_MAXV_RESET25USB_MAXV_WR25USB_MAXV_RDn25
USB_MAXV_RXFn25USB_MAXV_TXEn25
USB_MAXV_D525USB_MAXV_D625USB_MAXV_D725
SPI_SDIO 41SPI_CLK 41
SPI_CSn 41
LMK_RESET 41
MAXVtoMAXV11 35
MAXVtoMAXV8 35MAXVtoMAXV9 35
MAXVtoMAXV10 35
MAXVtoMAXV12 35MAXVtoMAXV13 35
MAXVtoMAXV7 35MAXVtoMAXV6 35
MAXVtoMAXV4 35MAXVtoMAXV5 35
FPGAIO10_N27FPGAIO10_P27FPGAIO11_N27FPGAIO11_P27FPGAIO12_N27FPGAIO12_P27
FPGAIO9_N29FPGAIO9_P29
FPGAIO8_N 29FPGAIO8_P 29
FAHBP1117FAHBN1117FAHBP1217FAHBN1217
FAHBP1417FAHBN1417FAHBP1517FAHBN1517
FAHBP1617FAHBN1617
FAHBP1717FAHBN1717
FMCB_DC_3V3 72
ENETA_RESETn11
ENETB_RESETn12
ENETA_INTn11
ENETB_INTn12
MAX_IO_CLK35
IO_1V8
IO_2V5
IO_1V8
IO_1V8
IO_2V5
Vbank3
Vbank3
Vbank4
Vbank4
IO_1V8Vbank3 Vbank4
IO_1V8 IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B36 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B36 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B36 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C490
0.1uF
C433
0.1uF
C443
0.1uF
C445
0.1uF
C403
0.1uF
C404
0.1uF
C430
0.1uF
MAX VBANK2
U21B
5M2210ZF256
DIFFIO_T9PB8
DIFFIO_T9NA8
DIFFIO_T8PD8
DIFFIO_T8NA7
DIFFIO_T7PC8
DIFFIO_T7NB7
DIFFIO_T6PB6
DIFFIO_T6NE7
DIFFIO_T5PA5
DIFFIO_T5ND7
DIFFIO_T4PE6
DIFFIO_T4NB5
DIFFIO_T3PB4
DIFFIO_T3ND6
DIFFIO_T2PC5
DIFFIO_T2NC4
DIFFIO_T1PD4
DIFFIO_T1NB1
DIFFIO_T18PC13
DIFFIO_T18NB16
DIFFIO_T17PD12
DIFFIO_T17NB14
DIFFIO_T16PC11
DIFFIO_T16NB13
DIFFIO_T15PE11
DIFFIO_T15NB12
DIFFIO_T14PB11
DIFFIO_T14NA12
DIFFIO_T13PE10
DIFFIO_T13NA11
DIFFIO_T12PA10
DIFFIO_T12NC9
DIFFIO_T11PB9
DIFFIO_T11ND9
DIFFIO_T10PA9
DIFFIO_T10NE9
IOB2_6A13
IOB2_7A15
IOB2_8A2
IOB2_9A4
IOB2_10A6
IOB2_11B10
IOB2_12B3
IOB2_13C10
IOB2_14C12
IOB2_15C6
IOB2_16C7
IOB2_17D10
IOB2_18D11
IOB2_19D5
IOB2_20E8
C420
0.1uF
R540
DNI
C441
0.1uF
C431
0.1uF
MAX VBANK1
U21A
5M2210ZF256
DIFFIO_L19PN1
IOB1/CLK0H5
IOB1/CLK1J5
DIFFIO_L9PG1
DIFFIO_L9NG4
DIFFIO_L8PG2
DIFFIO_L8NG3
DIFFIO_L7PF1
DIFFIO_L7NF6
DIFFIO_L6PF4
DIFFIO_L6NF2
DIFFIO_L5PF3
DIFFIO_L5NE1
DIFFIO_L4PD1
DIFFIO_L4NE5
DIFFIO_L3PD2
DIFFIO_L3NE4
DIFFIO_L2PC3
DIFFIO_L2NE3
DIFFIO_L21PN3
DIFFIO_L21NP2
DIFFIO_L20PN2
DIFFIO_L20NM3
DIFFIO_L1PD3
DIFFIO_L1NC2
DIFFIO_L19NM4
DIFFIO_L18PL4
DIFFIO_L18NL3
DIFFIO_L17PM1
DIFFIO_L17NM2
DIFFIO_L16PL2
DIFFIO_L16NK3
DIFFIO_L15PK5
DIFFIO_L15NL1
DIFFIO_L14PJ3
DIFFIO_L14NK2
DIFFIO_L13PJ4
DIFFIO_L13NK1
DIFFIO_L12PH4
DIFFIO_L12NJ2
DIFFIO_L11PH3
DIFFIO_L11NJ1
DIFFIO_L10PH2
DIFFIO_L10NG5
IOB1_1E2
IOB1_2F5
IOB1_3H1
IOB1_4K4
IOB1_5L5
TMSN4TDOM5TDIL6TCKP3
R522
0.001
C444
0.1uF
R5521
0.001
MAX VPower
U21E
5M2210ZF256
GNDINTF7
GNDINTG6
GNDINTH7
GNDINTH9
GNDIOA1
GNDIOA16
GNDIOB15
GNDIOB2
GNDIOG10
GNDIOG7
GNDIOG8
GNDIOG9
GNDIOK10
GNDIOK7
GNDIOK8
GNDIOK9
GNDIOR15
GNDIOR2
GNDIOT1
GNDIOT16
VCCINTH8VCCINTH10VCCINTG11VCCINTF10
VCCIO1C1
VCCIO1H6
VCCIO1J6
VCCIO1P1
VCCIO2A14
VCCIO2A3
VCCIO2F8
VCCIO2F9
VCCIO3C16
VCCIO3H11
VCCIO3J11
VCCIO3P16
VCCIO4L8
VCCIO4L9
VCCIO4T14
VCCIO4T3
GNDINTJ10
VCCINTJ7
VCCINTL7
GNDINTJ8
GNDINTK11
VCCINTK6VCCINTJ9
GNDINTL10
GNDIOT6
C464
0.1uF
C440
0.1uF
R55220
R444
DNI
MAX VBANK3
U21C
5M2210ZF256
IOB3/CLK2J12
IOB3/CLK3H12
DIFFIO_R9PG12
DIFFIO_R9NG16
DIFFIO_R8PG13
DIFFIO_R8NG15
DIFFIO_R7PG14
DIFFIO_R7NF16
DIFFIO_R6PE16
DIFFIO_R6NF15
DIFFIO_R5PF13
DIFFIO_R5NE15
DIFFIO_R4PF14
DIFFIO_R4ND16
DIFFIO_R3PE12
DIFFIO_R3ND15
DIFFIO_R2PC15
DIFFIO_R2NE13
DIFFIO_R22PP15
DIFFIO_R22NP14
DIFFIO_R21PN15
DIFFIO_R21NN14
DIFFIO_R20PN16
DIFFIO_R20NM13
DIFFIO_R1PE14
DIFFIO_R1NC14
DIFFIO_R19PM15
DIFFIO_R19NL14
DIFFIO_R18PM16
DIFFIO_R18NL13
DIFFIO_R17PL15
DIFFIO_R17NL12
DIFFIO_R16PL16
DIFFIO_R16NL11
DIFFIO_R15PK15
DIFFIO_R15NK14
DIFFIO_R14PK16
DIFFIO_R14NK13
DIFFIO_R13PJ14
DIFFIO_R13NJ15
DIFFIO_R12PJ13
DIFFIO_R12NJ16
DIFFIO_R11PH13
DIFFIO_R11NH16
DIFFIO_R10PH14
DIFFIO_R10NH15
IOB3_21D13
IOB3_22D14
IOB3_23F11
IOB3_24F12
IOB3_25K12
IOB3_26M14
IOB3_27N13
R443
DNI
C465
0.1uF
MAX VBANK4
U21D
5M2210ZF256
DIFFIO_B13N/DEV_CLRnM9
DIFFIO_B13P/DEV_OEM8
DIFFIO_B9PP8
DIFFIO_B9NT7
DIFFIO_B8PM7
DIFFIO_B8NR7
DIFFIO_B7PR6
DIFFIO_B7NN7
DIFFIO_B6PT5
DIFFIO_B6NP7
DIFFIO_B5PR5
DIFFIO_B5NM6
DIFFIO_B4PP6
DIFFIO_B4NN6
DIFFIO_B3PR3
DIFFIO_B3NN5
DIFFIO_B2PT2
DIFFIO_B2NP5
DIFFIO_B22PR16
DIFFIO_B22NP13
DIFFIO_B21PP12
DIFFIO_B21NT15
DIFFIO_B20PN12
DIFFIO_B20NR14
DIFFIO_B1PR1
DIFFIO_B1NP4
DIFFIO_B19PT13
DIFFIO_B19NR13
DIFFIO_B18PR12
DIFFIO_B18NP11
DIFFIO_B17PT12
DIFFIO_B17NN11
DIFFIO_B16PP10
DIFFIO_B16NR11
DIFFIO_B15PN10
DIFFIO_B15NT11
DIFFIO_B14PM10
DIFFIO_B14NR10
DIFFIO_B12PR9
DIFFIO_B12NP9
DIFFIO_B11PT8
DIFFIO_B11NT9
DIFFIO_B10PN8
DIFFIO_B10NR8 IOB4_28
M11
IOB4_29M12
IOB4_30N9
IOB4_31R4
IOB4_32T10
IOB4_33T4
C415
0.1uF
C478
0.1uF
C442
0.1uF
C432
0.1uF
C421
0.1uF
C429
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
On-Board USB Blaster II - Part 1
PLACE NEAR CY7C68013A
IFCLK = 48MHz
FX2_D_NFX2_D_P
FX2_WAKEUPVBUS_5V
VBUS_5V
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
24M_XTALIN24M_XTALOUT
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_CLK
FX2_RESETn
FX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SDAFX2_PD2FX2_PD0C_USB_MAX_TCK
C_USB_MAX_TDIFX2_PD3C_USB_MAX_TDOFX2_PD1C_USB_MAX_TMS
FX2_PA0
FX2_PA0
FX2_PA2
FX2_CLK
FX2_PA1FX2_PB1
FX2_PA4
FX2_PB2
FX2_PA6FX2_PB5
FX2_SLWRn
FX2_PD5
FX2_PA5
FX2_SCL
FX2_PD6
FX2_PB7
FX2_PD4
FX2_PB4
FX2_FLAGC
FX2_PA3
FX2_PB0
FX2_SLRDn
FX2_PB6
FX2_PD7
FX2_PB3
FX2_FLAGA
FX2_RESETnMAX_SDA
FX2_PA7
MAX_SDAFX2_PD[0:7]
FX2_PB[0:7]
FX2_PA[0:7]
FX2_SCL
FX2_FLAGB
RJT
AG
_TC
KR
JTA
G_T
DI
RJT
AG
_TD
OR
JTA
G_T
MS
1V8 35,543V3 35,42,51
PCIE_TCK 10PCIE_TMS 10
PCIE_TDI 10PCIE_TDO 10
PCIE_TRSTN 10
FATRST 17
FATMS 17
FATDO 17
FATDI 17FATCK 17
FBTRST 18
FBTMS 18
FBTDO18
FBTDI 18FBTCK 18
HPS_warm_RESET1n35
EBLST_ENABLEN38
EBLST_JTAG_TCK 38
EBLST_JTAG_TDO 38EBLST_JTAG_TMS 38
EBLST_JTAG_TDI 38
MAX2toMAXV635MAX2toMAXV735MAX2toMAXV835MAX2toMAXV935
MAX2toMAXV1035MAX2toMAXV1135MAX2toMAXV1235MAX2toMAXV1335
MAX2toMAXV435MAX2toMAXV535
MAX2toMAXV135MAX2toMAXV235MAX2toMAXV335
MAX2toMAXV035
EBLST_PROC_RSTn38
EBLAST_RESERVE138EBLAST_RESERVE038
PCIE_PRSNT2n 10
MAXV_USB_CLK35
IO_1V8 15,20,21,22,23,25,27,39,40,42,74,77
USB_FPGA_CLK 27
1V83V3
3V3
3V33V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B37 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B37 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B37 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R467 DNI
C377
0.1uF
R476 0
R475 DNI
C396
0.1uF
R477 DNI
C368
0.1uF
C369
0.1uF
VBUSD-D+ID
J22MICRO_USB_CONN
12345
6789
C361
0.1uF
R474 DNI
C3474.7nF
R452 0
R438
20K
R93 10K
C408
0.1uF
C59
12pF
Y3
24.00MHz
1 3
24
MAX IIBANK4
U17D
EPM1270_M256FBGA
IOB4/DEV_CLRnY13
IOB4/DEV_OEW12
IOB4_1U13
IOB4_2U14
IOB4_3U15
IOB4_4U16
IOB4_5U4
IOB4_6U5
IOB4_7U6
IOB4_8U7
IOB4_9U8
IOB4_10V14
IOB4_11V15
IOB4_12V16
IOB4_13V17
IOB4_14V18
IOB4_15V4
IOB4_16V5
IOB4_17V6
IOB4_18V7
IOB4_20W11
IOB4_21W13
IOB4_22W14
IOB4_23W15
IOB4_24W16
IOB4_25W17
IOB4_26W18
IOB4_27W3
IOB4_28W4
IOB4_29W5
IOB4_30W6
IOB4_32W8
IOB4_33W9
IOB4_34Y1
IOB4_35Y10
IOB4_36Y11
IOB4_37Y12
IOB4_38Y14
IOB4_39Y15
IOB4_40Y16
IOB4_41Y17
IOB4_42Y18
IOB4_43Y19
IOB4_44Y2
IOB4_45Y3
IOB4_46Y4
IOB4_47Y5
IOB4_48Y6
IOB4_49Y7
IOB4_50Y8
IOB4_51Y9
IOB4_31W7
IOB4_19W10
R97100K
C60
12pF
MAX IIBANK1
U17A
EPM1270_M256FBGA
IOB1_21G4
IOB1_22H1
IOB1_23H2
IOB1/GCLK0K1
IOB1/GCLK1L1
IOB1_1B1
IOB1_2C1
IOB1_3C2
IOB1_4C3
IOB1_5C4
IOB1_6D1
IOB1_7D2
IOB1_8D3
IOB1_9D4
IOB1_10E1
IOB1_11E2
IOB1_12E3
IOB1_13E4
IOB1_14F1
IOB1_15F2
IOB1_16F3
IOB1_17F4
IOB1_18G1
IOB1_19G2
IOB1_20G3
IOB1_24H4
IOB1_25J1
IOB1_26J2
IOB1_27K2
IOB1_28L2
IOB1_29M1
IOB1_30M2
IOB1_31N1
IOB1_32N2
IOB1_33N4
IOB1_34P1
IOB1_35P2
IOB1_36P3
IOB1_37P4
IOB1_38R1
IOB1_39R2
IOB1_40R3
IOB1_41R4
IOB1_42T1
IOB1_43T2
IOB1_44T4
IOB1_45U1
IOB1_46U3
IOB1_47V1
TMST3TDOV2TDIU2TCKW2
IOB1_48V3
IOB1_49W1
R5500 10
R459 0
R428 0
C425 0.1uF
R4121M
C57
0.1uF
C360
0.1uF
U73
SN74LVC1G17
2 A 4Y
NC1
GND3
VCC5
R472 0
U18
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC3
DMINUS9
AGND6
VCC11
GND12
PD752
CLKOUT54
XTALOUT4
AVCC7
DPLUS8
AGND10
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND26
GND28
GND41
PB119
PB321PB220
VCC17
VCC27
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND53
VCC43
PA336
CTL130CTL029
PD045
RESET42
PA538
GND56
VCC55
PA235
PA033
CTL231
VCC32
EXPOSED_PAD57
R90 DNI
U53
TPD2EUSB30D-
2D+1
GND3
R468 0
U20
MAX811
GND1
RESET2
VCC4
MR3
C1563
0.1uF
R478 0
R434 0
R5460 2.00K
C407
0.1uF
R473 0R5459 2.00K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
On-Board USB Blaster II - Part 2
PLACE NEAR MAX II (U25)
USB Blaster Programming Header
(uses JTAG mode only)
Logic 0 = Device JTAG BypassLogic 1 = Device JTAG Enable
Direct USB D[7:0]
Direct USB_RDnDirect USB_WrnDirect USB_OEnDirect USB_RESETnDirect USB_EMPTYDirect USB_FULLDirect USB_SDADirect USB_SCL
MSTR2 MSTR1 MSTR0
ON ON ON
ON ON
ON
ON ON
ON
ON
ON
ON
OFF
OFF
OFF OFF
OFF
OFF OFF
OFF OFF
OFF OFF OFF ON-board UBII
Mode
BOOT
FMCA Master
FMCB Master
Reserved
FTRACE Master
GUI Test
SystemMAXV Progrm Mode
FMCB_BYPASSFMCA_BYPASSM5B_BYPASSA10_BYPASS
JTAG_TX
SC_RX
SC_TX
PCIE_BYPASSMSTR0MSTR1MSTR2
JTAG_RX
A10_JTAG_TDI 21A10_JTAG_TCK 21A10_JTAG_TMS 21A10_JTAG_TDO 21
M5A_JTAG_TCK35M5A_JTAG_TMS35
M5A_JTAG_TDI35
M5A_JTAG_TDO35
1V8 35,543V3 35,42,512V5 35,53
FAPRSNT_N 17
FBPRSNT_N 18
EBLST_ENABLEN37
EBLST_JTAG_TCK37
EBLST_JTAG_TMS37
EBLST_JTAG_TDI37
EBLST_JTAG_TDO37
FTRACE_D11 23,27
FTRACE_D8 23,27
FTRACE_D10 23,27FTRACE_D9 23,27
FTRACE_D13 23,27FTRACE_D12 23,27
FTRACE_D15 23,27FTRACE_D14 23,27
FTRACE_JTAG_TRSTn23FTRACE_JTAG_TCK23FTRACE_JTAG_TMS23
FTRACE_JTAG_TDI23FTRACE_JTAG_TDO23
FTRACE_PROC_RESETN 23
FTRACE_D3 23,27
FTRACE_D0 23,27
FTRACE_D2 23,27FTRACE_D1 23,27
FTRACE_D5 23,27FTRACE_D4 23,27
FTRACE_D7 23,27FTRACE_D6 23,27
FTRACE_CLK23,27
M5B_JTAG_TCK 36M5B_JTAG_TMS 36
M5B_JTAG_TDI 36
M5B_JTAG_TDO 36
A10_JTAG_TRST 21
EBLST_PROC_RSTn37EBLAST_RESERVE1 37EBLAST_RESERVE037
MICTOR_JTAG_TCK 23MICTOR_JTAG_TRSTn 23
MICTOR_JTAG_TMS 23
MICTOR_JTAG_TDI 23MICTOR_JTAG_TDO 23
MICTOR_PROC_RESETn 23
1V8
3V3
3V33V3
2V5
2V5
1V8 1V8
1V8
3V3
3V3
2V5
1V8
3V33V3 3V3
1V8
1V8
3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B38 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B38 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B38 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R407 22.0
R423DNI
R54761.00k
D16GREEN_LED
R408 22.0
J24
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
C380
0.1uF
R409 22.0
MAX IIBANK2
U17B
EPM1270_M256FBGA
IOB2_1A1
IOB2_2A10
IOB2_3A11
IOB2_4A12
IOB2_5A13
IOB2_6A14
IOB2_7A15
IOB2_8A16
IOB2_9A17
IOB2_10A18
IOB2_11A19
IOB2_12A2
IOB2_13A20
IOB2_14A3
IOB2_15A4
IOB2_16A5
IOB2_17A6
IOB2_18A7
IOB2_20A9
IOB2_21B10
IOB2_22B11
IOB2_23B12
IOB2_24B13
IOB2_25B14
IOB2_26B15
IOB2_27B16
IOB2_28B17
IOB2_29B18
IOB2_30B19
IOB2_31B2
IOB2_32B3
IOB2_33B4
IOB2_34B5
IOB2_36B7
IOB2_37B8
IOB2_38B9
IOB2_39C14
IOB2_40C15
IOB2_41C16
IOB2_42C17
IOB2_43C5
IOB2_44C6
IOB2_45C7
IOB2_46D13
IOB2_47D14
IOB2_48D15
IOB2_49D16
IOB2_50D5
IOB2_51D6
IOB2_52D7
IOB2_53D8
IOB2_19A8
IOB2_35B6
C397
0.1uF
SW3
TDA08H0SB1
12345678
16151413121110
9
C370
0.1uF
R421DNI
MAX IIBANK3
U17C
EPM1270_M256FBGA
IOB3/GCLK3L20
IOB3_24J19
IOB3_1B20
IOB3_2C18
IOB3_3C19
IOB3_4C20
IOB3_5D17
IOB3_6D18
IOB3_7D19
IOB3_8D20
IOB3_9E17
IOB3_10E18
IOB3_11E19
IOB3_12E20
IOB3_13F17
IOB3_14F18
IOB3_15F19
IOB3_16F20
IOB3_17G17
IOB3_18G18
IOB3_19G19
IOB3_20G20
IOB3_21H17
IOB3_23H20
IOB3/GCLK2M20
IOB3_25J20
IOB3_26K19
IOB3_27K20
IOB3_28L19
IOB3_29M19
IOB3_30N17
IOB3_31N19
IOB3_32N20
IOB3_33P17
IOB3_35P19
IOB3_36P20
IOB3_37R17
IOB3_38R18
IOB3_39R19
IOB3_40R20
IOB3_41T17
IOB3_42T18
IOB3_43T19
IOB3_44T20
IOB3_45U17
IOB3_46U18
IOB3_47U19
IOB3_48U20
IOB3_49V19
IOB3_50V20
IOB3_51W19
IOB3_52W20
IOB3_53Y20
IOB3_22H19
IOB3_34P18
R5473 1.00k
C410
0.1uF
D15GREEN_LED
D13GREEN_LED
R5477 1.00k
R422DNI
C379
0.1uF
R5528 1.00k
R406 22.0
C371
0.1uF
D14GREEN_LED
R465 0
R424DNI
C381
0.1uF
MAX IIPower
U17E
EPM1270_M256FBGA
GNDINTJ4
GNDINTU12
GNDINTM17
GNDINTD12
GNDIOH3
GNDIOJ3
GNDIOM4
GNDION3
GNDIOU9
GNDIOV8
GNDIOV9
GNDIOV13
GNDIOH18
GNDIOJ17
GNDION18
GNDIOC8
GNDIOD9
GNDIOC12
GNDIOC13
GNDIOM18
VCCINTD11VCCINTL17VCCINTU11VCCINTK4
VCCIO1K3
VCCIO1L3
VCCIO1L4
VCCIO1M3
VCCIO2C9
VCCIO2C10
VCCIO2D10
VCCIO2C11
VCCIO3J18
VCCIO3K17
VCCIO3K18
VCCIO3L18
VCCIO4U10
VCCIO4V10
VCCIO4V11
VCCIO4V12
C382
0.1uF
R458 DNIC378
0.1uF
R466DNI
C2490 DNI C409
0.1uF
R5474 1.00k
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PLL
OSC1_CLK_SEL = HIGH selects (OSC1_CLK_SMA) SMA inputOSC1_CLK_SEL = LOW selects (OSC1_CLK_SYN) Si5356A input
CMOS
Si5358 Programmable Oscillator Use Clock Control GUI (Defaults 156.25MHz,156.25MHz,25MHz,25MHz, 25MHz, 25MHz,100MHz, 100MHz)I2C Address 70 HEX
25Mhz
100Mhz
100MHz
156.25MHz
PCIE reference clock
Populated with Si516. FS Control on DIPSWITCHFS=0: 148.35MHzFS=1: 148.50MHzI2C only available if Si571 is populated.
From FPGA
I2C Address = b'1110000'
100MHz
100MHz
148.5MHz
OSC2_CLK_SYN
OSC2_CLK_SMA
2.5V_CLK_MUX
CLKIN_50
CLK_DIFF1_N
CLK_DIFF1_P
CLK_DIFF2_N
CLK_DIFF2_P
OSC2_HPS_CLK
3.3V_VCXO
OSC2_CLK_SEL0
OSC2_CLK_SEL1
REFCLK_SDI_CP
REFCLK_SDI_CN
SI571_VCONTROL
IO_1V836,37,68
CLK_3Ap 43
IO_3V369
PCIE_REFCLK_QR0_P 8
PCIE_REFCLK_QR0_N 8
PCIE_REFCLK_SYN_P 10
PCIE_REFCLK_SYN_N 10
HPS_CLK1 21
CLK_50M_MAX 35
CP141
VCXO 41
CLKUSR 27
CLOCK_I2C_SCL40,45
CLOCK_I2C_SDA40,45
IO_2V536,68
REFCLK_SDI_P 9
REFCLK_SDI_N 9
SI516_FS36
SDI_CLK148_UP36SDI_CLK148_DOWN36
CLK_3An 43
CLK_3En 43CLK_3Ep 43
1V835,54
IO_1V81V8_PLLIO_2V5
IO_2V5
IO_2V5
IO_1V8
1V81V8
IO_1V8
IO_3V3
IO_3V3
IO_2V5
2.5V_Si516 IO_2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B39 78Thursday, April 28, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B39 78Thursday, April 28, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B39 78Thursday, April 28, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C461 0.1uF
R580
C372
0.1uF
PLL
U11
Si52112VSS2
5
DIFF16
DIFF28
DIFF29
XIN/CLKIN3
XOUT2
VDD1
VSS4
DIFF17
VDD210
C287
0.1uF
C278
0.1uF
C419
1.0nF
R660
U47
ICS83054I
CLK110
SEL17
Q1
NC26
NC311
VD
DQ
16
CLK28
CLK34
NC12
GN
D5
VD
D12
NC515
CLK014
OE3
SEL09
NC413
C462 0.1uF
C322
0.1uF
C782
2.2uF
L21
742792780C304
0.1uF
C41
0.1uF
R429 10K
R350 DNI
Y7
OSC_33MHZ
EN1
VDD4
OUT3
GND2
L28
3A, 30 Ohm FB
J16
CON2
12
C302
0.1uF
R447 22.0
C259 DNI
C303
0.1uFL22
742792780
C3390.01uF
R370DNI
C277
0.1uF
U51
50MHz
VCC4
GND2
OUT3
EN1
R149 1.00K
R2931.00K
Y225.00MHz
13
24
C305
0.1uF
J17
CON2
12
R84DNI
C783
0.1uF
C271
0.1uF
R390 22.0
L25
BLM15AG221SN1 R2921.00K
L3
742792780
U54
Si516_148.5M_148.35M
FS(OE)2
VC1
GND3
CLK+4
CLK-5
VDD6
NC(SDA)7
NC(SCL)8
C373
2.2uF
Y625.00MHz
13
24
C463
0.1uF
C254 DNI
R349 DNI
C311
0.1uF
R490 180K
C279
0.1uF
R650
C439
10uF
C272 DNIR600
R4694.99K
C253
2.2uF
C260
0.1uF
R491 180K
C428
0.1uF
C40
0.1uF
Y5
122.88 MHz
VC1
GND2
VDD4
OUT3
C258 DNI
U42
Si5338A-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
J15
SMA1
2345
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PLL (2)
LVDS
270MHz
125MHz
I2C Address = b'1110001'
LVDS
133.33MHz
133.33MHz
I2C Address = b'1110011'
133.33MHz
133.33MHz
100MHz
100MHz
1.8V_PLLA
REFCLK0_FMCB_CPREFCLK0_FMCB_CN
REFCLK_DP_CPREFCLK_DP_CN
ENET_REFCLK_CPENET_REFCLK_CN
1.8V_PLLB
EXTSMACLKN
EXTSMACLKP
REFCLK_SMA_CPREFCLK_SMA_CN
REFCLK1_FMCB_CPREFCLK1_FMCB_CN
IO_1V8 36,37,68
REFCLK_SMA_P 9REFCLK_SMA_N 9
CLK_ENET_FPGA_P 8CLK_ENET_FPGA_N 8
CLOCK_I2C_SCL39,45
CLOCK_I2C_SDA39,45
REFCLK_DP_P 9REFCLK_DP_N 9
REFCLK0_FMCB_P 7REFCLK0_FMCB_N 7
CLK_HPSEMI_P 19CLK_HPSEMI_N 19
CLK_FAEMI_P 43CLK_FAEMI_N 43
CLK_EMI_P 31CLK_EMI_N 31
REFCLK1_FMCB_P 8REFCLK1_FMCB_N 8
IO_1V8
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B40 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B40 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B40 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C52
0.1uF
L24
BLM15AG221SN1
C323 DNI
C341 DNI
Y925.00MHz
13
24
R85 4.7K
C45
0.1uF
C55
0.1uF
C343 0.1uF
C51
0.1uF
J141
2 3 4 5
C349 0.1uF
L23
BLM15AG221SN1
C325 0.1uF
J131
2 3 4 5
C50
0.1uF
C53
0.1uF
C46
0.1uF
C332 0.1uF
C326 0.1uF
C342 0.1uF
C49
0.1uF
C340 DNI
C44
0.1uF
U49
Si5338B-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
U50
Si5338B-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
C39 0.1uF
C345 DNI
R86 4.7K
C344 DNI
C54
0.1uF
C47
0.1uF
C333 0.1uF
C38 0.1uF
C348 0.1uF
Y825.00MHz
13
24
C48
0.1uF
C324 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FROM FPGA RX_CLK
CMOS INPUT -> LVPECL OUTPUT
Clock Cleaner3.3V_VCC1_5_6
3.3V_VCC7
3.3V_VCC9
3.3V_VCC3
3.3V_VCC8_10
3.3V_VCC4
3.3V_VCC113.3V_VCC12
3.3V_VCC2
CLK_CLN_IN_C_PCLK_CLN_IN_C_N
OSC_IN_POSC_IN_N
LMK_SYNC_IN
CP2
3.3V_MUX
LO_SMA
LMK_CLK_P
LMK_CLK_N
LMK_SDCLK_N
LMK_SDCLK_P
LMK_CLK_IN_NLMK_CLK_IN_P
MUX_OSC_IN_NMUX_OSC_IN_P
LMK_OSC_SEL
OSC_IN_C_P
OSC_IN_C_N
LMKR_CLK_FMC_PLMKR_CLK_FMC_N
LMKR_SYSREF_FMC_PLMKR_SYSREF_FMC_N
LMKR_CLK_FMCB_PLMKR_CLK_FMCB_N
LMKR_SYSREF_FMCB_PLMKR_SYSREF_FMCB_N
SMA_LMK_CLK_IN
LMK_SFPCLK_C_PLMK_SFPCLK_C_N
2.0V_VTD
LMK_FMCCLK_C_NLMK_FMCCLK_C_P
IO_3V369
SPI_CSn36
RCLOCK_OUT_P43
RCLOCK_OUT_N43
LMK_RESET35,36
SPI_CLK36SPI_SDIO36
VCXO39
IO_2V5 36,68
CP1 39
LMK_CLK_FMC_P 43LMK_CLK_FMC_N 43
LMK_SYSREF_FMC_P 43LMK_SYSREF_FMC_N 43
LMK_CLK_FMCB_P 43LMK_CLK_FMCB_N 43
LMK_SYSREF_FMCB_P 43LMK_SYSREF_FMCB_N 43
LMK_SFPCLK_P 7LMK_SFPCLK_N 7
LMK_CLEAN_CLK_P 43LMK_CLEAN_CLK_N 43
LMK_SYSREF_P 43LMK_SYSREF_N 43
LMK_FMCCLK_P 9LMK_FMCCLK_N 9
IO_3V3
IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B41 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B41 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B41 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R175 0
U26LMK04828
CLKIN0p37
CLKIN0n38
CLKIN1p/FBCLKINp/FINp34
CLKIN1n/FBCLKINn/FINn35
OSCINp43
OSCINn44
SDIO20 SCK19
RESET5
CLKin_SEL058
CLKin_SEL159
SYNC6
VCC1_VCO10
VCC2_GC117
DAP65
CS18
VCC3_SYSREF21
VCC4_CG226
VCC5_DIG33
VCC6_PLL136
VCC7_OSCout39
VCC8_OSCin42
VCC9_CP245
VCC10_PLL247
VCC11_CG353
VCC12_CG064
DCLKOUT0p1
DCLKOUT0n2
SDCLKOUT1p3
SDCLKOUT1n4
DCLKOUT2p15
DCLKOUT2n16
SDCLKOUT3p13
SDCLKOUT3n14
DCLKOUT4p24
DCLKOUT4n25
SDCLKOUT5p22
SDCLKOUT5n23
DCLKOUT6p27
DCLKOUT6n28
STATUS_LD131
STATUS_LD248
OSCOUTp40
OSCOUTn41
SDCLKOUT7n30
DCLKOUT8p51
DCLKOUT8n52
SDCLKOUT9p49
SDCLKOUT9n50
DCLKOUT10p54
DCLKOUT10n55
SDCLKOUT7p29
SDCLKOUT11p56
SDCLKOUT11n57
CPOUT132
CPOUT246
LDObyp111
LDObyp212
DCLKOUT12p62
DCLKOUT12n63
SDCLKOUT13p60
SDCLKOUT13n61
C832
1uF
C802
0.1uF
C101
0.1uF
R207 820,1%
L9
742792780
C821
0.01uF
R174 0
C12247pF
R72249.9
C103 0.1uF
L6
3A, 30 Ohm FB
L32
3A, 30 Ohm FB
R203
DNI
C113 0.1uF
R173 0
U25
NB6L72MNGSEL1
8
VCC13
D0n3 D0p2
GND16
VTD04
Q0p15
Q0n14
D1p6
D1n7
VTD15
GND_PAD17SEL0
1
Q1n10Q1p11
VCC12
GND9
C794
0.01uF
D34 Green_LED
J33
CON2
12
R72149.9
C801
0.1uF
J341
2 3 4 5
C820
0.01uF
C114 0.1uF
L8
3A, 30 Ohm FB
R204
DNI
R208 820,1%
R166 0
L33
3A, 30 Ohm FB
R199
DNI
C793
0.01uF
R111.00K
R165 0
R591.00K
D35 Green_LED
L34
3A, 30 Ohm FB
R190 100
C1213900pF
C792
0.01uF
C115 0.1uF
R198620
C791
0.01uF
C116 0.1uF
J38
1
2 3 4 5
C110
10uF
J401
2345
J371
2 3 4 5
J391
2345
L29
3A, 30 Ohm FB
C831
0.01uF
C1070.1uF R4149
1.00K
R189
240
R183 100
R16439K
XJ13
881545-2
C112
0.1uF
R191
DNI
J44
1
2 3 4 5
C131 0.1uF
R197
240
R209 820,1%
R177 10K
L30
3A, 30 Ohm FB
C132 0.1uF
C129 0.1uF
J451
2 3 4 5
C823
0.1uF
D36 Green_LED
R168 0
C812
0.01uF
L31
3A, 30 Ohm FB
R182 1.96K
R178 10K
C108 0.1uF
C130 0.1uF
C824
0.1uF
C104 0.1uF
R167 0
C106
0.1uF
R210 820,1%
C804
0.01uF
R188 3.01K
C109 0.1uF
C810
1uF
R176 0
C1000.68uF
C803
0.01uF
D33 Green_LED
C822
0.01uF
C120
0.1uF
C811
0.1uF
L7
3A, 30 Ohm FB
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
User I/O
3V3 Power on LED
MAX_LOAD
MAX_ERROR
MAX_CONF_DONE
PGM_LED1
PGM_LED2
PGM_LED0
USER_LED_HPS0
USER_LED_HPS3
USER_LED_HPS2
USER_LED_HPS1
USER_LED_FPGA0
USER_LED_FPGA3
USER_LED_FPGA2
USER_LED_FPGA1
MAX_ERROR35
MAX_LOAD35
MAX_CONF_DONE35
PGM_LED035
PGM_LED135
PGM_LED235
USER_LED_HPS035
USER_LED_HPS135
USER_LED_HPS235
USER_LED_HPS320,35
USER_LED_FPGA035
USER_LED_FPGA135
USER_LED_FPGA235
USER_LED_FPGA335
USER_DIPSW_HPS0 35USER_DIPSW_HPS1 35USER_DIPSW_HPS2 20,35USER_DIPSW_HPS3 20,35
USER_DIPSW_FPGA0 35USER_DIPSW_FPGA1 35USER_DIPSW_FPGA2 35USER_DIPSW_FPGA3 35
PGM_CONFIG35PGM_SEL35Logic_RESETn35EXT_INTn35
USER_PB_HPS035USER_PB_HPS135USER_PB_HPS235USER_PB_HPS320,35
USER_PB_FPGA035USER_PB_FPGA135USER_PB_FPGA235USER_PB_FPGA335
2V5 38,68,71
1V8 23,38,39,55
3V3 37,38,44,53,54,55,65,69,71
FAPRSNT_N17
FBPRSNT_N18
SECURITY_MODE 35
FACTORY_LOAD 35
DC_POWER_CTRL 35
I2C_flag 35
IO_3V3 69
IO_1V8 36,37,68
3V3
2V5
1V8
3V3
3V3
3V3
3V3
3V3
IO_3V3
IO_3V3
IO_1V8
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B42 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B42 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B42 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R125 100
R139 100
R116 100
S7
PB Switch1 2
R5501 100
D28 Green_LED
R138 100
D22 Green_LED
S10
PB Switch1 2
S12
PB Switch1 2
D29 Green_LED
D19 Green_LED
S14
PB Switch1 2
S4
PB Switch1 2
D25 Green_LED
D31 Green_LED
S3
PB Switch1 2
R123 100
R598 100
D18 Green_LED
R113 100
D27 Green_LED
D32 Green_LED
S5
PB Switch1 2
R127 100
D30 Green_LED
R5529 10K
D24 Green_LED
R5532 10K
R115 100
D20 Green_LEDR588 100
R137 100
OPEN
SW1
TDA04H0SB1
12345
678
R122 100
R5530 10K
D21 Green_LED
S8
PB Switch1 2
R117 100
D26 Green_LED
R5531 10K
D23 Green_LED
S9
PB Switch1 2
S6
PB Switch1 2
S11
PB Switch1 2
SW2
TDA08H0SB1
12345678
16151413121110
9
R126 100
S13
PB Switch1 2
R128 100
R136 100
D42 Green_LED
D17 Red_LED
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Clock Resistor Mux
FMC B Clock MUX for FMC card
FMC A Clock MUX for FMC card
Clock MUX for 3A Bank reference clock
Clock MUX for 3E Bank reference clock
Clock MUX for 3G Bank reference clock
MUX for supporting Altera FMC spec
FALAP117FALAN117
FALAP517FALAN517
FBLAP118FBLAN118
FBLAP518FBLAN518
Refclk_3An30Refclk_3Ap30
Refclk_3En29Refclk_3Ep29
FBCLK1M2CP 18FBCLK1M2CN 18
CLK_3Ap 39CLK_3An 39
FACLK1M2CN 17FACLK1M2CP 17
FACLK3BIDIRP 17FACLK3BIDIRN 17
LMK_SYSREF_N 41LMK_SYSREF_P 41
LMK_CLEAN_CLK_N 41LMK_CLEAN_CLK_P 41
CLK_3Ep 39CLK_3En 39
FACLK2BIDIRP 17FACLK2BIDIRN 17
RCLOCK_OUT_N 41RCLOCK_OUT_P 41FPGA_RCLK_3Gp28
FPGA_RCLK_3Gn28
FPGA_Refsys_3Ep29FPGA_Refsys_3En29
LMK_CLK_FMC_P 41LMK_CLK_FMC_N 41
FA_LA_DEVCLK_P 28FA_LA_DEVCLK_N 28
LMK_SYSREF_FMC_P 41LMK_SYSREF_FMC_N 41
FA_LA_SYSREF_P 28FA_LA_SYSREF_N 28
LMK_CLK_FMCB_P 41LMK_CLK_FMCB_N 41
FB_LA_DEVCLK_P 30FB_LA_DEVCLK_N 30
LMK_SYSREF_FMCB_P 41LMK_SYSREF_FMCB_N 41
FB_LA_SYSREF_P 30FB_LA_SYSREF_N 30
FBHA_P6M18FBHA_N6M18
FBD15C2MP 8FBD15C2MN 8
FBHA_P6 29FBHA_N6 29
FBD12C2MP 8FBD12C2MN 8
FBHA_P17M18FBHA_N17M18
FBHA_P17 29FBHA_N17 29
FBHA_P21 29FBHA_N21 29
FBD15M2CP 8FBD15M2CN 8
FBHA_P21M18FBHA_N21M18
FBHA_N23 29FBHA_P23 29
FBD10C2MN 8FBD10C2MP 8
FBHA_N23M18FBHA_P23M18
FACLK0M2CN 17FACLK0M2CP 17
CLK_FAEMI_N 40CLK_FAEMI_P 40
FA_EMI_CLKN28FA_EMI_CLKP28
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B43 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B43 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B43 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R5760
R610DNI
R6010
R587DNI
R3610
R355DNI
R574DNI
R6120
R3830
R586DNI
R5750
R3540
C335 0.1uF
R632DNI
R404DNI
R5850
R6330
R348DNI
C336 0.1uF
R6130 R437DNI
R5840
C346 0.1uF
R3470
R405DNI
R364DNI
R470DNI
C354 0.1uF
C367 0.1uF
R579DNI
R445DNI
R372DNI
C376 0.1uF
R578DNI
R471DNI
R6210
R594DNI
R382DNI
R5960
R411DNI
R3650
R593DNI
R604DNI
C422 0.1uF
R620DNI
R5950
R427DNI
R603DNI
C423 0.1uF
R3730
R360DNI
R577DNI
R6020
R611DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Reset Circuit
RESET CIRUIT
PB_COLD_RESETn
WARM_RESETnPB_WARM_RESETn
COLD_RESETn3V335,42,51
HPS_cold_RESETn 35
HPS_warm_RESETn 35
3V3
3V33V3
3V3 3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B44 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B44 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B44 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R43020K
R2890
R1620K
R92 100K
R4400
S2
PB Switch1 2
U14
MAX811
GND1
RESET2
VCC4
MR3
C3570.1uF
R294 100K
U1
MAX811
GND1
RESET2
VCC4
MR3
C1730.1uF
S1
PB Switch1 2
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
I2C ADDRESS:b'1101000'
I2C ADDRESS:b'1010001'
I2C ADDRESS: 0x28
Note to assembler: Use this resistorto attach to LCD Header (followassembly instructions).
I2C ADDRESS:b'1001100' I2C MUX
PMBus
0.04A
VBAT
LCD_SDALCD_SCL
Bus1_SDABus1_SCL
A10_PMBUSDIS_N35
LTSDA 71LTSCL 71
LT_3V3 69
IO_3V3 69
EXTA_SCL 10,13,17EXTA_SDA 10,13,17
EXTB_SCL 14,18EXTB_SDA 14,18
OVERTEMPn 35TSENSE_ALERTn 35
PMbus_SDA_3V3 27,51,56,73PMbus_SCL_3V3 27,51,56,73
A10_2L_SDA20,35A10_2L_SCL20,35
CLOCK_I2C_SCL 39,40CLOCK_I2C_SDA 39,40
PMbus_ALTERTn 35,51,56,73
IO_2V5 36,68
IO_5V 50
TEMPDIODE_P21
TEMPDIODE_N21
IO_5V
IO_3V3
IO_3V3
IO_3V3IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_2V5IO_2V5
IO_2V5
IO_3V3
IO_5V
IO_5V
IO_5VIO_3V3
IO_2V5
IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B45 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B45 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B45 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
B1
2x16 LCD BOM I2C
C331
0.1uF
C314
0.1uF
J28
2X6
11
22
33
44
55
66
77
88
99
1010
1212
1111
R614 0
R402 0
R387
DNI
R380
4.7K
R605 0
C320
0.1uF
R377 0
R51 4.7K
C321
0.1uF
C309
0.1uFC338
0.1uF
R397 0
C310
0.1uF
R395
DNI
R50 0
U5
DS1339C
SDA16
SCL1
GND15
VCC3
VBACKUP14
SQW/INT2
NC54
NC65
NC76
NC87
NC98
NC109
NC410 NC311 NC212 NC113
C330
0.1uF
R389 0
R399 200
U43
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R386
4.7K
R394
DNI
R410
4.7K
R385 0
C315
0.1uF
BT1
12
R375 0
C1562
2200pf
U45
24LC32A
A01
A12
A23
GND4
VCC8
WP7
SCL6
SDA5
R374
4.7K
U48
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
U44
FXMA2102UMX
A02
A13 B0
7
B16
VCCA1
GND4
OE5
VCCB8
R398 0
R379
4.7K
J35
LCD_HEADER
123456789
10
R401
4.7K
R388 0
C18 0.1uF
R29 0
U46
MAX1619
ADD16
ADD010
SMBCLK14
SMBDATA12DXP
3
DXN4
VCC1
OVERTn9
ALERTn11
STBYn15 GND1
2
GND27
GND38
NC15
NC213
NC316
R757
4.7K
C2350
0.1uF
R776
4.7K C873
0.1uF
R396
DNIR376
4.7K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
A10 SOC DEV KIT PDN Diagram
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B46 78Tuesday, May 24, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
A10 SOC Power Sequence
1. If the VCC voltage level is different from VCCT_GXB, VCCR_GXB, and orVCCRAM, then ramp VCC first followed by VCCT_GXB, VCCR_GXB, and VCCRAM (In any order) within group 12. All Power rails must ramp completely to full rail voltage within the Tramp (0.2ms to 4ms)3.VCCBAT (1.2-1.8V) can be powered up/down at any time and is not shown in the power sequence4.The Power down sequence is the reverse of the power up sequence
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B47 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B47 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B47 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B48 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B48 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B48 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
12V ATX INPUT (12.5A)
16A 1A
4A
1A
10A
Input connector for 200 Watt AC/DC Adapter 12V Power PMOS Switches
3v/ms
3v/ms
3v/ms
3v/ms
Adapter_DC_12V
MAIN_GATE
FMCB_EN35
PCIE_EN35
FMCA_EN35
FMCB_12V 18
PCIE_12V 10
FMCA_12V 17
MAIN_12V 27,50,51,55,68
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B49 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B49 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B49 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
D41
B530C
Q39MMBT2222A-7-F
CE
B
R68610
Q9
DMP3098L
S
D
G
R79549.9K
R520849.9K
C8821uF
R53531.00k
R80810K
C8791uF
R80749.9K
Q30MMBT2222A-7-F
CE
B
Q37MMBT2222A-7-F
CE
B Q31MMBT2222A-7-F
CE
B
C64
330uF25V
R75610 R786
10
C899
0.1uF
R5354
1.00k
C1021uF
J31
PCIe 2x4 ATX
12V1
12V2
12V3
GND8
SENSE14 SENSE06
GND5
GND7
R73510
R68510K
R16249.9K
C67
330uF25V
R775100K
TP90
Q8Si7635DP
1
567
4
8
23
Q35DMP3098L
S D
G
SW5SW_SLIDE_DPDT
1
236
5
4
Q34DMP3098L
S D
G
TP26
R187100K
TP103
R53741.00k
R78110
C63
330uF25V
TP104
TP114
TP84
R78549.9K
R75549.9K
R80310K
R17110
R796100K
C777
0.1uF
J36
PD-40S
GND3VOUT2VOUT1
GND4
SGND5
SGND6
SGND7
SGND8
SGND9
R78010
R172100K
R79449.9K
C65
330uF25V
Q42MMBT2222A-7-F
CE
B
R19610
TP113
R5375
1.00k
TP24
R68749.9K
Q36
DMP3098L
S
D
G
C898
0.1uF
R77349.9K
Q12Si7635DP
1
567
4
8
23
C8721uF
R5214
1.00k
R52131.00k
Q38
DMP3098L
S
D
G
R77410
R81049.9K
Q41MMBT2222A-7-F
CE
B
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0402
0402
0402
Output capacitors chosen for smallest footprint. For lower Vout ripple option, use two 47uF/1206/X5R capacitors.
PVIN = 12V
Connect input and output caps to GND plane through mulitple vias. (See the Gerber files.)
0402X7R
A single through-hole via connects these AGND pins to the GND plane.
0402X7R
0402X7R
X7R
0402/X7R
0402
0402
0402
Cin: 22u 1206 25V X5R
0402
VOUT = 5V
Rclx and Rfs chosenfor 12Vin/1.2Vout
0402 or0201
12V to 5V Converter
1.5A
PO_EN
5V0_Pgood 35
IO_5V11,12,22,25,45,71
MAIN_12V 49
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B50 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B50 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B50 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C834
TP100
R709
100k
R728560
C8051uF R696
49.9K
TP105
TP92
R5508DNI
TP93
C7881uF
R503080.6k
TP102
C79622nF
R69514.3K
C787 47nF
F1 1AC78556pf
C786680PF
R70810K
C840R69110K
R70768.1K0402
R7104.75k
U66EN2342QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
2626
NC
(SW
)27
27
NC
(SW
)28
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
PG
ND
34
S_OUT48
S_IN47
BGND46
VDDB45
BTMP44
PG43
AVINO42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
NC
(SW
)61
61
AG
ND
60
NC
5959
FQAD
J58
RC
LX57
SS
56
EA
OU
T55
VFB
54
AG
ND
53
AG
ND
52
AV
IN51
EN
AB
LE50
POK
49
GN
D_P
AD
69
R6924.7
C795
0.22uF
R7050
R70630.1K0402
C835
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
I2C ADDRESS:b'1001110'
6A
20A
12V to 3V3 Converter
INTVCC_5V_2
3V3_SENSE+
VDD33_2
COMP02
VDD25_2
SHARE_CLK2
3V3_SENSE-
SYNC_2
PMbus_SDA_3V3 27,45,56,73
PMbus_SCL_3V3 27,45,56,73
PMbus_ALTERTn 35,45,56,73
3V3
37,38,44,53,54,55,65,69,71
MAIN_12V49
3V3_Pgood 35
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
3V3
3V3
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B51 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B51 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B51 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C9668pF
R14
810
K
R147 22.6K
R49
9D
NI
TP131
R54
610
K
TP61
R54
510
K
C84DNI
C9122uF
R54
110
K
U24
LTM4676
VOUT0_1A1
VOUT0_2A2
VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISN
S1b
-G
1
ISN
S1b
+H
1
VO
UT1
_1J1
VO
UT1
_2J2
VO
UT1
_3J3
VO
UT1
_4K
1
VOUT0_4B1
VOUT0_5B2
VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISN
S1a
-G
2
ISN
S1a
+H
2
VO
UT1
_5K
2
VO
UT1
_6K
3
VO
UT1
_7L1
VO
UT1
_8L2
VOUT0_7C1
VOUT0_8C2
VOUT0_9C3
VOUT0_12D3
GN
D1
A4
GN
D2
A6
GN
D3
A7
GN
D4
A8
VO
UT1
_9L3
VO
UT1
_10
M1
VO
UT1
_11
M2
VO
UT1
_12
M3
GN
D5
A9
GN
D6
A10
GN
D7
B4
GN
D8
B5
ASELG4
FSWPHCFGH4
GN
D9
B6
GN
D10
B7
GN
D11
B8
GN
D12
B9
GPIO0E4
GPIO1F4
SNUB0A5
GN
D13
C4
TSNS0bC5
TSNS0aD5
ALERTE5
RUN0F5
VOUT0CFGG5
VTRIM0CFGH5
TSN
S1a
J5TS
NS
1bK
5
GN
D14
C6
SN
UB
1M
5G
ND
15C
7
GN
D16
C8
GN
D17
C9
SDAD6
SCLE6
RUN1F6
VOUT1CFGG6
VTRIM1CFGH6
VDD25J6
WPK6
GN
D18
D4
GN
D20
E3
GN
D21
F3
GN
D22
F10
GN
D23
G3
GN
D24
G10
SYNCE7
GN
D45
M9
GN
D46
M10
SHARE_CLKH7
VDD33J7
GN
D25
G11
GN
D26
G12
GN
D39
L8G
ND
38L7
GN
D40
L9
GN
D27
H3
COMP0bD8
COMP0aE8
SG
ND
3F7
SG
ND
4F8
CO
MP
1aH
8
CO
MP
1bJ8
GN
D28
H10
GN
D29
J4
GN
D44
M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1F9
INTVCC_2G9
VO
SN
S1
H9
VO
RB
1J9
GN
D30
J10
GN
D35
L4
GN
D36
L5
GN
D31
K4
SW0B10
DN
C2
E11
VORB0+D10
VORB0-E10
GN
D37
L6
GN
D32
K7
GN
D33
K8
GN
D34
K9
DN
C1
C10
SW
1L1
0
GN
D41
M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DN
C4
K10
VINL_2F12
GN
D42
M6
DN
C3
H11
VIN
H1_
1H
12
VIN
H1_
2J1
1
VIN
H1_
3J1
2
VIN
H1_
4K
11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GN
D43
M7
VIN
H1_
5K
12
VIN
H1_
6L1
1
VIN
H1_
7L1
2
VIN
H1_
8M
11
VIN
H1_
9M
12
SG
ND
1G
7
SG
ND
2G
8
GN
D19
D7
R5710
C9222uF
R54
810
K
C69100uF
TP83
R16010K
TP72
R54
710
K
C82
330uF6.3V
R156DNI
R1200
TP130
R54
910
K
C73100uF
R1210
R152 DNI
TP66
TP73
C83DNI
R159 DNI
C71100uF
R132 22.6K
C80330uF6.3V
C74100uF
R157DNI
TP62
C72100uF
R542
4.75K
R1510
C76
100u
F
TP65
R509DNI
C952200pF
C75100uF
TP25
R158 22.6K
R146 DNI
R497 DNI
TP23
R49
80
R1310
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B52 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B52 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B52 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206 1206
0402
0402
0402
0402
VIN = 2.4 - 6.6 VDC
A single through-hole test point connects the AGNDpin to the GND plane.
Connect the output cap to the GND plane through multiple vias
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
X5RX5R
2A
2A
3V3 to 2V5 Converter
PDEN
2V5out
2V5_Pgood 35
3V3 35,42,51
2V538,68,71
2V5I_P71
2V5I_N71
3V3
2V5
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B53 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B53 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B53 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C1251uF
R7360
R202
0.001
R737
100k
C798 47uF
R732DNI
R744
200k
R7450
TP96
C797 22uF
U68EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VO
UT
7
VO
UT
8
VO
UT
9
VO
UT
10
VO
UT
11
NC
(SW
)12
PG
ND
13
PG
ND
14
PG
ND
15
PG
ND
16
PG
ND
17
PG
ND
18
PV
IN19
NC2525
NC2424
NC2323
NC2222
PVIN21
PVIN20
NC
(SW
)138
NC
(SW
)237
NC
(SW
)336
NC
(SW
)435
NC
(SW
)534
AV
IN33
AG
ND
32
VFB
31
SS
30
RLL
M29
POK
28
EN
AB
LE27
LLM
/SY
NC
26
GN
D_P
AD
39
C82615nF
TP95
R738
86.6k
R195 10KC827
15pF
R201 10K
TP101
C111 47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)
X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5R
A single through-hole viaconnects the AGNDpin to the GND plane.
0402
0402
0402
0201
0.999V
10A
0402
3.3V to 1.8V Converter
8A
5A
1V8_OUT
1V8_Pgood 35
3V3 35,42,51
1V8DAC_P 73
1V8DAC_N 73
1V8SENSP73
1V8SENSN73
1V823,38,39,55
A10_1V8I_P71
A10_1V8I_N71
1V8
3V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B54 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B54 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B54 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R723
100k
R69915k
TP109
C841 47uF
R7150
TP97
C862 47uF
R7140
R712 10K
R758100
C789 15nF
R701
DNI
R713
5.49k
R759100
C850 47uF
C7990.22uF
R700
DNI
C874
0.22uF
TP160
TP33
C842 47uF
R711 DNI
U67EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1919
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
VO
UT
25
VO
UT
26
VO
UT
27
VO
UT
28
NC
2929
NC
(SW
)30
30
NC
(SW
)31
31
PG
ND
32
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
S_IN56
BGND55
VDDB54
NC5353
NC5252
PVIN51
PVIN50
PVIN49
PVIN48
PVIN47
PVIN46
PVIN45
PVIN44
PVIN43
NC
7676
NC
7575
NC
7474
NC
7373
NC
7272
NC
(SW
)71
71
NC
(SW
)70
70
EN
_PB
69
FQAD
J68
NC
(XR
EF)
67
VS
EN
SE
66
SS
65
EA
OU
T64
VFB
63
M/S
62
AG
ND
61
AV
IN60
EN
AB
LE59
POK
58
PG
ND
38S
_OU
T57
PVIN42
PVIN41
PVIN40
PVIN39
NC1515
NC1616
NC1717
NC1818
GN
D_P
AD
77
R698160k
R258
0.00025
R6970R271 10K
C78027pF
R522980.6K
R272 10K
C849 47uFC1721uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Typical 12V good threshold voltage is 10.62V. Typcial 12V bad threshold voltage is 10.11V
9A 3.5A10A
A10 12V,3V3 and 1V8 PMOS Switches
J58 need be shorted if MAXV is not programmed
10A
A10_12V 56,73MAIN_12V49
A10_EN35
A10_main_3V3 58,59,60,62,63,64,66,67
10V_Fail_n 35
10V_good 35
3V335,42,51
1V835,54
A10_main_1V8 68
3V3
3V3
A10_12V
3V3
1V8
MAIN_12V
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B55 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B55 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B55 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
TP88
C1561
100uF6.3V
R69310K
U39
TPS3700
OUTA1
OUTB6
VDD5
INA+3
INB-4
GND2
Q40MMBT2222A-7-F
CE
B
R68210
R5971.00k
Q44
SiRA00DP
1567
4
8
23
R608100K
Q28MMBT2222A-7-F
CE
B
TP68
TP42
J58
CON2
12
TP69
TP45
C20
0.1uF
TP37
TP44
R694
10K
R680100K
R68149.9K
C8940.01uF
C5990.01uF
TP87
Q46MMBT2222A-7-F
CE
B
R5210K
Q27
SiRA00DP
1567
4
8
23
C7741uF
R5449.9
R277100K
Q29MMBT2222A-7-F
CE
B
R273100K
R54911.00k
R2781.00k
R5325.5K
TP89
R60710K
C779
0.1uF
Q10Si7635DP
1
567
4
8
23
C1560
100uF6.3V
R5510K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.5A
30A0.95V output
I2C ADDRESS:b'1000010'Need be open-drain output
12V to 0V9 Converter
VDD25_1
SHARE_CLK1
0.9VO_SENSE+
0.9VO_SENSE-
SYNC_1
VDD33_1
COMP01
INTVCC_5V_1
A10_12V55
A10_0V9 74,76
A10_VCCLSENSE74
A10_GNDSENSE74
A10_0V9_EN 35
PMbus_SDA_3V3 27,45,51,73
PMbus_SCL_3V3 27,45,51,73
PMbus_ALTERTn 35,45,51,73
P0V9Pgood 35
GND_SIGNAL1
GND_SIGNAL1
GND_SIGNAL1
GND_SIGNAL1
GND_SIGNAL1
GND_SIGNAL1
A10_12V
A10_0V9
A10_0V9
A10_12V
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B56 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B56 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B56 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
TP41
C838100uF
U31
LTM4677
VOUT0_1A1
VOUT0_2A2
VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISN
S1b
-G
1
ISN
S1b
+H
1
VO
UT1
_1J1
VO
UT1
_2J2
VO
UT1
_3J3
VO
UT1
_4K
1
VOUT0_4B1
VOUT0_5B2
VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISN
S1a
-G
2
ISN
S1a
+H
2
VO
UT1
_5K
2
VO
UT1
_6K
3
VO
UT1
_7L1
VO
UT1
_8L2
VOUT0_7C1
VOUT0_8C2
VOUT0_9C3
VOUT0_12D3
GN
D1
A4
GN
D2
A6
GN
D3
A7
GN
D4
A8
VO
UT1
_9L3
VO
UT1
_10
M1
VO
UT1
_11
M2
VO
UT1
_12
M3
GN
D5
A9
GN
D6
A10
GN
D7
B4
GN
D8
B5
ASELG4
FSWPHCFGH4
GN
D9
B6
GN
D10
B7
GN
D11
B8
GN
D12
B9
GPIO0E4
GPIO1F4
SNUB0A5
GN
D13
C4
TSNS0bC5
TSNS0aD5
ALERTE5
RUN0F5
VOUT0CFGG5
VTRIM0CFGH5
TSN
S1a
J5TS
NS
1bK
5
GN
D14
C6
SN
UB
1M
5G
ND
15C
7
GN
D16
C8
GN
D17
C9
SDAD6
SCLE6
RUN1F6
VOUT1CFGG6
VTRIM1CFGH6
VDD25J6
WPK6
GN
D18
D4
GN
D20
E3
GN
D21
F3
GN
D22
F10
GN
D23
G3
GN
D24
G10
SYNCE7
GN
D45
M9
GN
D46
M10
SHARE_CLKH7
VDD33J7
GN
D25
G11
GN
D26
G12
GN
D39
L8G
ND
38L7
GN
D40
L9
GN
D27
H3
COMP0bD8
COMP0aE8
SG
ND
3F7
SG
ND
4F8
CO
MP
1aH
8
CO
MP
1bJ8
GN
D28
H10
GN
D29
J4
GN
D44
M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1F9
INTVCC_2G9
VO
SN
S1
H9
VO
RB
1J9
GN
D30
J10
GN
D35
L4
GN
D36
L5
GN
D31
K4
SW0B10
DN
C2
E11
VORB0+D10
VORB0-E10
GN
D37
L6
GN
D32
K7
GN
D33
K8
GN
D34
K9
DN
C1
C10
SW
1L1
0
GN
D41
M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DN
C4
K10
VINL_2F12
GN
D42
M6
DN
C3
H11
VIN
H1_
1H
12
VIN
H1_
2J1
1
VIN
H1_
3J1
2
VIN
H1_
4K
11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GN
D43
M7
VIN
H1_
5K
12
VIN
H1_
6L1
1
VIN
H1_
7L1
2
VIN
H1_
8M
11
VIN
H1_
9M
12
SG
ND
1G
7
SG
ND
2G
8
GN
D19
D7
R253DNI
TP35
R2310
R81
2D
NI
R238DNI
R186 DNI
C806100uF
C14322uF
R2320
R76
2D
NI
C1651800pF
TP39
R240DNI
R275 DNI
R27410K
C151DNI
C14422uF
C118330uF6.3V
R24
2D
NI
TP118
R270 1.65K
R25217.8K
R21
4D
NI
C819
330uF6.3V
R76
310
K
C807
330uF6.3V
R2490
C124100uF
C152DNI
TP34
TP38
R269 1.65K
R24
110
K
C123100uF
C127100uF
R251DNI
C161DNI
R801 DNI
TP29
R254 1.65K
R7790
R27
610
K
R813 DNI
C12
610
0uF
TP36
R250DNI
C147330uF6.3V
TP30
TP120
TP117
TP119
D43SL03-GS08
C818100uF
R21
30
TP121
C117100uF
R80
010
K
R2330
TP40
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B57 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B57 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B57 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206 1206
0402
0402
0402
0402
VIN = 2.4 - 6.6 VDC
A single through-hole test point connects the AGNDpin to the GND plane.
Connect the output cap to the GND plane through multiple vias
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
For a PWM application RLLM pin can float, and LLM/SYNC has to be tied to GND.
X5RX5R
2A
1A
3.3V to 0.9V Converter
Change Votlage to 0.9V for production FPGA
PPEN
0V95out
P0V95Pgood 35
0V9574,76
A10_Main_3V3 55
A10_0V95_EN 35,73
A10_0V95I_P71
A10_0V95I_N71
0V95
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B58 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B58 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B58 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C767 22uF
R66949.9
C76015nF
R135
0.001
R655
1.00M
TP81
C740
15pF
C739 47uF
TP86
R668DNI
R657
100k
R652
200k
TP85
R6500
R133 10K
R134 10K
TP74
C771uF
U64EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VO
UT
7
VO
UT
8
VO
UT
9
VO
UT
10
VO
UT
11
NC
(SW
)12
PG
ND
13
PG
ND
14
PG
ND
15
PG
ND
16
PG
ND
17
PG
ND
18
PV
IN19
NC2525
NC2424
NC2323
NC2222
PVIN21
PVIN20
NC
(SW
)138
NC
(SW
)237
NC
(SW
)336
NC
(SW
)435
NC
(SW
)534
AV
IN33
AG
ND
32
VFB
31
SS
30
RLL
M29
POK
28
EN
AB
LE27
LLM
/SY
NC
26
GN
D_P
AD
39
C78 47uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDCConnect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
Optional EAOUT test pointis used for monitoring purposes only.
0201X5R
0402
1206 X5R
0402
0.896V
3A
1.5A
3.3V to 0.9V converter ( HPS Core)
HPS_0V95outHPS_0V9574,76
A10_Main_3V3 55
HPS_Pgood 35
A10_0V95_EN 35,73
A10_0V95DAC_P 73
A10_0V95DAC_N 73
A10_0V95SENSP73
A10_0V95SENSN73
A10_HPS0V95I_N71
A10_HPS0V95I_P71
HPS_0V95
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B59 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B59 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B59 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R665
1.78M
TP94
J30
CON2
12
R702160kR170 10K
R66649.9
R161 10K R68915k
C773 47uFC991uF
C759 22uF
R169
0.001
TP78
R683 DNI
R656
100k
C775 15nF TP79
R688 10K
R6770
U65EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
TP77
R141100
R667324K
R7030
C772 47uF
R142100
R14010K
C7570.22uF
C85
0.22uF
R684
3.57k
C758 22uF
R153
DNI
TP80
C78122pF
R143
DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206
1206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)
X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5R
A single through-hole viaconnects the AGNDpin to the GND plane.
4A
0402
0402
0402
0201
Feedback network configured for 3.3Vin /1.0Vout 0.999V
10A
0402
3.3V to 1.0V Converter
+-15% rangeUpdate the value to 226K from 240K for 1.03V output
1.03V output
A10_1V0OUT
PFEN
A10_Main_3V3 55
A10_1V074,77
A10_1V0DAC_P 73
A10_1V0DAC_N 73
A10_1V0SENSP73
A10_1V0SENSN73
A10_1V0_EN 35,73
1V0_Pgood 35
A10_1V0I_P71
A10_1V0I_N71
A10_Main_3V3
A10_1V0
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B60 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B60 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B60 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R460
100k
C456 47uF
R494
619K
TP60
R5040
TP15
TP58
R50312k
R502160k
TP59
R48810K
C455 47uF
C45227pF
C454 47uF
R495226K
U56EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1919
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
VO
UT
25
VO
UT
26
VO
UT
27
VO
UT
28
NC
2929
NC
(SW
)30
30
NC
(SW
)31
31
PG
ND
32
PG
ND
33
PG
ND
34
PG
ND
35
PG
ND
36
PG
ND
37
S_IN56
BGND55
VDDB54
NC5353
NC5252
PVIN51
PVIN50
PVIN49
PVIN48
PVIN47
PVIN46
PVIN45
PVIN44
PVIN43
NC
7676
NC
7575
NC
7474
NC
7373
NC
7272
NC
(SW
)71
71
NC
(SW
)70
70
EN
_PB
69
FQAD
J68
NC
(XR
EF)
67
VS
EN
SE
66
SS
65
EA
OU
T64
VFB
63
M/S
62
AG
ND
61
AV
IN60
EN
AB
LE59
POK
58
PG
ND
38S
_OU
T57
PVIN42
PVIN41
PVIN40
PVIN39
NC1515
NC1616
NC1717
NC1818
GN
D_P
AD
77
R110 10K
R109 10K
C427 47uF
R511 10K
R4930
R5100
R506100
TP19
C426 47uF
R505
3.57k
R4252
0.00025
C4180.22uF
R512 DNI
C457
0.22uF
R496100
C661uF
C453 15nF
R48949.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B61 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B61 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B61 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V2SET
1V5SET
1V35SET
3A
1.5A
3.3V to HPS HILO VDD converter
HILOHPS_VDDOUT
PIEN
HILOHPS_VDD24,74,77
HILOHPS_VDDPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOHPSSENSP73
HILOHPSSENSN73
HILOHPSDAC_P 73
HILOHPSDAC_N 73
HILOHPS_1V2_SETn24
HILOHPS_1V35_SETn24
HILOHPS_1V5_SETn24
A10_HPSVDDI_P71
A10_HPSVDDI_N71
HILOHPS_VDD
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B62 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B62 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B62 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R462160k
R425
240K
TP51
C41422pF
R91100
R4330
R451 10K
R87100
C3510.22uF
C56
0.22uF
TP56
R4630
R442
5.49k
R88
DNI
R436191K
R426
390K
R89
DNI
TP50
TP54
C375 15nF
R45615k
R450 DNI
C365 47uF
R4410
C352 22uF
C353 22uF
R95 10K
TP57
R96 10K
C366 47uF
R431
976K
C581uF
TP55
R5131
100k
U52EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R94
0.001
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
4A
1.7A
3.3V to HILO VDD converter
1V3SET
PGEN
HILO_VDDOUTHILO_VDD34
HILO_VDDPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOVDDSENSP73
HILOVDDSENSN73
HILOVDDDAC_P 73
HILOVDDDAC_N 73
HILO_1V25_SETn34
HILO_1V2_SETn34
HILO_1V5_SETn34
HILO_1V35_SETn34
HILO_1V8_SETn34
HILO_1V30_SETn34
A10_HLVDDI_P71
A10_HLVDDI_N71
HILO_VDD
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B63 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B63 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B63 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R145 10K
R155
0.001
U63EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R6390
C709 15nF
R5160
487K
TP76
R130
DNI
R622
137K
R623
240K
R129
DNI
TP70
R624
390K
R638191K
R626
976K
R635 10K
C765 47uF
R5169
100k
R163100
C7320.22uF
C766 22uF
R636 DNI
R154100 R63415k
TP71
C755 47uF
R6370
C97
0.22uF
R648
5.49k
R647160k
TP75
TP82
C756 22uF
R144 10K
R6490
C861uF
C72522pF
R627
649K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
3A
1.5A
3.3V to HILO VDDQ converter
A single through-holevia/test point connects AGND pin to the GND plane.
1V3SET
HILO_VDDQOUTHILO_VDDQ34,74,77
HILO_VDDQPGood 35
IO_EN 35,73
A10_Main_3V3 55
HILOVDDQSENSP73
HILOVDDQSENSN73
HILOVDDQDAC_P 73
HILOVDDQDAC_N 73
HILOQ_1V2_SETn34
HILOQ_1V25_SETn34
HILOQ_1V30_SETn34
HILOQ_1V35_SETn34
HILOQ_1V5_SETn34
HILOQ_1V8_SETn34
A10_HLVDDQI_P71
A10_HLVDDQI_N71
HILO_VDDQ
A10_Main_3V3
A10_Main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B64 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B64 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B64 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R559
100k
C492 15nF
U59EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
TP18
R557191K
C529 47uF
TP21
C4950.22uF
TP20
R5580
C530 22uF
R526
649K
R119100
R118100
R111 10K
TP17
R108
DNI
R527
976K
C70
0.22uF
C681uF
R107
DNI
R553 10K
TP16
R530
240K
R112 10K
R551160k
R114
0.001
TP22
R528
390K
C49422pF
R554 DNI
R55215k
R531
137K
R555
5.49k
C564 47uF
R5680
C565 22uF
R5560R529
487K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3A
0.02A
3A
0.02A
FMC 3.3V PMOS SwitchesFMCB_3V3 72
FMCB_aux3V3 18
FMCA_3V3 72
FMCA_aux3V3 17
FMCA_EN35
FMCB_EN35
FMCA_AUXEN35
FMCB_AUXEN35
3V335,42,51
3V3
3V3
3V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B65 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B65 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B65 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Q13
DMG2305UX
S
D
G
R1410
Q3
SiSS23DN
1
567
4
8
23
Q17
DMG2305UX
S
D
G
R110
C1771uF
R610
TP4
Q1
SiSS23DN
1
567
4
8
23
R2100K
TP3
TP5R2310
TP10
TP2
Q16
DMG2305UX
S
D
G
TP1
C1871uF
R24100K
Q14
DMG2305UX
S
D
G
R410
Q4
SiSS23DN
1
567
4
8
23
R5100K
TP8
C1781uF
R1910
TP6
R25100K
C1861uF
R310
R1810
Q2
SiSS23DN
1
567
4
8
23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
6A3A
3.3V to FMC A VADJ converter
PJE
A
FMCAVADJOUT
PJEN
FMCAVADJ17,36,74,77
FMCAVADJPGood 35
A10_main_3V3 55
FMADAC_P 73
FMADAC_N 73
FMASENSP73
FMASENSN73
FMAVADJI_P71
FMAVADJI_N71
FMCA_EN 35
FMCAVADJA10_main_3V3
A10_main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B66 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B66 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B66 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R777
5.49k
C896 22uF
R811
137K
R7980
R261
DNI
C883 47uF
R76015k
R260
DNI
TP112R7870
R799
390K
R788
976K
R761 10KC880 15nF
U70EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R805
240K
TP115
C86322pF
C1641uF
TP111
R752160k
R243 10K
R797191K
C9000.22uF
R234 10K
TP110
C895 22uF
C884 47uF
R244
0.001
R256100
TP116J42
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
R257100
R789
649K
C167
0.22uF
R778 DNI
TP108
R7510
R804
100k
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
0402
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V25SET
1V2SET
1V5SET
1V35SET
1V8SET
4A
2A
3.3V to FMC B VADJ converter
FMCBVADJOUT
PKEN
FMCBVADJ18,36,74,77
FMCBVADJPGood 35
A10_main_3V3 55
FMBDAC_P 73
FMBDAC_N 73
FMBSENSP73
FMBSENSN73
FMBVADJI_P71
FMBVADJI_N71
FMCB_EN 35
FMCBVADJ
A10_main_3V3
A10_main_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B67 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B67 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B67 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C829 47uF
TP107
C844 22uF
TP99
J32
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
C828 47uF
R200100
TP31
R215
DNI
R206100
C817 15nF
R720
137K
C1191uF
R205
DNI
C128
0.22uF
R739191K
R193 10K
C8450.22uF
R72515k
R730 DNI
R192 10K
R7460
TP98
C843 22uF
C80022pF
R194
0.001
R718
390K
U69EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC
1515
VO
UT
16
VO
UT
17
VO
UT
18
VO
UT
19
VO
UT
20
VO
UT
21
VO
UT
22
VO
UT
23
VO
UT
24
NC
2525
NC
(SW
)26
26
NC
(SW
)27
27
PG
ND
28
PG
ND
29
PG
ND
30
PG
ND
31
PG
ND
32
PG
ND
33
S_IN48
BGND47
VDDB46
NC4545
NC4444
PVIN43
PVIN42
PVIN41
PVIN40
PVIN39
PVIN38
PVIN37
PVIN36
PVIN35
NC
6868
NC
6767
NC
6666
NC
6565
NC
6464
NC
(SW
)63
63
NC
(SW
)62
62
EN
_PB
61
FQAD
J60
NC
5959
VS
EN
SE
58
SS
57
EA
OU
T56
VFB
55
M/S
54
AG
ND
53
AV
IN52
EN
AB
LE51
POK
50
PG
ND
34S
_OU
T49
GN
D_P
AD
69
R733
5.49k
R717
649K
R729 10K
R719
240K
R716
976K
R747
100k
R7400
R726160k
TP106
R7240
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1A 1A
5A 5A
4A 4A
2.5V and 1.8V IO SwitchesIO_2V5 11,12,16,22,24,27,34,39,41,45
IO_EN35,73
IO_1V8
15,20,21,22,23,25,27,39,40,42,74,77
PLL_1V8 70,74,77
A10_1V8_EN35,73
2V535,53
A10_main_1V855
MAIN_12V49
2V5
PLL_1V8
A10_main_1V8
A10_main_1V8
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B68 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B68 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B68 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R531510K
TP47
R551010K
Q19
DMG2305UX
S
D
G
Q26MMBT2222A-7-F
CE
BQ7SiRA00DP
1567
4
8
23
TP53
R179100K
R38110
TP52
Q25MMBT2222A-7-F
CE
B
C3061uF
Q11MMBT2222A-7-F
CE
B
TP27
TP28
Q33MMBT2222A-7-F
CE
B
R455100K
R37110
R1841.00k
R44910K
R550910K
R45410K
C105
0.01uF
R36249.9K
R18510K
R1811.00k
Q20
SiSS23DN
1
567
4
8
23
C7900.01uF
Q24SiRA00DP
1567
4
8
23
TP46
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3A
0.375A
3A3A
0.3A
3.3V IO SwitchesPCIE_3V3 72
PCIE_aux3V3 10
PCIE_EN35
PCIE_auxEN35
IO_3V3
13,14,15,20,22,23,24,25,26,27,33,34,39,41,42,45,70
IO_EN35,73
LT_3V3 45,71,73
3V335,42,51
3V3
3V3
LT_3V3
3V3
3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B69 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B69 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B69 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Q22
DMG2305UX
S
D
G
TP11
Q15
DMG2305UX
S
D
G
C2161uF
TP12
C3271uFC185
1uF
R4610
R317
0.01
TP13
TP14
R39349.9K
R3110
R40010R20
10
TP9
R30100K
R26100K
TP7
TP49
Q6
SiSS23DN
1
567
4
8
23
Q23
SiSS23DN
1
567
4
8
23Q5
SiSS23DN
1
567
4
8
23
R1510
TP48
R40310
Q18
DMG2305UX
S
D
G
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
50us Discharge time
3.3V and 1.8V Discharge Load
DS3v3Current DS1V8Current
IO3V3_discharge35
IO_3V369
PLL1V8_discharge35
PLL_1V868
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B70 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B70 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B70 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
drain-tabQ32
RJK0301DPB
4
5
31 2
drain-tabQ21
RJK0301DPB
4
5
31 2
R7340.5
R3630.5
R391
10
R727
10
R39210K
R73110K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
RefVoltage = 0.3V
I2C Address = b'0010100'
RefVoltage = 0.3V
I2C Address = b'0010110'
I2C Current ADC (A)
LTSDALTSCL
LTREFP
LTSCLLTSDA
LT_3V369
LTSDA45LTSCL45
PCIE3V3I_P 72PCIE3V3I_N 72FMA3V3I_P 72FMA3V3I_N 72FMB3V3I_P 72FMB3V3I_N 72FMAVADJI_P 66FMAVADJI_N 66FMBVADJI_P 67FMBVADJI_N 67
2V5 35,53
3V3 35,42,51
IO_5V 50
A10_HPS0V95I_P 59A10_HPS0V95I_N 59
A10_0V95I_P 58A10_0V95I_N 58
A10_1V0I_P 60A10_1V0I_N 60
A10_1V8I_P 54A10_1V8I_N 54
A10_HPSVDDI_P 62A10_HPSVDDI_N 62
A10_HLVDDQI_P 64A10_HLVDDQI_N 64
A10_HLVDDI_P 63A10_HLVDDI_N 63
2V5I_P 532V5I_N 53
LT_3V3
LT_3V3
LT_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B71 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B71 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B71 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R52851.00k
R330100
0402
U38
LTC2497
CN08
CN19
CN210
CN311
CH412
CH513
CH614
CH715
CH816
CH917
CH1018
CH1119
CH1220
CH1321
CH1422
CH1523
GND131
GND232
GND333
GND434
GND539
GND61
GND74
GND86
COM7
NC5
SCL2 SDA3
MUXOUTP24 MUXOUTN27
ADCINN26
ADCINP25
VCC28
REFN30
REFP29
CA036 CA137 CA238
f035
R52861.00kC240
10uF
C239
0.1uF
C241
10uF
C19220pF
U40
LTC2497
CN08
CN19
CN210
CN311
CH412
CH513
CH614
CH715
CH816
CH917
CH1018
CH1119
CH1220
CH1321
CH1422
CH1523
GND131
GND232
GND333
GND434
GND539
GND61
GND74
GND86
COM7
NC5
SCL2 SDA3
MUXOUTP24 MUXOUTN27
ADCINN26
ADCINP25
VCC28
REFN30
REFP29
CA036 CA137 CA238
f035
R33949.9K
R33849.9K
C226220pF
R33749.9K
R52831.00k
C17
0.1uF
R52991.00k
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
User DC card 3.3V Current Sensors
PCIE3V3I_P71PCIE3V3I_N71
PCIE_DC_3V3 10
PCIE_3V3 69
FMA3V3I_P71FMA3V3I_N71
FMCA_DC_3V3 17
FMCA_3V3 65
FMB3V3I_P71FMB3V3I_N71
FMCB_DC_3V3 18,36
FMCB_3V3 65
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B72 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B72 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B72 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R3160.01C11
1uF
C4791uF
R32 10K
R5240.01
R47 10K
C8331uF
R523 10K
R7430.01
R507 10K
R742 10K
R741 10K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
I2C Address = b'1011100'
I2C Power ADC, DAC Controller
LT_3V3 69
A10_12V55
A10_0V95_EN 58,59
A10_1V8_EN 68IO_EN 62,63,64,68,69
A10_0V95DAC_P 59A10_0V95DAC_N 59A10_1V0DAC_P 60A10_1V0DAC_N 601V8DAC_P 541V8DAC_N 54FMADAC_P 66FMADAC_N 66FMBDAC_P 67FMBDAC_N 67
A10_0V95SENSP59A10_0V95SENSN59A10_1V0SENSP60A10_1V0SENSN601V8SENSP541V8SENSN54FMASENSP66FMASENSN66FMBSENSP67FMBSENSN67HILOHPSSENSP62HILOHPSSENSN62HILOVDDSENSP63HILOVDDSENSN63
HILOVDDQSENSP64HILOVDDQSENSN64
LTCNTRL035LTCNTRL135LTWDI_RESETN35LTFAUL035
LTPWRGD 35
HILOHPSDAC_P 62HILOHPSDAC_N 62HILOVDDDAC_P 63HILOVDDDAC_N 63HILOVDDQDAC_P 64HILOVDDQDAC_N 64
PMbus_SDA_3V327,45,51,56PMbus_SCL_3V327,45,51,56
PMbus_ALTERTn 35,45,51,56
A10_1V0_EN 60
LT_3V3
A10_12V
LT_3V3
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B73 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B73 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B73 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R285 DNI
R300 10K R288 DNI
R279 10K
R10 10KR283 10KR12 10K
R301 10K
R284 10K
C3
0.1uF
R13 10K
R291 10K
C1
0.1uF
R280 5.49K
R295 10K
C2
0.1uF
C194
0.1uF
U35
LTC2977
VOUT_EN48
VOUT_EN59
VOUT_EN610
VOUT_EN711
VIN_EN12
NC13
VIN_SNS14
VPWR15
VDD33_OUT16
VDD33_IN17
VDD2518WP
19 PWRGD20SHARE_CLK
21
WDI/RESET22
FAULTB0023
FAULTB0124
FAULTB1025
FAULTB1126
SDA27 SCL28
ALERTB29
CONTROL030
CONTROL131
ASEL032
ASEL133
REFP34
REFM35VSENSEP0
36
VSENSEM037
VDACM038VDACP039
VDACP140
VDACM141
VSENSEP142
VSENSEM143
VDACP244
VDACM245
VSENSEP246
VSENSEM247
VSENSEP348
VSENSEM349
VDACP350
VDACM351
VSENSEP452
VSENSEM61
VSENSEP72
VSENSEM73
VOUT_EN04
VOUT_EN15
VOUT_EN26
VOUT_EN37
VSENSEM453
VDACM454VDACP455
VDACP556
VDACM557
VDACM658VDACP659
VDACP760
VDACM761
VSENSEP562
VSENSEM563
VSENSEP664
E-PAD65
R287 DNI
R296 10KR299 10K R281 10K
R286 DNIR290 10K
R9 10K
R282 10K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Power Inputs
3A
2A
1.8A
VREFB2AVREFB2IVREFB2JVREFB2K
VREFB3AVREFB3BVREFB3CVREFB3D
VREFB3EVREFB3FVREFB3GVREFB3H
VREFB2L
FMCAVADJ 66
A10_VCCAPLL77
A10VCCPLLHPS 77
A10_VCCLSENSE 56A10_GNDSENSE 56
HILOHPS_VDD 62
IO_1V8 36,37,68
FMCBVADJ 67
HILO_VDDQ 64
PLL_1V868
A10_1V060
A10_0V9 56
HPS_0V95 59
0V9558
VCCIO_HPS 77VCCIOREF_HPS 77
IO_1V8
FMCAVADJ
IO_1V8
IO_1V8
IO_1V8
IO_1V8
HILOHPS_VDD
FMCBVADJ
HILO_VDDQ
HILOHPS_VDD FMCBVADJ
HILO_VDDQ
PLL_1V8
PLL_1V8
PLL_1V8
IO_1V8 FMCAVADJ
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B74 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B74 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B74 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
R619 240
C566
0.1uFR538 DNI
R618 240
R536 DNI
R600 240
R519 240
R580 240
C644
0.1uF
R592 240
R591 240
R521 240
R599 240
A10SOC_1517
U23Q
VCCAF21
VCCAF22
VCCP21
VCCP23
VCCR12
VCCR13
VCCR14
VCCR15
VCCR16
VCCR17
VCCR20
VCCR21
VCCR22
VCCR23
VCCR25
VCCT12
VCCT13
VCCT18
VCCT22
VCCT25
VCCU12
VCCU14
VCCU19
VCCU24
VCCU25
VCCU26
VCCV12
VCCV13
VCCV14
VCCV16
VCCV17
VCCV18
VCCV19
VCCV21
VCCV22
VCCV23
VCCV24
VCCW13
VCCW14
VCCW20
VCCW21
VCCW23
VCCW24
VCCW25
VCCY14
VCCY16
VCCAA12
VCCAA13
VCCAA14
VCCAA15
VCCAA16
VCCAA20
VCCAA22
VCCAA23
VCCAA24
VCCAA25
VCCAB12
VCCAB15
VCCAB16
VCCAB17
VCCAB19
VCCAB20
VCCAB21
VCCAB22
VCCAB24
VCCAB25
VCCAC12
VCCAC13
VCCAC18
VCCAC23
VCCAC24
VCCAC26
VCCAD13
VCCAD17
VCCAD18
VCCAD19
VCCAD21
VCCAD22
VCCAD23
VCCAE12
VCCAE13
VCCAE14
VCCAE15
VCCAE16
VCCAE17
VCCAE21
VCCAE22
VCCAE25
VCCY17
VCCY20
VCCY25
R616 240
R520 240
C719
0.1uF
R581 240
R674
100KR617 240
C720
0.1uF
R644 240
R645 240
C524
0.1uF
R630 240
R535 240C522
0.1uF
R646 DNI
C675
0.1uF
C523
0.1uF
R678 240
C521
0.1uF
R518 240
A10SOC_1517
U23Y
VC
CP
AD
14V
CC
PA
D15
VC
CP
AD
16V
CC
PA
D20
VC
CP
AD
24V
CC
PA
D25
VC
CP
T14
VC
CP
T15
VC
CP
T17
VC
CP
T19
VC
CP
T20
VC
CP
T23
VC
CP
T24
VC
CA
_PLL
W18
VC
CA
_PLL
W19
VC
CB
AT
AE
18
VCCH_GXBLAD27
VCCH_GXBLAH27
VCCH_GXBLAM27
VCCH_GXBLD27
VCCH_GXBLH27
VCCH_GXBLM27
VCCH_GXBLT27
VCCH_GXBLY27
VCCR_GXBL1CAP28
VCCR_GXBL1CAP29
VCCR_GXBL1DAK28
VCCR_GXBL1DAK29
VCCR_GXBL1EAF28
VCCR_GXBL1EAF29
VCCR_GXBL1FAB28
VCCR_GXBL1FAB29
VCCR_GXBL1GV28
VCCR_GXBL1GV29
VCCR_GXBL1HP28
VCCR_GXBL1HP29
VCCR_GXBL1IK28
VCCR_GXBL1IK29
VCCR_GXBL1JF28
VCCR_GXBL1JF29
VC
CE
RA
MY
12
VC
CE
RA
MY
13
VC
CE
RA
MY
18
VC
CE
RA
MY
21
VC
CE
RA
MY
22
VC
CE
RA
MY
23
VCCT_GXBL1CAM28 VCCT_GXBL1CAM29 VCCT_GXBL1DAH28 VCCT_GXBL1DAH29 VCCT_GXBL1EAD28 VCCT_GXBL1EAD29 VCCT_GXBL1F
Y28 VCCT_GXBL1FY29 VCCT_GXBL1GT28 VCCT_GXBL1GT29 VCCT_GXBL1HM28 VCCT_GXBL1HM29 VCCT_GXBL1IH28 VCCT_GXBL1IH29 VCCT_GXBL1JD28 VCCT_GXBL1JD29
VC
CIO
RE
F_H
PS
N16
VC
CIO
_HP
SM
16
VC
CLS
EN
SE
AA
19
VC
CL_
HP
SN
17
VC
CL_
HP
SP
16
VC
CL_
HP
SP
18
VC
CL_
HP
SR
18
VCCIO2AAK19
VCCIO2AAM18
VCCIO2AAP17
VCCIO2IAL21
VCCIO2IAP22
VCCIO2IAT21
VCCIO2JAK24
VCCIO2JAN25
VCCIO2JAR24
VCCIO2KE24
VCCIO2KH25
VCCIO2KK24
VCCIO2LH20
VCCIO2LJ22
VCCIO2LK19
VCCIO3AAK14
VCCIO3AAL11
VCCIO3AAM13
VCCIO3BAK9
VCCIO3BAL6
VCCIO3BAM8
VCCIO3CAD7
VCCIO3CAG8
VCCIO3CAH5
VCCIO3DAA6
VCCIO3DAC5
VCCIO3DY4
VCCIO3ER4
VCCIO3ET6
VCCIO3EV5
VCCIO3FK4
VCCIO3FL6
VCCIO3FM8
VCCIO3GG8
VCCIO3GK9
VCCIO3GL11
VCCIO3HG13
VCCIO3HJ12
VCCIO3HK14
VC
CP
GM
AF1
8V
CC
PG
MA
F19
VC
CP
LL_H
PS
N18
VC
CP
TA
B14
VC
CP
TA
C14
VC
CP
TA
C16
VC
CP
TA
C17
VC
CP
TA
C19
VC
CP
TA
C21
VC
CP
TU
15V
CC
PT
U16
VC
CP
TU
17V
CC
PT
U20
VC
CP
TU
21V
CC
PT
U22
VR
EFB
2AN
0A
G19
VR
EFB
2IN
0A
E23
VR
EFB
2JN
0A
F23
VR
EFB
2KN
0P
24V
RE
FB2L
N0
P22
VR
EFB
3AN
0A
H16
VR
EFB
3BN
0A
F13
VR
EFB
3CN
0A
D11
VR
EFB
3DN
0Y
11V
RE
FB3E
N0
W11
VR
EFB
3FN
0T1
0V
RE
FB3G
N0
P13
VR
EFB
3HN
0M
15V
RE
FN_A
DC
D15
VR
EFP
_AD
CD
16
GN
DS
EN
SE
AA
18
C554
0.1uF
R672 240
C673
0.1uF
C741
0.1uF
R643 240
R631 240
C567
0.1uFR537 240
D40
LT1389
GND4
VOUT6
GND5
NC11
NC22
NC33
NC77
NC88
C711
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Ground Connections
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B75 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B75 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B75 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
A10SOC_1517
U23T
GN
DA
W38
GN
DA
W7
GN
DB
13
GN
DB
18
GN
DB
2
GN
DB
23
GN
DB
25
GN
DB
27
GN
DB
28
GN
DB
29
GN
DB
3
GN
DB
32
GN
DB
33
GN
DB
36
GN
DB
37
GN
DB
8
GN
DC
10
GN
DC
15
GN
DC
20
GN
DC
27
GN
DC
28
GN
DC
29
GN
DC
30
GN
DC
31
GN
DC
34
GN
DC
35
GN
DC
38
GN
DC
39
GN
DC
5
GN
DD
12
GN
DD
17
GN
DD
2
GN
DD
22
GN
DD
26
GN
DD
32
GN
DD
33
GN
DD
36
GN
DD
37
GNDD7
GNDE14
GNDE19
GNDE27
GNDE30
GNDE31
GNDE34
GNDE35
GNDE38
GNDE39
GNDE4
GNDE9
GNDF1
GNDF11
GNDF16
GNDF21
GNDF27
GNDF32
GNDF33
GNDF36
GNDF37
GNDF6
GNDG18
GNDG23
GNDG27
GNDG3
GNDG30
GNDG31
GNDG34
GNDG35
GNDG38
GNDG39
GNDH10
GNDH15
GNDH26
GNDH32
GNDH33
GNDH36
GNDH37
GNDH5
GNDJ17
GNDJ2
GNDJ27
GNDJ30
GNDJ31
GNDJ34
GNDJ35
GNDJ38
GNDJ39
GNDJ7
GNDK27
GNDK32
GNDK33
GNDK36
GNDK37
GNDL1
GNDL16
GNDL21
GNDL27
GNDL30
GNDL31
GNDL34
GN
DL3
5
GN
DL3
8
GN
DL3
9
GN
DM
13
GN
DM
18
GN
DM
23
GN
DM
26
GN
DM
3
GN
DM
32
GN
DM
33
GN
DM
36
GN
DM
37
GN
DN
10
GN
DN
15
GN
DN
21
GN
DN
26
GN
DN
27
GN
DN
30
GN
DN
31
GN
DN
34
GN
DN
35
GN
DN
38
GN
DN
39
GN
DN
5
GN
DP
12
GN
DP
17
GN
DP
2
GN
DP
26
GN
DP
27
GN
DP
32
GN
DP
33
GN
DP
36
GN
DP
37
GN
DP
7
GN
DR
19
GN
DR
24
GNDR26
GNDR27
GNDR30
GNDR31
GNDR34
GNDR35
GNDR38
GNDR39
GNDR9
GNDT1
GNDT11
GNDT16
GNDT21
GNDT26
GNDT32
GNDT33
GNDT36
GNDT37
GNDU13
GNDU18
GNDU23
GNDU27
GNDU3
GNDU30
GNDU31
GNDU34
GNDU35
GNDU38
GNDU39
GNDU8
GNDV10
GNDV15
GNDV20
GNDV25
GNDV26
GNDV27
GNDV32
GNDV33
GNDV36
GNDV37
GNDW12
GNDW17
GNDW2
GNDW22
GNDW26
GNDW27
GNDW30
GNDW31
GNDW34
GNDW35
GNDW38
GNDW39
GNDW7
GNDY15
GNDY19
GNDY24
GNDY26
GNDY32
GNDY33
GNDY36
GNDY37
GNDY9
ADCGNDB17
A10SOC_1517
U23Z
GN
DA
R15
GN
DA
P14
GN
DA
11G
ND
A16
GN
DA
21G
ND
A27
GN
DA
29G
ND
A30
GN
DA
31G
ND
A34
GNDA35
GNDA38
GNDA6
GNDAA1
GNDAA11
GNDAA17
GNDAA21
GNDAA26
GNDAA27
GNDAA30
GNDAA31
GNDAA34
GNDAA35
GNDAA38
GNDAA39
GNDAB13
GNDAB18
GNDAB23
GNDAB26
GNDAB27
GNDAB3
GNDAB32
GNDAB33
GNDAB36
GNDAB37
GNDAB8
GNDAC10
GNDAC15
GNDAC20
GNDAC22
GNDAC25
GNDAC27
GNDAC30
GNDAC31
GNDAC34
GNDAC35
GNDAC38
GNDAC39
GNDAD12
GNDAD2
GNDAD26
GNDAD32
GNDAD33
GNDAD36
GNDAD37
GNDAE19
GNDAE24
GNDAE26
GNDAE27
GNDAE30
GNDAE31
GNDAE34
GNDAE35
GNDAE38
GNDAE39
GNDAE4
GNDAE9
GNDAF1
GNDAF11
GN
DA
F16
GN
DA
F26
GN
DA
F27
GN
DA
F32
GN
DA
F33
GN
DA
F36
GN
DA
F37
GN
DA
F6
GN
DA
G13
GN
DA
G18
GN
DA
G23
GN
DA
G26
GN
DA
G27
GN
DAG
3
GN
DA
G30
GN
DA
G31
GN
DA
G34
GN
DA
G35
GN
DA
G38
GN
DA
G39
GN
DA
H10
GN
DA
H15
GN
DA
H20
GN
DA
H26
GN
DA
H32
GN
DA
H33
GN
DA
H36
GN
DA
H37
GN
DA
J12
GN
DA
J17
GN
DA
J2
GN
DA
J22
GN
DA
J27
GN
DA
J30
GN
DA
J31
GN
DA
J34
GN
DA
J35
GN
DA
J38
GN
DA
J39
GN
DA
J7
GN
DA
K27
GN
DA
K32
GN
DA
K33
GN
DA
K36
GN
DA
K37
GN
DA
K4
GN
DA
L1
GN
DA
L16
GN
DA
L27
GN
DA
L30
GN
DA
L31
GN
DA
L34
GN
DA
L35
GN
DA
L38
GN
DA
L39
GN
DA
M23
GN
DA
M26
GN
DA
M3
GN
DA
M32
GN
DA
M33
GN
DA
M36
GN
DA
M37
GN
DA
N10
GNDAN15
GNDAN20
GNDAN27
GNDAN30
GNDAN31
GNDAN34
GNDAN35
GNDAN38
GNDAN39
GNDAN5
GNDAP12
GNDAP2
GNDAP27
GNDAP32
GNDAP33
GNDAP36
GNDAP37
GNDAP7
GNDAR14
GNDAR19
GNDAR27
GNDAR30
GNDAR31
GNDAR34
GNDAR35
GNDAR38
GNDAR39
GNDAR4
GNDAR9
GNDAT1
GNDAT11
GNDAT16
GNDAT27
GNDAT28
GNDAT29
GNDAT32
GNDAT33
GNDAT36
GNDAT37
GNDAT6
GNDAU13
GNDAU18
GNDAU23
GNDAU29
GNDAU3
GNDAU30
GNDAU31
GNDAU34
GNDAU35
GNDAU38
GNDAU39
GNDAU8
GNDAV10
GNDAV15
GNDAV20
GNDAV25
GNDAV31
GNDAV32
GNDAV33
GN
DA
V36
GN
DA
V37
GN
DA
V5
GN
DA
W12
GN
DA
W17
GN
DA
W22
GN
DA
W27
GN
DA
W29
GN
DA
W31
GN
DA
W34
GN
DA
W35
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
0.95V HPS is for boost mode
0.9V Decoupling 0.95V HPS VCCL
Core Power Decoupling
Only install for supporting NF5 FPGA
3A
U23. pin R23, R21, Ae14,Ae13,U19,AD16
A10_0V956
0V9558
HPS_0V9559
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B76 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B76 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B76 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C618
0.1uF
C714
0.1uF
C677
0.1uF
C541
0.1uF
C5720.1uF
C6540.1uF
C5520.1uF
C629
0.1uF
C15910.1uF
C539
0.1uF
C493
100uF6.3V
C585
0.1uF
C582
0.1uF
C696
0.1uF
C624
0.1uF
C5700.1uF
C689
0.1uF
C701
0.1uF
C5500.1uF
C768
100uF6.3V
C664
0.1uF
C535
0.1uF
C688
0.1uF
C627
0.1uF
C569
0.1uF
C580
0.1uF
C501
100uF6.3V
C690
0.1uF
C603
0.1uF
C15920.1uF
C5510.1uF
C663
0.1uF
C6580.1uF
C681
0.1uF
C475
100uF6.3V
C623
0.1uF
C648
0.1uF
C608
0.1uFC6600.1uF
C687
0.1uF
C586
0.1uF
C5490.1uF
C536
0.1uF
C476
100uF6.3V
C700
0.1uF
C589
0.1uF
C647
0.1uF
C15930.1uF
C583
0.1uF
C641
100uF6.3V
C5480.1uF
C542
0.1uF
C679
0.1uF
C769
100uF6.3V
C630
0.1uF
R663DNI
C540
0.1uF
C6070.1uF
C649
0.1uF
C477
100uF6.3V
C6120.1uF
C631
0.1uF
C15940.1uF
C621
0.1uF
C699
0.1uF
C579
0.1uF
C622
0.1uF
C698
0.1uF
C726
100uF6.3V
C661
0.1uF
C685
0.1uF
C6110.1uF
C625
0.1uF
C747
100uF6.3V
C6520.1uF
C5530.1uF
C15950.1uF
C651
0.1uF
C568
0.1uF
C693
0.1uF
C5750.1uF
C606
0.1uF
C594
100uF6.3V
C771
100uF6.3V
C680
0.1uF
C692
0.1uF
C6050.1uF
C678
0.1uF
C695
0.1uF
C609
0.1uF
C615
0.1uF
C15960.1uF
C613
0.1uF
C555
0.1uF
C5740.1uF
C610
0.1uF
C544
0.1uF
C6830.1uF
C662
0.1uF
C655
0.1uF
C619
0.1uF
C576
0.1uF
C665
0.1uF
C538
0.1uF
C588
0.1uF
C604
0.1uF
C5780.1uF
C620
0.1uF
C7641uF
C628
0.1uF
C668
100uF6.3V
C778
100uF6.3V
C646
0.1uF
C537
0.1uF
C505
100uF6.3V
C684
0.1uF
C626
0.1uF
C584
0.1uF
C556
0.1uF
C614
0.1uF
C682
0.1uF
C694
0.1uF
C474
100uF6.3V
C686
0.1uF
C676
0.1uF
C5470.1uF
C528
100uF6.3V
C697
0.1uF
C691
0.1uF
C587
0.1uF
C770
100uF6.3V
C5900.1uF
C645
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
IO Power Decoupling
0.1A
0.1A
4A
Only install for supporting NF5 FPGA
Only install for supporting NF5 FPGA
Only install for supporting NF5 FPGA
0.1A
0.1A
PLL_1V868
A10_VCCAPLL 74
A10VCCPLLHPS 74
FMCBVADJ67
HILOHPS_VDD62
HILO_VDDQ64
FMCAVADJ66
IO_1V836,37,68
A10_1V060
VCCIO_HPS 74
VCCIOREF_HPS 74
PLL_1V8
IO_1V8
PLL_1V8
A10_VCCAPLL
A10VCCAPLLHPS
A10_VCCAPLL
A10VCCAPLLHPS
A10_1V0
IO_1V8
PLL_1V8
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B77 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B77 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B77 78Thursday, March 31, 2016
150-0321308 (6XX-44382R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
C745
4.7uF
C500
4.7uF
C706
4.7uF
R664DNI
C761
0.1uF
C602
0.1uF
C717
0.1uF
L26
3A, 30 Ohm FB
C507
0.1uF
C571
0.1uF
C1579
0.1uF
C666
0.1uF
C762
0.1uF
C633
0.1uF
C718
4.7uF
C498
0.1uF
C591
0.1uF
C560
4.7uF
C519
0.1uF
C727
0.1uF
C509
4.7uF
C499
0.1uF
C1589
0.1uF
L27
3A, 30 Ohm FB
C558
0.1uF
R6750
C506
0.1uF
C1581
0.1uF
C656
0.1uF
C513
0.1uF
C515
0.1uF
C731
4.7uF
C733
0.1uF
C526
0.1uF
C744
0.1uF
C616
0.1uF
C545
0.1uF
C496
0.1uF
C497
0.1uF
R662DNI
C508
0.1uF
C1584
0.1uF
C738
4.7uF
C516
0.1uF
C1582
0.1uF
C488
0.1uF
C704
0.1uF
C728
0.1uF
C634
4.7uF
C1580
0.1uF
C1585
0.1uF
C712
0.1uF
C617
0.1uF
C642
0.1uF
C743
0.1uF
C730
0.1uF
C593
4.7uF
C489
0.1uF
C710
0.1uF
C1586
0.1uF
C643
0.1uF
C650
0.1uF
C487
0.1uF
C763
0.1uF
C736
0.1uF
C715
0.1uF
C1588
0.1uF
C734
0.1uF
C527
4.7uF
C546
0.1uF
C702
0.1uF
C486
0.1uF
C716
0.1uF
C581
0.1uF
C735
0.1uF R6730
C557
0.1uF
C517
4.7uF
C577
0.1uF
C667
4.7uF
C729
0.1uF
C657
0.1uF
C742
0.1uF
C703
0.1uF
R660DNI
C520
0.1uF
C713
0.1uF
C632
0.1uF
C1587
0.1uF
C510
330uF
C1590
0.1uF
C573
0.1uF
C653
0.1uF
C705
4.7uF
C534
0.1uF
C674
0.1uF
C746
4.7uF
C592
0.1uF
C1578
0.1uF
C559
4.7uF
C659
0.1uF
C543
0.1uF
C533
0.1uF
C561
100uF6.3V
C1583
0.1uF
C525
0.1uF
C737
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
THIS PAGE IS INTENTIONALLY LEFT BLANK
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B78 78Thursday, March 31, 2016
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B78 78Thursday, March 31, 2016
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet o f
C
Arria 10 SoC FPGA Development Kit Board
B78 78Thursday, March 31, 2016
150-0321304 (6XX-44294R)
Altera Corporation,101 innovation Dr, San Jose, CA 95134
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