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D D
C C
B B
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DESCRIPTIONREV DATE PAGESNOTES:
1516 Parts, 84 Library Parts, 1524 Nets, 7856 Pins Arria 10 FPGA Development Kit
1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
2.
100-0321301-E3110-0321301-E3120-0321301-E3130-0321301-E3140-0321301-E3150-0321301-E3160-0321301-E3170-0321301-E3180-0321301-E3210-0321301-E3220-0321301-E3320-0321301-E3
Clock Diagram
Arria 10 GX Bank 2Arria 10 GX Bank 3A-3DArria 10 GX Bank 3E-3HArria 10 ConfigurationArria 10 ClocksPLL
Arria 10 XCVR Left (B1)Arria 10 XCVR Right (B4)5M2210 System ControllerFlash10/100/1000 Ethernet PHYEMI Connector MapExternal Memory InterfaceDisplayPort (x4)FMC Port AFMC Port BQSFPSFP+SDI Transmit/ReceiveUser IOOn-Board USB Blaster II -1On-Board USB Blaster II -2Power Tree
PCI Express Edge Connector
Power - Select Power Input
DESCRIPTION
3130
3233
36
373839404142434445464748495051525354
3435
55565758
PAGE DESCRIPTION
5960616263
20
2827
56
29
21
34
7
98
1112
1413
1516
1817
19
10
2221
2324
2625
PAGE
64656667
Title, Notes, Block Diagram, Rev. History
68
PLL2
Voltage & Temperature Sense
Power - DCin to 3.3VPower - 3.3V & 5.0VPower - MEM_VDD & 2.5VPower1 - A10 VCC
Power2 - A10 VCCRAMPower2 - A10 VCCR GXBBlank PagePower3 - A10 VCCPT/1.8VPower4 - A10 VCCIO 1.8VPower4 - A10 VCCIO FMCAPower4 - A10 VCCIO FMCBPower4 - A10 VCCIO MEMArria 10 PowerArria 10 GroundDecoupling
Power1 A10 VCC ET4040 (1)
Power1 A10 VCC ET4040 (2)
Power Sequence Control
Power Sequence Diagram
Power-Down Discharge
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B1 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B1 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B1 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Clock Diagram
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B2 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B2 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B2 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Link Width DIP Switch
PCI Express Edge Connector
75-ohm to 100-ohm XCVR traces.
QDRIV needs 1.3V VDD. SW3.4 allows changing of1.35V to 1.3V for QDRIV.
PCIE_EDGE_SMBCLK
PCIE_PRSNT2n_x8
PCIE_PRSNT2n_x4
PCIE_EDGE_SMBDAT
PCIE_EDGE_WAKEn
PCIE_PRSNT2n_x1
PCIE_TX_CP6PCIE_TX_CN6
PCIE_TX_CP7PCIE_TX_CN7
PCIE_TX_CN5PCIE_TX_CP5
PCIE_TX_CN4PCIE_TX_CP4
PCIE_TX_CP2PCIE_TX_CN2
PCIE_EDGE_PERSTn
PCIE_TX_CP3PCIE_TX_CN3
PCIE_TX_CN1PCIE_TX_CP1
PCIE_TX_CP0PCIE_TX_CN0
PCIE_WAKEn_R3.3V_PCIE_AUX
PCIE_PRSNT1nPCIE_PRSNT2n_x4PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x8
PB_PERSTn
PB_PERSTn PCIE_3P3V_PERSTn
PCIE_3P3V_PERSTnPCIE_EDGE_SMBCLKPCIE_EDGE_SMBDATPCIE_EDGE_WAKEn
PCIE_TX_N0PCIE_TX_P0
PCIE_TX_P1PCIE_TX_N1
PCIE_TX_P2PCIE_TX_N2
PCIE_TX_P3PCIE_TX_N3
PCIE_TX_P4PCIE_TX_N4
PCIE_TX_P5PCIE_TX_N5
PCIE_TX_P6PCIE_TX_N6
PCIE_TX_P7PCIE_TX_N7
PCIE_RX_N0PCIE_RX_P0
PCIE_RX_N1PCIE_RX_P1
PCIE_RX_N2PCIE_RX_P2
PCIE_RX_N3PCIE_RX_P3
PCIE_RX_N4PCIE_RX_P4
PCIE_RX_N5PCIE_RX_P5
PCIE_RX_P6
PCIE_RX_N7PCIE_RX_P7
PCIE_RX_N6
12V_PCIE 3.3V_PCIE
12V_PCIE 3.3V_PCIE12V_PCIE3.3V_PCIE
3.3V
3.3V
1.8V
1.8V3.3V
PCIE_EDGE_REFCLK_P11PCIE_EDGE_REFCLK_N11
PCIE_PERSTn7
PCIE_WAKEn7
PCIE_SMBCLK7PCIE_SMBDAT4
PCIE_TX_N[7:0]11
PCIE_TX_P[7:0]11
PCIE_RX_N[7:0]11
PCIE_RX_P[7:0]11
VDD_1.35V_SET17,34VDD_1.3V_SET34
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B3 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B3 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B3 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C7190.22uF
C2550.1uF
S8
PB Switch1 2
C7110.22uF
C7130.22uF
C2570.1uF
C7160.22uF
C7230.1uF
C7090.22uF
C7250.1uF
OPEN
SW3
DIPSWITCH4
1234 5
678
R546 DNI
C2540.1uF
C7070.22uF
C706
0.1uF
C7210.22uF
C7080.22uF
KEY
X4
X8
X1
J22
PCIE_Slot
+12VB1
+12VB2
+12VB3
GNDB4
SMCLKB5
SMDATB6
GNDB7
+3_3VB8
JTAG_TRSTNB9
+3_3VAUXB10
WAKE_NB11
RSVD1B12
GNDB13
PET0PB14
PET0NB15
GNDB16
PRSNT2_N_X1B17
GNDB18
PET1PB19
PET1NB20
GNDB21
GNDB22
PET2PB23
PET2NB24
GNDB25
GNDB26
PET3PB27
PET3NB28
GNDB29
RSVD3B30
PRSNT2_N_X4B31
GNDB32
PET4PB33
PET4NB34
GNDB35
GNDB36
PET5PB37
PET5NB38
GNDB39
GNDB40
PET6PB41
PET6NB42
GNDB43
GNDB44
PET7PB45
PET7NB46
GNDB47
PRSNT2_N_X8B48
GNDB49
PRSNT1_NA1
+12VA2
+12VA3
GNDA4
JTAG_TCKA5
JTAG_TDIA6
JTAG_TDOA7
JTAG_TMSA8
+3_3VA9
+3_3VA10
PERST_NA11
GNDA12
REFCLK+A13
REFCLK-A14
GNDA15
PER0PA16
PER0NA17
GNDA18
RSVD2A19
GNDA20
PER1PA21
PER1NA22
GNDA23
GNDA24
PER2PA25
PER2NA26
GNDA27
GNDA28
PER3PA29
PER3NA30
GNDA31
RSVD4A32
RSVD5A33
GNDA34
PER4PA35
PER4NA36
GNDA37
GNDA38
PER5PA39
PER5NA40
GNDA41
GNDA42
PER6PA43
PER6NA44
GNDA45
GNDA46
PER7PA47
PER7NA48
GNDA49
R544 10.0K
C7140.22uF
C7180.22uF
C7100.22uF
C7150.22uF
C7240.1uF
R552 DNI
C7120.22uF
C693
0.1uF
C2580.1uF
C2560.1uF
C692
1uF
U74
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
C7170.22uF
C7220.22uF
A&B=Y
U75
SN74LVC1G08_6PIN
A1
B2
GND3
VCC6
NC5
Y4
C7200.22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 GX Bank 2
MEMORY INTERFACE
CLOCK INTERFACE
DISPLAYPORT INTERFACE
QSFP INTERFACE
SFP+ INTERFACE
SDI INTERFACEVCCIO = 1.8V
VARIABLE EMI VCCIO
(1.2V, 1.35V, 1.5V)
VARIABLE EMI VCCIO
(1.2V, 1.35V, 1.5V)
VARIABLE EMI VCCIO
(1.2V, 1.35V, 1.5V)
PCIe INTERFACE
QDR4 QKB_P1 ->
QDR4 QKB_P0 ->
ENABLE ARRIA 10 OCT ->
<- QDR4 QKA_P0
<- QDR4 QKA_P1
Stratix 5 RZQ100-ohm for 50-ohm RT or 25-ohm RS.
DP_CONFIG1DP_CONFIG2
PCIE_SMBDAT
MEM_DQB7
MEM_DQB8MEM_DQB9MEM_DQB10MEM_DQB11MEM_DQB12
SDI_MF1_AUTO_SLEEPSDI_MF0_BYPASS
SDI_TX_SD_HDnSDI_MF2_MUTE
MEM_DQB13
MEM_DQB14
MEM_DQB17MEM_DQB18
MEM_DQB21
MEM_DQB23
MEM_DQB24
MEM_DQB25MEM_DQB26
CLOCK_SCL
CLOCK_SDA
MEM_DQB27
MEM_DQB28MEM_DQB29
MEM_DQB30
MEM_DQB31
MEM_QKB_P1
MEM_DQB33
DP_HOT_PLUG
DP_RETURN
DP_AUX_CH_PDP_AUX_CH_N
DISP_SPISSDISP_I2C_SDA
DISP_I2C_SCL
MEM_DMB0
MEM_DMB3
MEM_DQB0
QSFP_LP_MODE
QSFP_MOD_PRSn
QSFP_INTERRUPTn
QSFP_SDA
QSFP_SCLQSFP_RSTn
QSFP_MOD_SELn
MEM_DQSB_P0MEM_DQSB_N0
MEM_QKB_P0
MEM_DQSB_P2MEM_DQSB_N2
MEM_DQSB_P3MEM_DQSB_N3
MEM_DQB1
RZQ_B2I
MEM_DQB2
SFP_TX_FAULTSFP_RS0
SFP_RS1
SFP_TX_DISABLE
SFP_MOD0_PRSNTn
SFP_RX_LOS
SFP_MOD1_SCL
SFP_MOD2_SDA
MEM_DQB3
MEM_DQB4
MEM_DQB5MEM_DQB6
MEM_DQA7
MEM_DQA8MEM_DQA9
MEM_DQA12MEM_DQA13
MEM_DQA14
MEM_DQA17MEM_DQA21
MEM_DQA23
MEM_DQA24
MEM_DQA25
MEM_DQA26
MEM_DQA27
MEM_DQA28
MEM_DQA29MEM_DQA30
MEM_DQA31
MEM_DQA33
MEM_DMA0
MEM_DQ_ADDR_CMD0
MEM_DQ_ADDR_CMD1
MEM_DQ_ADDR_CMD2
MEM_DQ_ADDR_CMD3MEM_DQ_ADDR_CMD4
MEM_DQ_ADDR_CMD5
MEM_DQ_ADDR_CMD6MEM_DQ_ADDR_CMD7
MEM_DQ_ADDR_CMD8
MEM_DMA1
MEM_DMA3
MEM_ADDR_CMD0
MEM_DQA0
MEM_CLK_PMEM_CLK_N
MEM_DQS_ADDR_CMD_PMEM_DQS_ADDR_CMD_N
MEM_ADDR_CMD1
MEM_ADDR_CMD2MEM_ADDR_CMD3
MEM_ADDR_CMD4MEM_ADDR_CMD5
MEM_ADDR_CMD8MEM_ADDR_CMD9
MEM_ADDR_CMD12
MEM_ADDR_CMD15MEM_ADDR_CMD16
MEM_ADDR_CMD17MEM_ADDR_CMD18MEM_ADDR_CMD19
MEM_ADDR_CMD20MEM_ADDR_CMD21MEM_ADDR_CMD22MEM_ADDR_CMD23
MEM_ADDR_CMD24MEM_ADDR_CMD25
MEM_ADDR_CMD26
MEM_ADDR_CMD27MEM_ADDR_CMD28
MEM_ADDR_CMD29
MEM_ADDR_CMD30MEM_ADDR_CMD31
MEM_DQSA_P0MEM_DQSA_N0
MEM_QKA_P0
MEM_QKA_P1
MEM_DQSA_N2MEM_DQSA_P2
MEM_DQSA_N3MEM_DQSA_P3
MEM_DQA1MEM_DQA2
MEM_DQA3MEM_DQA4MEM_DQA5
MEM_DQA6
MEM_DQB32
MEM_DMB2
MEM_DQA15
MEM_DQA16
MEM_DQA32
MEM_DQA19
MEM_DQA[33:0]8,17
MEM_DMA[3:0]8,17
MEM_DQSA_P[3:0]8,17
MEM_DQSA_N[3:0]8,17
MEM_ADDR_CMD[31:0]8,17
MEM_CLK_P17MEM_CLK_N17
MEM_DQ_ADDR_CMD[8:0]17
MEM_DQS_ADDR_CMD_P17MEM_DQS_ADDR_CMD_N17
MEM_QKA_P[1:0]17
MEM_DMB[3:0]8,17
MEM_DQB[33:0]8,17
MEM_DQSB_N[3:0]8,17
MEM_DQSB_P[3:0]8,17
MEM_QKB_P[1:0]17
CLOCK_SDA9CLOCK_SCL9
DP_HOT_PLUG18DP_RETURN18
DP_AUX_CH_P18DP_AUX_CH_N18
DISP_I2C_SDA24DISP_I2C_SCL24
DISP_SPISS24
QSFP_MOD_SELn21QSFP_RSTn21QSFP_SCL21QSFP_SDA21
QSFP_INTERRUPTn21QSFP_MOD_PRSn21
QSFP_LP_MODE21
SFP_MOD1_SCL22SFP_MOD2_SDA22
SFP_RS022SFP_RS122
SFP_RX_LOS22
SFP_TX_DISABLE22
SFP_TX_FAULT22SFP_MOD0_PRSNTn22
SDI_MF2_MUTE13,23
SDI_TX_SD_HDn13,23
SDI_MF0_BYPASS13,23SDI_MF1_AUTO_SLEEP13,23
DP_CONFIG118DP_CONFIG218
PCIE_SMBDAT3
RZQ_B2K24
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B4 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B4 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B4 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
BA
NK
-2I
BA
NK
-2K
BA
NK
-2J
BA
NK
-2L
ARRIA 10 - BANK 2I-2L
10AX115F1932C
U28C
IO,LVDS2I_4P,DQS12LAN34
IO,LVDS2I_4N,DQSN12LAM35
IO,LVDS2I_1N,DQ12LAL34 IO,LVDS2I_1P,DQ12LAK34
IO,LVDS2I_3P,DQ12LAL32
IO,LVDS2I_3N,DQ12LAL33
IO,LVDS2I_5P,DQ12LAK32
IO,LVDS2I_5N,DQ12LAK31
IO,LVDS2I_2P,DQ12LAM30
IO,LVDS2I_6N,DQ12LAM32 IO,LVDS2I_6P,DQ12LAM31
IO,LVDS2I_2N,DQ12LAN30
IO,LVDS2I_11N,DQ13LAR35
IO,LVDS2I_7P,DQ13LAR32
IO,LVDS2I_7N,DQ13LAP32
IO,LVDS2I_8P,DQ13LAT37
IO,LVDS2I_8N,DQ13LAU37
IO,LVDS2I_9N,DQ13LAP33 IO,LVDS2I_9P,DQ13LAP34
IO,LVDS2I_14N,DQ14LAR31
IO,LVDS2I_16N,DQSN14LAT35
IO,LVDS2I_17N,DQ14LAP31 IO,LVDS2I_17P,DQ14LAN31
IO,LVDS2I_14P,DQ14LAT30
IO,LVDS2I_16P,DQS14LAT34
IO,LVDS2I_18N,DQ14LAU30 IO,LVDS2I_18P,DQ14LAU31
IO,LVDS2I_23N,DQ15LAV33
IO,LVDS2I_19N,DQ15LAU35 IO,LVDS2I_19P,DQ15LAU36
IO,LVDS2I_23P,DQ15LAW33
IO,LVDS2I_20P,DQ15LAV34
IO,LVDS2I_20N,DQ15LAV35
IO,LVDS2I_22P,DQS15LAW32
IO,LVDS2I_21P,DQ15LAY35
IO,LVDS2I_21N,DQ15LAW34
IO,LVDS2I_22N,DQSN15LAY32
IO,LVDS2I_24P,DQ15LAY34
IO,LVDS2I_24N,DQ15LBA35
IO,LVDS2J_6N,DQ8LAA30
IO,LVDS2J_5P,DQ8LY31
IO,LVDS2J_19P,DQ11LAD34
IO,LVDS2J_19N,DQ11LAC34
IO,LVDS2J_1P,DQ8LAC31
IO,LVDS2J_3N,DQ8LAB31 IO,LVDS2J_3P,DQ8LAB32
IO,LVDS2J_21N,DQ11LAE34
IO,LVDS2J_1N,DQ8LAD31
IO,LVDS2J_2N,DQ8LAD32
IO,LVDS2J_21P,DQ11LAD35
IO,LVDS2J_23N,DQ11LAJ34
IO,LVDS2J_2P,DQ8LAD33
IO,LVDS2J_22P,DQS11LAF33
IO,LVDS2J_23P,DQ11LAJ33
IO,LVDS2J_24P,DQ11LAH34
IO,LVDS2J_8P,DQ9LAE30 IO,LVDS2J_7N,DQ9LAE32
IO,LVDS2J_22N,DQSN11LAF34
IO,LVDS2J_24N,DQ11LAH35
IO,LVDS2J_8N,DQ9LAF30
IO,LVDS2J_7P,DQ9LAE31
IO,LVDS2J_9P,DQ9LAG33
IO,LVDS2J_9N,DQ9LAH33
IO,LVDS2J_11N,DQ9LAG32
IO,LVDS2J_17P,DQ10LW35
IO,LVDS2J_17N,DQ10LY35
IO,LVDS2J_14P,DQ10LW32
IO,LVDS2J_14N,DQ10LW33
IO,LVDS2J_18N,DQ10LV34 IO,LVDS2J_18P,DQ10LV33
IO,LVDS2J_4P,DQS8LY32
IO,LVDS2J_16P,DQS10LAA34
IO,LVDS2J_16N,DQSN10LAA33
IO,LVDS2J_20P,DQ11LAB33
IO,LVDS2J_6P,DQ8LY30 IO,LVDS2J_5N,DQ8LW31
IO,LVDS2J_4N,DQSN8LAA32
IO,LVDS2J_20N,DQ11LAC33
IO,LVDS2K_2N,DQ4LA32
IO,LVDS2K_3N,DQ4LA33
IO,LVDS2K_2P,DQ4LB32
IO,LVDS2K_3P,DQ4LB33
IO,LVDS2K_1N,DQ4LC33
IO,LVDS2K_4N,DQSN4LC34
IO,LVDS2K_5P,DQ4LC35
IO,LVDS2K_1P,DQ4LD32
IO,LVDS2K_4P,DQS4LD33
IO,LVDS2K_5N,DQ4LD34
IO,LVDS2K_9P,DQ5LE32
IO,LVDS2K_6N,DQ4LE34IO,LVDS2K_6P,DQ4LE35
IO,LVDS2K_9N,DQ5LF32
IO,LVDS2K_8N,DQ5LF33IO,LVDS2K_8P,DQ5LG33
IO,LVDS2K_7P,DQ5LG35
IO,LVDS2K_11N,DQ5LH34
IO,LVDS2K_7N,DQ5LH35
IO,LVDS2K_14N,DQ6LJ32IO,LVDS2K_14P,DQ6LJ33
IO,LVDS2K_18P,DQ6LM32
IO,LVDS2K_18N,DQ6LL32
IO,LVDS2K_16N,DQSN6LK34
IO,LVDS2K_17N,DQ6LM35
IO,LVDS2K_16P,DQS6LL34
IO,LVDS2K_17P,DQ6LN34
IO,LVDS2K_19N,DQ7LT32IO,LVDS2K_19P,DQ7LU32
IO,LVDS2K_22N,DQSN7LP33IO,LVDS2K_22P,DQS7LN33
IO,LVDS2K_21P,DQ7LU33
IO,LVDS2K_24N,DQ7LT35IO,LVDS2K_24P,DQ7LT34IO,LVDS2K_23N,DQ7LP34
IO,LVDS2K_20P,DQ7LR30
IO,LVDS2K_20N,DQ7LR31
IO,LVDS2K_21N,DQ7LT33
IO,LVDS2K_23P,DQ7LR34
IO,LVDS2L_2N,DQ0LA27IO,LVDS2L_2P,DQ0LA28
IO,LVDS2L_4P,DQS0LB26
IO,LVDS2L_3N,DQ0LB27IO,LVDS2L_3P,DQ0LB28
IO,LVDS2L_4N,DQSN0LC26
IO,LVDS2L_6P,DQ0LC28
IO,LVDS2L_16N,DQSN2LC29IO,LVDS2L_16P,DQS2LC30
IO,LVDS2L_14N,DQ2LC31
IO,LVDS2L_1P,DQ0LD26
IO,LVDS2L_5P,DQ0LD27
IO,LVDS2L_6N,DQ0LD28
IO,LVDS2L_18N,DQ2LD29
IO,LVDS2L_14P,DQ2LD31
IO,LVDS2L_1N,DQ0LE26
IO,LVDS2L_5N,DQ0LE27
IO,LVDS2L_18P,DQ2LE29
IO,LVDS2L_17P,DQ2LE30
IO,LVDS2L_17N,DQ2LE31
IO,LVDS2L_7N,DQ1LF27IO,LVDS2L_7P,DQ1LF28
IO,LVDS2L_19N,DQ3LF29IO,LVDS2L_19P,DQ3LF30
IO,LVDS2L_9N,DQ1LG25
IO,LVDS2L_8N,DQ1LG27IO,LVDS2L_8P,DQ1LG28
IO,LVDS2L_23P,DQ3LG30
IO,LVDS2L_23N,DQ3LG31
IO,LVDS2L_9P,DQ1LH25
IO,LVDS2L_24P,DQ3LH29
IO,LVDS2L_24N,DQ3LH30
IO,LVDS2L_20N,DQ3LJ29
IO,LVDS2L_11N,DQ1LK27
IO,LVDS2L_21N,DQ3LK30
IO,LVDS2L_20P,DQ3LK29
IO,LVDS2L_22N,DQSN3LL29
IO,LVDS2L_21P,DQ3LK31
IO,LVDS2L_22P,DQS3LL30
IO,RZQ_2I,LVDS2I_11P,DQ13LAR34
IO,RZQ_2J,LVDS2J_11P,DQ9LAF32
IO,RZQ_2K,LVDS2K_11P,DQ5LJ34
IO,RZQ_2L,LVDS2L_11P,DQ1LJ28
R449100, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Bank 3A-3DFLASH/FM BUS
FMC PORT A INTERFACE
ARRIA 10 USB INTERFACEVCCIO = 1.8V
FMCA VARIABLE VCCIO
DEFAULT 1.8V
(1.2V, 1.5V, 1.8V)
FMCA VARIABLE VCCIO
DEFAULT 1.8V
(1.2V, 1.5V, 1.8V)
VCCIO = 1.8V
3.3V to 1.8V
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16FM_A17
FM_A18
FMCA_LA_TX_N10
FMCA_LA_RX_P10FMCA_LA_RX_N10
FMCA_LA_TX_P10
FM_A19
FMCA_LA_TX_N11
FMCA_LA_RX_P11FMCA_LA_RX_N11
FMCA_LA_TX_P11
FM_A20
FMCA_LA_TX_N12
FMCA_LA_RX_P12FMCA_LA_RX_N12
FMCA_LA_TX_P12
FM_A21
FMCA_LA_TX_N13
FMCA_LA_RX_P13FMCA_LA_RX_N13
FMCA_LA_TX_P13
FM_A22
FM_A23
FMCA_LA_TX_N14
FMCA_LA_RX_P14FMCA_LA_RX_N14
FMCA_LA_TX_P14
FM_A24
FMCA_LA_TX_N15FMCA_LA_TX_P15
FMCA_LA_TX_N16FMCA_LA_TX_P16
FM_A25
FM_A26
FMCA_GA0
FMCA_GA1
FMCA_SCLFMCA_SDA
USB_DATA0
USB_ADDR0
USB_DATA1
USB_ADDR1
USB_DATA2USB_DATA3
USB_DATA4USB_DATA5
USB_DATA6USB_DATA7
USB_RESETn
USB_OEnUSB_RDn
USB_WRn
FM_A1FM_A2
FM_A3
RZQ_B3C
FM_A4FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FMCA_LA_RX_P9FMCA_LA_RX_N9
FMCA_LA_RX_P3FMCA_LA_RX_N3
FMCA_LA_TX_N3
FM_D10
FMCA_LA_TX_P3
FM_D11
FMCA_LA_TX_N4
FMCA_LA_RX_P4FMCA_LA_RX_N4
FMCA_LA_TX_P4
FM_D12
FMCA_LA_TX_N5
FMCA_LA_RX_P5FMCA_LA_RX_N5
FMCA_LA_TX_P5
FM_D13
FMCA_LA_TX_N6
FMCA_LA_RX_P6FMCA_LA_RX_N6
FMCA_LA_TX_P6
FM_D14FMCA_LA_TX_N7
FMCA_LA_RX_P7FMCA_LA_RX_N7
FMCA_LA_TX_P7
FM_D15
FMCA_LA_TX_N8
FMCA_LA_RX_P8FMCA_LA_RX_N8
FMCA_LA_TX_P8
FM_D16
FM_D17
FMCA_LA_TX_N9FMCA_LA_TX_P9
FM_D18
FM_D19
FM_D20
FM_D21
FM_D22
FM_D23
FM_D24
FM_D25
FM_D26FM_D27
FM_D28
FM_D29
FM_D30
FM_D31
FLASH_CLK
FLASH_RESETn
FLASH_CEn0FLASH_CEn1
FLASH_OEnFLASH_WEn
FLASH_ADVn
FLASH_RDYBSYn0
FM_D0
FM_D1
FM_D2
FM_D3
FMCA_LA_RX_P0
FM_D4
FMCA_LA_RX_N0
FM_D5
FMCA_LA_TX_P0FMCA_LA_TX_N0
FM_D6
FM_D7
FMCA_LA_RX_P1FMCA_LA_RX_N1
FMCA_LA_TX_N1FMCA_LA_TX_P1
FM_D8
FMCA_LA_RX_P2FMCA_LA_RX_N2
FMCA_LA_TX_N2FMCA_LA_TX_P2
FM_D9
FMCA_3P3V_SDAFMCA_3P3V_SCL FMCA_SCL
FMCA_SDA
3.3V 1.8V
FM_D[31:0]13,14
FM_A[26:1]13,14
FLASH_CLK13,14FLASH_RESETn13,14FLASH_CEn013,14FLASH_CEn113,14
FLASH_WEn13,14FLASH_OEn13,14
FLASH_ADVn13,14FLASH_RDYBSYn013,14
FMCA_LA_RX_P[14:0]19
FMCA_LA_RX_N[14:0]19
FMCA_LA_TX_P[16:0]19
FMCA_LA_TX_N[16:0]19
FMCA_GA[1:0]19
FMCA_3P3V_SDA19FMCA_3P3V_SCL19
USB_DATA[7:0]26
USB_ADDR[1:0]26
USB_RESETn26USB_OEn26USB_RDn26USB_WRn26
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B5 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B5 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B5 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R65810.0K
R65910.0K
BA
NK
-3A
BA
NK
-3C
BA
NK
-3B
BA
NK
-3D
ARRIA 10 - BANK 3A-3D
10AX115F1932C
U28D
IO,LVDS3A_1P,DQ60RAP22
IO,LVDS3A_1N,DQ60RAP23
IO,LVDS3A_4N,DQSN60RAP24
IO,LVDS3A_5P,DQ60RAP26
IO,LVDS3A_4P,DQS60RAR24
IO,LVDS3A_2N,DQ60RAR25
IO,LVDS3A_5N,DQ60RAR26
IO,LVDS3A_3P,DQ60RAT23
IO,LVDS3A_3N,DQ60RAT24
IO,LVDS3A_2P,DQ60RAT25
IO,LVDS3A_6N,DQ60RAU22 IO,LVDS3A_6P,DQ60RAU23
IO,LVDS3A_9P,DQ61RAU25
IO,LVDS3A_9N,DQ61RAV25
IO,LVDS3A_11N,DQ61RAY22
IO,LVDS3A_8P,DQ61RAY24 IO,LVDS3A_7N,DQ61RAY25
IO,LVDS3A_22P,DQS63RBA17
IO,LVDS3A_22N,DQSN63RBA18
IO,LVDS3A_21P,DQ63RBA19
IO,LVDS3A_21N,DQ63RBA20
IO,LVDS3A_18P,DQ62RBA22
IO,LVDS3A_16N,DQSN62RBA23
IO,LVDS3A_8N,DQ61RBA24
IO,LVDS3A_7P,DQ61RBA25
IO,LVDS3A_24N,DQ63RBB20
IO,LVDS3A_23N,DQ63RBB21
IO,LVDS3A_18N,DQ62RBB22
IO,LVDS3A_16P,DQS62RBB23
IO,LVDS3A_14N,DQ62RBB25
IO,LVDS3A_20P,DQ63RBC19
IO,LVDS3A_24P,DQ63RBC20
IO,LVDS3A_23P,DQ63RBC21
IO,LVDS3A_14P,DQ62RBC25
IO,LVDS3A_17N,DQ62RBC26
IO,LVDS3A_20N,DQ63RBD19
IO,LVDS3A_19P,DQ63RBD21
IO,LVDS3A_19N,DQ63RBD22
IO,LVDS3A_17P,DQ62RBD26
IO,LVDS3B_21N,DQ59RAN19
IO,LVDS3B_22P,DQS59RAN20
IO,LVDS3B_1N,DQ56RAP16
IO,LVDS3B_4N,DQSN56RAP17
IO,LVDS3B_21P,DQ59RAP18
IO,LVDS3B_22N,DQSN59RAP19
IO,LVDS3B_20P,DQ59RAP21
IO,LVDS3B_5N,DQ56RAR14
IO,LVDS3B_6P,DQ56RAR15
IO,LVDS3B_1P,DQ56RAR16
IO,LVDS3B_4P,DQS56RAR17
IO,LVDS3B_23N,DQ59RAR19 IO,LVDS3B_23P,DQ59RAR20
IO,LVDS3B_20N,DQ59RAR21
IO,LVDS3B_24P,DQ59RAR22
IO,LVDS3B_5P,DQ56RAT14
IO,LVDS3B_6N,DQ56RAT15
IO,LVDS3B_3P,DQ56RAT17 IO,LVDS3B_2N,DQ56RAT18
IO,LVDS3B_19P,DQ59RAT19
IO,LVDS3B_19N,DQ59RAT20
IO,LVDS3B_24N,DQ59RAT22
IO,LVDS3B_3N,DQ56RAU17
IO,LVDS3B_2P,DQ56RAU18
IO,LVDS3B_18N,DQ58RAU20
IO,LVDS3B_16P,DQS58RAU21
IO,LVDS3B_14N,DQ58RAV18
IO,LVDS3B_17P,DQ58RAV19
IO,LVDS3B_18P,DQ58RAV20
IO,LVDS3B_16N,DQSN58RAV21
IO,LVDS3B_11N,DQ57RAY14
IO,LVDS3B_9N,DQ57RAW16
IO,LVDS3B_7N,DQ57RAW17
IO,LVDS3B_14P,DQ58RAW18
IO,LVDS3B_17N,DQ58RAW19
IO,LVDS3B_8N,DQ57RAW14 IO,LVDS3B_8P,DQ57RAV14
IO,LVDS3B_9P,DQ57RAY16
IO,LVDS3B_7P,DQ57RAY17
IO,LVDS3C_11N,DQ53RAP13
IO,LVDS3C_9N,DQ53RAT8
IO,LVDS3C_7P,DQ53RAR9
IO,LVDS3C_9P,DQ53RAU8
IO,LVDS3C_8P,DQ53RAT13IO,LVDS3C_7N,DQ53RAT9
IO,LVDS3C_1P,DQ52RAU10
IO,LVDS3C_2P,DQ52RAU11
IO,LVDS3C_2N,DQ52RAU12
IO,LVDS3C_8N,DQ53RAU13
IO,LVDS3C_1N,DQ52RAV10
IO,LVDS3C_6N,DQ52RAY11
IO,LVDS3C_3N,DQ52RAV13
IO,LVDS3C_6P,DQ52RAY10
IO,LVDS3C_4P,DQS52RAW12
IO,LVDS3C_3P,DQ52RAW13
IO,LVDS3C_5N,DQ52RAW11IO,LVDS3C_5P,DQ52RAV11
IO,LVDS3C_4N,DQSN52RAY12
IO,LVDS3C_21N,DQ55RBA14IO,LVDS3C_21P,DQ55RBA15
IO,LVDS3C_16N,DQSN54RBB11IO,LVDS3C_16P,DQS54RBB12IO,LVDS3C_18N,DQ54RBB13
IO,LVDS3C_22P,DQS55RBB15
IO,LVDS3C_19N,DQ55RBB16
IO,LVDS3C_24P,DQ55RBB17
IO,LVDS3C_24N,DQ55RBB18
IO,LVDS3C_18P,DQ54RBC13
IO,LVDS3C_17P,DQ54RBC14
IO,LVDS3C_22N,DQSN55RBC15
IO,LVDS3C_19P,DQ55RBC16
IO,LVDS3C_23P,DQ55RBC18
IO,LVDS3C_14N,DQ54RBD12IO,LVDS3C_14P,DQ54RBD13
IO,LVDS3C_17N,DQ54RBD14
IO,LVDS3C_20N,DQ55RBD16IO,LVDS3C_20P,DQ55RBD17
IO,LVDS3C_23N,DQ55RBD18
IO,LVDS3D_7N,DQ49RAE12IO,LVDS3D_7P,DQ49RAF12
IO,LVDS3D_9P,DQ49RAF14
IO,LVDS3D_11N,DQ49RAE15
IO,LVDS3D_8P,DQ49RAG12
IO,LVDS3D_9N,DQ49RAF15
IO,LVDS3D_5N,DQ48RAH11IO,LVDS3D_5P,DQ48RAH10
IO,LVDS3D_8N,DQ49RAG11
IO,LVDS3D_6N,DQ48RAJ13
IO,LVDS3D_3P,DQ48RAK14
IO,LVDS3D_2P,DQ48RAL12
IO,LVDS3D_2N,DQ48RAL13
IO,LVDS3D_6P,DQ48RAJ12
IO,LVDS3D_1P,DQ48RAJ11
IO,LVDS3D_3N,DQ48RAJ14
IO,LVDS3D_4N,DQSN48RAH14
IO,LVDS3D_23P,DQ51RAP11
IO,LVDS3D_1N,DQ48RAK12
IO,LVDS3D_4P,DQS48RAH13
IO,LVDS3D_16P,DQS50RAM15
IO,LVDS3D_14N,DQ50RAK15IO,LVDS3D_14P,DQ50RAL15
IO,LVDS3D_23N,DQ51RAR10
IO,LVDS3D_20N,DQ51RAK11
IO,LVDS3D_24P,DQ51RAM12
IO,LVDS3D_24N,DQ51RAM11
IO,LVDS3D_16N,DQSN50RAL14
IO,LVDS3D_18N,DQ50RAL17
IO,LVDS3D_17N,DQ50RAL20
IO,LVDS3D_19P,DQ51RAN11
IO,LVDS3D_20P,DQ51RAL10
IO,LVDS3D_21N,DQ51RAM13
IO,LVDS3D_18P,DQ50RAM17
IO,LVDS3D_17P,DQ50RAL19
IO,LVDS3D_19N,DQ51RAN10
IO,LVDS3D_21P,DQ51RAN13
IO,LVDS3D_22N,DQSN51RAN14IO,LVDS3D_22P,DQS51RAN15
RZQ_3A,LVDS3A_11P,DQ61RAW22
IO,RZQ_3B,LVDS3B_11P,DQ57RAY15
IO,RZQ_3C,LVDS3C_11P,DQ53RAP14
IO,RZQ_3D,LVDS3D_11P,DQ49RAE14
R352 100, 1%
R65710.0K
R66210.0K
R66110.0K
C7950.01uF
C7940.1uF
R66010.0K
U79
LTC4315
DISCEN2
VCC12
SCLOUT3
SCLIN4
ACCn5
GND6
READY7
ENABLE1
FAULTn8
SDAOUT10
VCC211
SDAIN9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
MAX V INTERFACE
FMC PORT B INTERFACE
USER I/O INTERFACE
ARRIA 10 CLOCKS
FMC PORT A INTERFACE
Arria 10 Bank 3E-3H
VCCIO = 1.8V
VCCIO = 1.8V
FMCB VARIABLE VCCIO
DEFAULT 1.8V
(1.2V, 1.5V, 1.8V)
FMCB VARIABLE VCCIO
DEFAULT 1.8V
(1.2V, 1.5V, 1.8V)
USER IO INTERFACE
3.3V to 1.8V
FMCB_LA_RX_P0FMCB_LA_RX_N0
FMCB_LA_TX_P0FMCB_LA_TX_N0
FMCB_LA_RX_P1FMCB_LA_RX_N1
FMCB_LA_TX_N1FMCB_LA_TX_P1
FMCB_LA_RX_P2FMCB_LA_RX_N2
FMCB_LA_TX_N2FMCB_LA_TX_P2
FMCB_LA_RX_P3
FMCB_LA_TX_N3
FMCB_LA_RX_N3
FMCB_LA_TX_P3
FMCB_LA_TX_N4
FMCB_LA_RX_P4FMCB_LA_RX_N4
FMCB_LA_TX_P4
FMCB_LA_TX_N5
FMCB_LA_RX_P5FMCB_LA_RX_N5
FMCB_LA_TX_P5
FMCB_LA_TX_N6
FMCB_LA_RX_P6FMCB_LA_RX_N6
FMCB_LA_TX_P6
FMCB_LA_TX_N7
FMCB_LA_RX_P7FMCB_LA_RX_N7
FMCB_LA_TX_P7
FMCB_LA_TX_N8
FMCB_LA_RX_P8FMCB_LA_RX_N8
FMCB_LA_TX_P8
FMCB_LA_TX_N9
FMCB_LA_RX_P9FMCB_LA_RX_N9
FMCB_LA_TX_P9
RZQ_B3E
FMCA_PRSNTnFMCB_PRSNTn
MAX5_BEn0MAX5_BEn1
MAX5_BEn2
MAX5_BEn3MAX5_OEn
MAX5_CSn
MAX5_WEn
VID0
VID1
VID2
VID3
VID4VID5
FMCB_LA_TX_N10
FMCB_LA_RX_P10FMCB_LA_RX_N10
FMCB_LA_TX_P10
FMCB_LA_TX_N11
FMCB_LA_RX_P11FMCB_LA_RX_N11FMCB_LA_TX_P11
FMCB_LA_TX_N12
FMCB_LA_RX_P12FMCB_LA_RX_N12
FMCB_LA_TX_P12
FMCB_LA_TX_N13
FMCB_LA_RX_P13FMCB_LA_RX_N13
FMCB_LA_TX_P13
FMCB_LA_TX_N14
FMCB_LA_RX_P14FMCB_LA_RX_N14
FMCB_LA_TX_P14
FMCB_LA_TX_N15FMCB_LA_TX_P15
FMCB_LA_TX_N16FMCB_LA_TX_P16
FMCB_SDA
FMCB_GA0
FMCB_SCL
FMCB_GA1
FMCA_RX_LED
FMCA_TX_LED
FMCB_RX_LED
FMCB_TX_LED
SDI_CLK148_UPSDI_CLK148_DOWN
USER_LED_G0USER_LED_R0
USER_LED_G1USER_LED_R1
USER_LED_G2
USER_LED_R2
USER_LED_G3
USER_LED_R3
USER_LED_G4
USER_LED_R4
USER_LED_G5
USER_LED_R5
USER_DIPSW0
USER_LED_G6USER_LED_R6
USER_LED_G7
USER_LED_R7
USER_DIPSW1USER_DIPSW2
USER_DIPSW3USER_DIPSW4
USER_DIPSW5USER_DIPSW6USER_DIPSW7
USER_PB0USER_PB1
USER_PB2
VID_EN
RZQ_B3G
FMCB_3P3V_SDAFMCB_3P3V_SCL FMCB_SCL
FMCB_SDA
A10_SI516_FS
3.3V 1.8V
MAX5_BEn[3:0]13
MAX5_OEn13MAX5_CSn13MAX5_WEn13
FMCB_GA[1:0]20
FMCB_3P3V_SDA20FMCB_PRSNTn13,20,24,26
FMCB_3P3V_SCL20
FMCB_LA_RX_P[14:0]20
FMCB_LA_RX_N[14:0]20
FMCB_LA_TX_P[16:0]20
FMCB_LA_TX_N[16:0]20
FMCA_RX_LED24FMCA_TX_LED24
FMCB_TX_LED24FMCB_RX_LED24
SDI_CLK148_UP9SDI_CLK148_DOWN9
FMCA_PRSNTn13,19,24,26
VID_EN7,35
VID[5:0]35
USER_LED_G[7:0]24
USER_LED_R[7:0]24
USER_DIPSW[7:0]24
USER_PB[2:0]24
A10_SI516_FS9
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B6 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B6 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B6 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R66310.0K
R368100, 1%
C7970.01uF
R66810.0K
R946 DNI
BA
NK
-3E
BA
NK
-3G
BA
NK
-3F
BA
NK
-3H
ARRIA 10 - BANK 3E-3H
10AX115F1932C
U28E
IO,LVDS3E_14N,DQ46RAD13 IO,LVDS3E_14P,DQ46RAD14
IO,LVDS3E_16N,DQSN46RAB12
IO,LVDS3E_18P,DQ46RAB13
IO,LVDS3E_16P,DQS46RAC13
IO,LVDS3E_3P,DQ44RL12
IO,LVDS3E_3N,DQ44RM11
IO,LVDS3E_6P,DQ44RN11
IO,LVDS3E_5P,DQ44RN13
IO,LVDS3E_5N,DQ44RN14
IO,LVDS3E_8N,DQ45RN15 IO,LVDS3E_8P,DQ45RN16
IO,LVDS3E_6N,DQ44RP11
IO,LVDS3E_4N,DQSN44RP12 IO,LVDS3E_4P,DQS44RP13
IO,LVDS3E_1N,DQ44RR11
IO,LVDS3E_7N,DQ45RP16 IO,LVDS3E_7P,DQ45RP17
IO,LVDS3E_2P,DQ44RN10
IO,LVDS3E_2N,DQ44RM10
IO,LVDS3E_1P,DQ44RR12
IO,LVDS3E_9P,DQ45RT14
IO,LVDS3E_9N,DQ45RR15
IO,LVDS3E_21N,DQ47RT12 IO,LVDS3E_21P,DQ47RU12 IO,LVDS3E_20N,DQ47RT10 IO,LVDS3E_20P,DQ47RU11
IO,LVDS3E_19P,DQ47RV13
IO,LVDS3E_11N,DQ45RW14
IO,LVDS3E_22N,DQSN47RW10
IO,LVDS3E_19N,DQ47RW13
IO,LVDS3E_22P,DQS47RV11 IO,LVDS3E_24N,DQ47RW11 IO,LVDS3E_24P,DQ47RW12
IO,LVDS3E_23P,DQ47RY14
IO,LVDS3E_23N,DQ47RY15
IO,LVDS3E_17N,DQ46RY11 IO,LVDS3E_17P,DQ46RY10
IO,LVDS3E_18N,DQ46RAA14
IO,LVDS3F_8N,DQ41RA12
IO,LVDS3F_7P,DQ41RA13
IO,LVDS3F_6N,DQ40RA14 IO,LVDS3F_6P,DQ40RA15
IO,LVDS3F_5P,DQ40RA17
IO,LVDS3F_4P,DQS40RA18
IO,LVDS3F_8P,DQ41RB12 IO,LVDS3F_7N,DQ41RB13
IO,LVDS3F_3N,DQ40RB15
IO,LVDS3F_2P,DQ40RB16
IO,LVDS3F_5N,DQ40RB17
IO,LVDS3F_4N,DQSN40RB18
IO,LVDS3F_11N,DQ41RC13
IO,LVDS3F_3P,DQ40RC15 IO,LVDS3F_2N,DQ40RC16
IO,LVDS3F_9N,DQ41RD11 IO,LVDS3F_9P,DQ41RD12
IO,LVDS3F_1N,DQ40RD16 IO,LVDS3F_1P,DQ40RD17
IO,LVDS3F_21N,DQ43RE10 IO,LVDS3F_21P,DQ43RE11
IO,LVDS3F_23P,DQ43RE12
IO,LVDS3F_22N,DQSN43RF10
IO,LVDS3F_23N,DQ43RF12
IO,LVDS3F_19P,DQ43RF13
IO,LVDS3F_22P,DQS43RG10
IO,LVDS3F_20P,DQ43RG11
IO,LVDS3F_20N,DQ43RG12
IO,LVDS3F_19N,DQ43RG13
IO,LVDS3F_24N,DQ43RH10 IO,LVDS3F_24P,DQ43RH11
IO,LVDS3F_17P,DQ42RH13
IO,LVDS3F_17N,DQ42RJ13
IO,LVDS3F_14N,DQ42RJ14 IO,LVDS3F_14P,DQ42RK14
IO,LVDS3F_18P,DQ42RM12
IO,LVDS3F_18N,DQ42RL13
IO,LVDS3F_16N,DQSN42RL14 IO,LVDS3F_16P,DQS42RM13
IO,LVDS3G_17P,DQ38RE14
IO,LVDS3G_16N,DQSN38RE15
IO,LVDS3G_11N,DQ37RE19
IO,LVDS3G_17N,DQ38RF14
IO,LVDS3G_16P,DQS38RF15IO,LVDS3G_18N,DQ38RG15IO,LVDS3G_18P,DQ38RG16
IO,LVDS3G_7N,DQ37RG20
IO,LVDS3G_8P,DQ37RG21
IO,LVDS3G_14P,DQ38RH14
IO,LVDS3G_14N,DQ38RH15
IO,LVDS3G_20P,DQ39RH16
IO,LVDS3G_9N,DQ37RH18IO,LVDS3G_9P,DQ37RH19
IO,LVDS3G_7P,DQ37RH20
IO,LVDS3G_8N,DQ37RH21
IO,LVDS3G_20N,DQ39RJ16
IO,LVDS3G_19P,DQ39RJ17
IO,LVDS3G_19N,DQ39RJ18
IO,LVDS3G_3P,DQ36RJ19
IO,LVDS3G_4N,DQSN36RJ21IO,LVDS3G_4P,DQS36RJ22
IO,LVDS3G_22P,DQS39RK16
IO,LVDS3G_22N,DQSN39RK17
IO,LVDS3G_3N,DQ36RK19
IO,LVDS3G_2P,DQ36RK20
IO,LVDS3G_5N,DQ36RK21
IO,LVDS3G_1P,DQ36RK22
IO,LVDS3G_24N,DQ39RL15
IO,LVDS3G_21P,DQ39RL18
IO,LVDS3G_2N,DQ36RL19
IO,LVDS3G_5P,DQ36RL20
IO,LVDS3G_1N,DQ36RL22
IO,LVDS3G_24P,DQ39RM15
IO,LVDS3G_23P,DQ39RM16
IO,LVDS3G_23N,DQ39RM17
IO,LVDS3G_21N,DQ39RM18
IO,LVDS3G_6N,DQ36RM20IO,LVDS3G_6P,DQ36RM21
IO,LVDS3H_4N,DQSN32RA19IO,LVDS3H_4P,DQS32RA20
IO,LVDS3H_5P,DQ32RA22
IO,LVDS3H_7P,DQ33RA23
IO,LVDS3H_8N,DQ33RA24IO,LVDS3H_8P,DQ33RA25
IO,LVDS3H_1P,DQ32RB20
IO,LVDS3H_6P,DQ32RB21IO,LVDS3H_5N,DQ32RB22
IO,LVDS3H_7N,DQ33RB23
IO,LVDS3H_2N,DQ32RC18
IO,LVDS3H_3N,DQ32RC19
IO,LVDS3H_1N,DQ32RC20
IO,LVDS3H_6N,DQ32RC21
IO,LVDS3H_11N,DQ33RC24
IO,LVDS3H_2P,DQ32RD18
IO,LVDS3H_3P,DQ32RD19
IO,LVDS3H_9P,DQ33RD21
IO,LVDS3H_9N,DQ33RD22
IO,LVDS3H_14N,DQ34RE21IO,LVDS3H_14P,DQ34RE22
IO,LVDS3H_16N,DQSN34RE25
IO,LVDS3H_17P,DQ34RF22
IO,LVDS3H_16P,DQS34RF25
IO,LVDS3H_17N,DQ34RG22
IO,LVDS3H_18P,DQ34RH23
IO,LVDS3H_18N,DQ34RH24
IO,LVDS3H_19N,DQ35RJ23IO,LVDS3H_19P,DQ35RJ24
IO,LVDS3H_21N,DQ35RJ26
IO,LVDS3H_22N,DQSN35RK24
IO,LVDS3H_20N,DQ35RK25
IO,LVDS3H_21P,DQ35RK26
IO,LVDS3H_23P,DQ35RL23
IO,LVDS3H_22P,DQS35RL24
IO,LVDS3H_20P,DQ35RL25
IO,LVDS3H_23N,DQ35RM23
IO,LVDS3H_24P,DQ35RL27
IO,LVDS3H_24N,DQ35RL28
IO,RZQ_3E,LVDS3E_11P,DQ45RV14
IO,RZQ_3F,LVDS3F_11P,DQ41RD13
IO,RZQ_3G,LVDS3G_11P,DQ37RF19
IO,RZQ_3H,LVDS3H_11P,DQ33RD24
U80
LTC4315
DISCEN2
VCC12
SCLOUT3
SCLIN4
ACCn5
GND6
READY7
ENABLE1
FAULTn8
SDAOUT10
VCC211
SDAIN9
R66610.0K
R66710.0K
R66410.0K
R382 100, 1%
R66510.0K
C7960.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 ConfigurationFPGA_nCONFIGPull-up not needed for FPP.Pull-up needed for AS.
CvP CLKUSR 100MHz
MSEL0
FPGA_TRST
FPGA_DCLK
MSEL1MSEL2
FPGA_nCONFIG
FPGA_nCEFPGA_nIO_PULLUP
FPGA_nIO_PULLUP
FPGA_CvP_CONFDONE
FPGA_PR_DONEFPGA_PR_READYFPGA_PR_ERROR
FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14
FPGA_CONFIG_D1FPGA_CONFIG_D0
FPGA_CONFIG_D15
FPGA_CONFIG_D7
FPGA_CONFIG_D2
FPGA_CONFIG_D4FPGA_CONFIG_D5FPGA_CONFIG_D6
FPGA_CONFIG_D3
FPGA_CONFIG_D18FPGA_CONFIG_D19FPGA_CONFIG_D20FPGA_CONFIG_D21FPGA_CONFIG_D22FPGA_CONFIG_D23FPGA_CONFIG_D24FPGA_CONFIG_D25FPGA_CONFIG_D26FPGA_CONFIG_D27FPGA_CONFIG_D28
FPGA_CONFIG_D16FPGA_CONFIG_D17
FPGA_CONFIG_D29FPGA_CONFIG_D30FPGA_CONFIG_D31
VID_EN
A10_CVP_100M
A10_VCCIO_1.8V
A10_VCCIO_1.8V
A10_VCCIO_1.8V
A10_VCCIO_1.8VA10_VCCIO_1.8V
A10_VCCIO_1.8V A10_VCCIO_1.8V
TEMPDIODE_P 29TEMPDIODE_N 29
A10_JTAG_TDO26
A10_JTAG_TCK26A10_JTAG_TDI26
A10_JTAG_TMS26
FPGA_AS_DATA114FPGA_AS_DATA014
FPGA_AS_DATA214FPGA_AS_DATA314
FPGA_nCSO14
FPGA_nCONFIG 13
FPGA_DCLK 13,14
MSEL0 13MSEL1 13MSEL2 13
FPGA_CONF_DONE13,35FPGA_nSTATUS13
PCIE_PERSTn3
FPGA_CvP_CONFDONE13
FPGA_PR_REQUEST13FPGA_PR_DONE13
FPGA_PR_READY13FPGA_PR_ERROR13
FPGA_CONFIG_D[31:0] 13
CPU_RESETn13,24
VID_EN6,35
FPGA_VID_EN35
PCIE_LED_G224
PCIE_LED_X124PCIE_LED_X424
PCIE_LED_X824
PCIE_SMBCLK3
PCIE_WAKEn3
PCIE_LED_G324
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B7 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B7 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B7 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R42610.0K
R41010.0K
R475 1.00k
C565 DNI
OPEN
SW5
DIPSWITCH4
12345
678
R404DNI
R427 DNI
R42310.0K
R4361.00k
R41110.0K
ARRIA 10 CONFIGURATION
BANK 2A
BANK CSS
CORE
10AX115F1932C
U28A
LVDS2A_1n,DQ28L,DATA0AU27
LVDS2A_1p,DQ28L,DATA1AU28
LVDS2A_6n,DQ28L,DATA10AV26
LVDS2A_6p,DQ28L,DATA11AU26
LVDS2A_7n,DQ29L,DATA12AV29
LVDS2A_7p,DQ29L,DATA13AV30
LVDS2A_8n,DQ29L,DATA14AV31
LVDS2A_8p,DQ29L,DATA15AW31
LVDS2A_9n,DQ29L,DATA16AW28
LVDS2A_9p,DQ29L,DATA17AV28
PLL_2A_CLKOUT1n,DQSn29L,DATA18AY31
PLL_2A_CLKOUT1p,DQS29L,DATA19AY30
LVDS2A_2n,DQ28L,DATA2AP28
CLK_2A_1n,DQ29L,DATA20BA29
CLK_2A_1p,DQ29L,DATA21BA30
CLK_2A_0n,DQ30L,DATA22BA32
CLK_2A_0p,DQ30L,DATA23BB32
LVDS2A_14n,DQ30L,DATA24BA33
LVDS2A_14p,DQ30L,DATA25BB33
PLL_2A_CLKOUT0n,DQ30L,DATA26BB31
PLL_2A_CLKOUT0p,DQ30L,DATA27BC31
LVDS2A_16n,DQSn30L,DATA28BC33
LVDS2A_16p,DQS30L,DATA29BD33
LVDS2A_2p,DQ28L,DATA3AR29
LVDS2A_17n,DQ30L,DATA30BA34
LVDS2A_17p,DQ30L,DATA31BB35
LVDS2A_3n,DQ28L,DATA4AT28
LVDS2A_3p,DQ28L,DATA5AT29
LVDS2A_4n,DQSn28L,DATA6AW27
LVDS2A_4p,DQS28L,DATA7AY27
LVDS2A_5n,DQ28L,DATA8AY26
LVDS2A_5p,DQ28L,DATA9AW26
MSEL0AN26
MSEL1AL28
MSEL2AK25
AS_DATA0,ASDOAL27
AS_DATA1AL22
AS_DATA2AM20
AS_DATA3AL25
LVDS2A_18n,DQ30L,CLKUSRBD32
CONF_DONEAP27
LVDS2A_24n,DQ31L,CRCERRORBD28
LVDS2A_22n,DQSn31L,CvP_CONFDONEBB26
DCLKAM26
LVDS2A_24p,DQ31L,DEV_CLRnBD27LVDS2A_23p,DQ31L,DEV_OEBD29
LVDS2A_23n,DQ31L,INIT_DONEBC29
nCEAM25
LVDS2A_11n,DQ29L,nCEOAY29
nCONFIGAK30
nCSO0AM23
nCSO1AN25
nCSO2AM27
nIO_PULLUPAN24
LVDS2A_19p,DQ31L,nPERSTL0BC30
LVDS2A_20p,DQ31L,nPERSTL1BC28
LVDS2A_22p,DQS31L,nPERSTR0BB27
LVDS2A_21p,DQ31L,nPERSTR1BA27
nSTATUSAN29
LVDS2A_20n,DQ31L,PR_DONEBB28
LVDS2A_21n,DQ31L,PR_ERRORBA28LVDS2A_19n,DQ31L,PR_READYBB30LVDS2A_18p,DQ30L,PR_REQUESTBD31
TCKAM21
TDIAN21
TDOAL29
TMSAL24
TRSTAL30
TEMPDIODEpN20
TEMPDIODEnN21
RZQ_2A,LVDS2A_11p,DQ29LAW29
R402 1.00k
R489 1.00k
R412 1.00k
R39210.0K
C175 0.01uF
R42510.0K
R476 1.00k
X7
100MHz
VCC4
GND2
OUT3
EN1
R424 1.00k
R422 10.0K
R490 1.00k
R405 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
ARRIA 10 CLOCKS
Arria 10 Clocks
MEMORY INTERFACE
VCCIO = 1.8V
VARIABLE EMI VCCIO(1.2V, 1.35V, 1.5V)
VARIABLE EMI VCCIO(1.2V, 1.35V, 1.5V)
VARIABLE EMI VCCIO(1.2V, 1.35V, 1.5V)
VCCIO = 1.8V
VCCIO = 1.8V
VCCIO = 1.8V
VCCIO = 1.8V
FMCA VARIABLE VCCIODEFAULT 1.8V(1.2V, 1.5V, 1.8V)
FMCA VARIABLE VCCIODEFAULT 1.8V(1.2V, 1.5V, 1.8V)
FMCB VARIABLE VCCIODEFAULT 1.8V(1.2V, 1.5V, 1.8V)
FMCB VARIABLE VCCIODEFAULT 1.8V(1.2V, 1.5V, 1.8V)
FLASH INTERFACE
FMC PORT A INTERFACE
ARRIA 10 USB INTERFACE
MAX V INTERFACE
FMC PORT B INTERFACE
CAN BE REMOVED FOR ARRIA 10 AND USE OCT ->
CAN BE REMOVED FOR ARRIA 10 AND USE OCT ->
STRATIX V MSEL PINS.CAN BE DELETED IN REV B
ETHERNET INTERFACE
CAN BE REMOVED FOR ARRIA 10 AND USE OCT ->
CAN BE REMOVED FOR ARRIA 10 AND USE OCT ->
CLK_FPGA_B2_PCLK_FPGA_B2_N
CLK_FPGA_B3_PCLK_FPGA_B3_N
MEM_DQB15
MEM_DQB16
MEM_ADDR_CMD10MEM_ADDR_CMD11
CLK_50
MEM_DMA2
ENET_MDCENET_INTn
ENET_MDIO
S5_MSEL3
USB_FPGA_CLK
CLK_EMI_PCLK_EMI_N
MAX5_CLK
FMCA_CLK_M2C_P0FMCA_CLK_M2C_N0
FMCA_CLK_M2C_P1FMCA_CLK_M2C_N1
FMCA_LA_RX_CLK_P0FMCA_LA_RX_CLK_N0
FMCA_LA_RX_CLK_P1FMCA_LA_RX_CLK_N1
FMCB_CLK_M2C_P0FMCB_CLK_M2C_N0FMCB_LA_RX_CLK_P0FMCB_LA_RX_CLK_N0
FMCB_CLK_M2C_N1FMCB_CLK_M2C_P1
FMCB_LA_RX_CLK_N1FMCB_LA_RX_CLK_P1
MEM_DQB19 MEM_DQB20MEM_DQSB_P1MEM_DQSB_N1
MEM_ADDR_CMD6MEM_ADDR_CMD7MEM_ADDR_CMD13MEM_ADDR_CMD14
ENET_RESETn
MEM_DQA20
MEM_DQSA_P1MEM_DQSA_N1
FLASH_RDYBSYn1
S5_MSEL3S5_MSEL4
SMA_CLK_OUT
USB_FULLUSB_EMPTYUSB_SCLUSB_SDA
MEM_DMB1
MEM_DQB22
MEM_DQA10MEM_DQA11
MEM_DQA18MEM_DQA22
ENET_TX_PENET_TX_N
CLK_125_PCLK_125_NENET_RX_PENET_RX_N
A10_VCCIO_1.8V
CLK_509
MEM_DQB[33:0]4,17
MEM_DMB[3:0]4,17
MEM_DQSB_P[3:0]4,17
MEM_DQSB_N[3:0]4,17
MEM_ADDR_CMD[31:0]4,17
MEM_DQA[33:0]4,17
MEM_DMA[3:0]4,17
MEM_DQSA_P[3:0]4,17
MEM_DQSA_N[3:0]4,17
CLK_125_P9CLK_125_N9
ENET_RESETn15
FLASH_RDYBSYn113,14
FMCA_LA_RX_CLK_P[1:0]19
FMCA_LA_RX_CLK_N[1:0]19
ENET_MDIO15ENET_MDC15ENET_INTn15
USB_FPGA_CLK25
USB_SDA26
USB_FULL26USB_EMPTY26USB_SCL26
MAX5_CLK13
FMCB_CLK_M2C_P[1:0]20
FMCB_CLK_M2C_N[1:0]20
FMCB_LA_RX_CLK_N[1:0]20
FMCB_LA_RX_CLK_P[1:0]20
CLK_FPGA_B2_P9CLK_FPGA_B2_N9
CLK_FPGA_B3_N9CLK_FPGA_B3_P9
FMCA_CLK_M2C_N[1:0]19
FMCA_CLK_M2C_P[1:0]19
CLK_EMI_P10CLK_EMI_N10
ENET_RX_N15ENET_RX_P15
ENET_TX_P15ENET_TX_N15
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B8 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B8 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B8 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R379 100, 1%
R306 1.00k
R336 100, 1%
R307 1.00kR305 DNI
R448 100, 1%
R383 100, 1%
R378 100, 1%
R308 DNI
R353 100, 1%
R391 100, 1%
BANK-2I
BANK-2J
BANK-2K
BANK-2L
BANK-3A
BANK-3B
BANK-3C
BANK-3D
BANK-3E
BANK-3F
BANK-3G
BANK-3H
ARRIA 10 CONFIGURATION
10AX115F1932C
U28B
CLK_2I_0P,DQ14LAU33
CLK_2J_0P,DQ10LU31
CLK_2K_0P,DQ6LH31
CLK_2L_0P,DQ2LA30
PLL_3A_CLKOUT1P,DQS61RAW23
CLK_3B_0P,DQ58RAY20
CLK_3C_0P,DQ54RBA12
CLK_3D_0P,DQ50RAM18
CLK_3E_0P,DQ46RAB11
CLK_3F_0P,DQ42RJ12
CLK_3G_0P,DQ38RF17
CLK_3H_0P,DQ34RF23
CLK_2I_0N,DQ14LAT33
CLK_2J_0N,DQ10LV31
CLK_2K_0N,DQ6LJ31
CLK_2L_0N,DQ2LA29
PLL_3A_CLKOUT1N,DQSn61RAV23
CLK_3B_0N,DQ58RAY19
CLK_3C_0N,DQ54RBA13
CLK_3D_0N,DQ50RAL18
CLK_3E_0N,DQ46RAC11
CLK_3F_0N,DQ42RK12
CLK_3G_0N,DQ38RG17
CLK_3H_0N,DQ34RG23
CLK_2I_1P,DQ13LAR36
CLK_2J_1P,DQ9LAG31
CLK_2K_1P,DQ5LF34
CLK_2L_1P,DQ1LG26
PLL_3A_CLKOUT0P,DQ62RBC23
CLK_3B_1P,DQ57RAV15
CLK_3C_1P,DQ53RAT10
CLK_3D_1P,DQ49RAF13
CLK_3E_1P,DQ45RR14
CLK_3F_1P,DQ41RC11
CLK_3G_1P,DQ37RG18
CLK_3H_1P,DQ33RC23
CLK_2I_1N,DQ13LAR37
CLK_2J_1N,DQ9LAH31
CLK_2K_1N,DQ5LF35
CLK_2L_1N,DQ1LH26
PLL_3A_CLKOUT0N,DQ62RBD23
CLK_3B_1N,DQ57RAU15
CLK_3C_1N,DQ53RAR11
CLK_3D_1N,DQ49RAG13
CLK_3E_1N,DQ45RP14
CLK_3F_1N,DQ41RC10
CLK_3G_1N,DQ37RF18
CLK_3H_1N,DQ33RD23
PLL_2I_CLKOUT0P,DQ14LAT32
PLL_2J_CLKOUT0P,DQ10LW34
PLL_2K_CLKOUT0P,DQ6LM33
PLL_2L_CLKOUT0P,DQ2LB31
CLK_3A_1P,DQ61RAV24
PLL_3B_CLKOUT0P,DQ58RAW21
PLL_3C_CLKOUT0P,DQ54RBB10
PLL_3D_CLKOUT0P,DQ50RAM16
PLL_3E_CLKOUT0P,DQ46RAA13
PLL_3F_CLKOUT0P,DQ42RK11
PLL_3G_CLKOUT0P,DQ38RE16
PLL_3H_CLKOUT0P,DQ34RE24
PLL_2I_CLKOUT0N,DQ14LAU32
PLL_2J_CLKOUT0N,DQ10LY34
PLL_2K_CLKOUT0N,DQ6LL33
PLL_2L_CLKOUT0N,DQ2LB30
CLK_3A_1N,DQ61RAW24
PLL_3B_CLKOUT0N,DQ58RAY21
PLL_3C_CLKOUT0N,DQ54RBA10
PLL_3D_CLKOUT0N,DQ50RAN16
PLL_3E_CLKOUT0N,DQ46RY12
PLL_3F_CLKOUT0N,DQ42RJ11
PLL_3G_CLKOUT0N,DQ38RE17
PLL_3H_CLKOUT0N,DQ34RF24
PLL_2I_CLKOUT1P,DQS13LAN33
PLL_2J_CLKOUT1P,DQS9LAJ32
PLL_2K_CLKOUT1P,DQS5LH33
PLL_2L_CLKOUT1P,DQS1LH28
CLK_3A_0P,DQ62RBD24
PLL_3B_CLKOUT1P,DQS57RAV16
PLL_3C_CLKOUT1P,DQS53RAP12
PLL_3D_CLKOUT1P,DQS49RAE11
PLL_3E_CLKOUT1P,DQS45RU13
PLL_3F_CLKOUT1P,DQS41RC14
PLL_3G_CLKOUT1P,DQS37RE20
PLL_3H_CLKOUT1P,DQS33RC25
PLL_2I_CLKOUT1N,DQSn13LAM33
PLL_2J_CLKOUT1N,DQSn9LAJ31
PLL_2K_CLKOUT1N,DQSn5LG32
PLL_2L_CLKOUT1N,DQSn1LJ27
CLK_3A_0N,DQ62RBC24
PLL_3B_CLKOUT1N,DQSn57RAU16
PLL_3C_CLKOUT1N,DQSn53RAR12
PLL_3D_CLKOUT1N,DQSn49RAD12
PLL_3E_CLKOUT1N,DQSn45RT13
PLL_3F_CLKOUT1N,DQSn41RD14
PLL_3G_CLKOUT1N,DQSn37RF20
PLL_3H_CLKOUT1N,DQSn33RB25
R349 100, 1%
R450 100, 1%
R406 100, 1%
R333 100, 1%
R369 100, 1%
J71
2 3 4 5
R403 100, 1%
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Clocks
CLK_SEL = LOW selects (CLK0p/n) Si570 inputCLK_SEL = HIGH selects (CLK1p/n) SMA input
Si570 Programmable OscillatorUse Clock Control GUI(Default 100MHz)I2C Address 00 HEX
LVDS OUTPUT
LVDS OUTPUT
Populated with Si516. FS Control on DIPSWITCHFS=0: 148.35MHzFS=1: 148.50MHzI2C only available if Si571 is populated. From FPGA
CLKIN_50
CLK1nCLKIN_SMA CLKIN_SMA_CMOS
CLOCK_SDACLOCK_SCL
100M_OSC_N100M_OSC_P
Si570_EN
CLOCK_I2C_SDA
CLOCK_I2C_SCL
REFCLK4_CPREFCLK4_CN
REFCLK1_CPREFCLK1_CN
OEA
OEB
REFCLK_SDI_CP
REFCLK_SDI_CN
SI571_VCONTROL
CLOCK_I2C_SDA
CLOCK_I2C_SCL
CLK1n
CLOCK_I2C_SDACLOCK_I2C_SCL
100M_OSC_CP
100M_OSC_CN
SI516_FS
1.8V
1.8V
1.8V
2.5V
Si53311_VDD
Si53311_VDD
2.5V_Si570
Si53311_VDD
2.5V_Si516
2.5V
2.5V
2.5V
2.5V
1.8V
2.5V 1.8V
1.8V
2.5V
2.5V
MV_CLK_5013CLK_508
CLK50_EN 13
SI570_EN 13
CLK_FPGA_B2_P8CLK_FPGA_B2_N8
CLK_FPGA_B3_P8CLK_FPGA_B3_N8
REFCLK4_P12REFCLK4_N12
REFCLK1_P11REFCLK1_N11
SDI_CLK148_DOWN 6SDI_CLK148_UP 6
SI516_FS 13,24
REFCLK_SDI_N11
REFCLK_SDI_P11
CLK125_EN 13 CLK_125_P8
CLK_125_N8
CLK_SEL 13,24
CLOCK_I2C_SCL10,13CLOCK_I2C_SDA10,13
CLOCK_SDA4CLOCK_SCL4
A10_SI516_FS6
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B9 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B9 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B9 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R56 10.0K
L15
BLM15AG221SN1
X3
SI570
OE2
NC1
GND3
CLK+4
CLK-5
VCC6
SDA7
SCL8
R4444.99K
R207 100, 1%
X1
Si516_148.5M_148.35M
FS(OE)2
VC1
GND3
CLK+4
CLK-5
VDD6
NC(SDA)7
NC(SCL)8
L9
BLM15AG221SN1
C680
1uF
C71
0.1uF
C619
10uF
R52 22.0
C214 0.1uF
C603
0.1uF
C239 0.1uF
C64
2.2uF
C700
10uF
C164
0.1uF
C689
0.1uF
R196 4.70K
R947DNI
J6 1
2345
C155 0.1uF
L8
DNI
C209 0.1uF
R435 4.70K
C573
10uF
R446 180K
C701
1uF
C572
0.1uF
C100
10uF
C210
1uF
C618
0.1uF
C225 0.1uF
C604
1.0nF
U53
SL18860DC
CLKIN3 CLKOUT1
8
CLKOUT29
GND1
CLKOUT310
VDD2
OE16
OE_OSC4
OE27
OE35
X2
125.0MHz
EN1
NC2
GND3
OUT4
OUTn5
VCC6
C101
0.1uF
C208 0.1uF
R524 4.70K
C238 0.1uF
BANK A OUTPUT
BANK B OUTPUT
BANK A CONTROL
BANK BCONTROL
U42
Si53301_11
DIVA1
SFOUTA[1]2 SFOUTA[0]3
Q04Q05
GN
D6
VD
D7
CLK_SEL8
NC
19
CLK010
CLK011
OEA12
OEB13
CLK114
CLK115
NC
216
VR
EF
17
VD
DO
A18
VD
DO
B19
Q520Q521
SFOUTB[0]22
SFOUTB[1]23
DIVB24
Q425Q426
Q327Q328
Q229Q230
Q131Q132
GN
D_P
AD
33
C679 0.1uF
C574
1uF
X4
50MHz
VCC4
GND2
OUT3
EN1
R511 4.70KL22
BLM15AG221SN1
R445 180K
C165
0.1uF
R452 4.70K
R195 4.70K
C154 0.1uF
U60
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PLL (2)
LVDS
302.083333MHz
625MHz
625MHz
100MHz
1.8V
2.5V
644.53125MHz
133.33MHz
644.53125MHz
270MHzLVDS
Si5338 Programmable Oscillator Use Clock Control GUI (Defaults CLK[0:3] = 270MHz, 644.53125MHz, 644.53125MHz, 133.33MHz)I2C Address 7A HEX
Si5338 Programmable Oscillator Use Clock Control GUI (Defaults CLK[0:3] = 100MHz, 625MHz, 625MHz, 302.083333MHz)I2C Address 7C HEX
CLOCK_I2C_SDA
CLOCK_I2C_SCL
1.8V_PLL
1.8V_PLL
REFCLK_SMA_CPREFCLK_SMA_CN
REFCLK_FMCB_CPREFCLK_FMCB_CN
REFCLK_FMCA_CPREFCLK_FMCA_CN
PCIE_OB_REFCLK_CPPCIE_OB_REFCLK_CN
REFCLK_SFP_CPREFCLK_SFP_CN
REFCLK_QSFP_CPREFCLK_QSFP_CN
REFCLK_DP_CPREFCLK_DP_CN
CLOCK_I2C_SDA
CLOCK_I2C_SCL
1.8V_PLL2
1.8V
1.8V
REFCLK_SMA_P11REFCLK_SMA_N11
REFCLK_FMCB_P12REFCLK_FMCB_N12
REFCLK_FMCA_P12REFCLK_FMCA_N12
PCIE_OB_REFCLK_P11PCIE_OB_REFCLK_N11
CLOCK_SDA4,9CLOCK_SCL4,9
CLOCK_I2C_SCL9,13CLOCK_I2C_SDA9,13
REFCLK_SFP_N11REFCLK_SFP_P11
CLK_EMI_N8CLK_EMI_P8
REFCLK_QSFP_P11REFCLK_QSFP_N11
REFCLK_DP_P11REFCLK_DP_N11
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B10 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B10 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B10 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C489
0.1uF
R81 4.70K
C66 0.1uF
C119 0.1uF
C73 0.1uF
C110 0.1uF
C109 DNI
L14
BLM15AG221SN1
C65 DNI
C488
0.1uF
C59 0.1uF
L13
BLM15AG221SN1
Y325.00MHz
13
24
C359
0.1uF
C102 0.1uF
U14
Si5338A-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
Y225.00MHz
13
24 C348
0.1uF
R106 4.70K
C358
0.1uF
C443
0.1uF
C129 0.1uF
C390
0.1uF
C470
0.1uF
C74 0.1uF
C391
0.1uF
C469
0.1uF
C103 0.1uF
U26
Si5338A-CUSTOM
CLKIN_P1
CLKIN_N2
CLKIN3
I2C_LSB4
FDBK_P5
FDBK_N6
VDD17
VDD224
VDDO311
VDDO215
VDDO116
VDDO020
INTR8
CLK3B9
CLK3A10SCL
12
CLK2B13
CLK2A14
CLK1B17
CLK1A18
SDA19
CLK0B21
CLK0A22
RSVD_GND23
EPAD25
C72 DNI
C130 0.1uF
C118 0.1uF
C357
0.1uF
C58 0.1uF
C94 0.1uF
C111 0.1uF
C117 DNI
C490
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Transceivers Left
QSFP INTERFACE
SDI INTERFACE
SFP+ INTERFACE
DISPLAYPORT INTERFACE
PCIe INTERFACE
SMA INTERFACE
REFCLK1_PREFCLK1_N
SDI_RX_PSDI_RX_N
SDI_TX_PSDI_TX_N
SMA_TX_PSMA_TX_N
QSFP_RX_P0 QSFP_TX_P0QSFP_RX_N0 QSFP_TX_N0
QSFP_RX_P1 QSFP_TX_P1QSFP_TX_N1QSFP_RX_N1
QSFP_TX_P2QSFP_TX_N2
QSFP_TX_N3QSFP_TX_P3
QSFP_RX_P2QSFP_RX_N2
QSFP_RX_P3QSFP_RX_N3
SFP_RX_PSFP_RX_N
SFP_TX_PSFP_TX_N
DP_ML_LANE_P0DP_ML_LANE_N0
DP_ML_LANE_P1DP_ML_LANE_N1
DP_ML_LANE_P2DP_ML_LANE_N2
DP_ML_LANE_N3DP_ML_LANE_P3
PCIE_EDGE_REFCLK_PPCIE_EDGE_REFCLK_N
PCIE_OB_REFCLK_NPCIE_OB_REFCLK_P
REFCLK_SFP_NREFCLK_SFP_P
REFCLK_DP_NREFCLK_DP_P
REFCLK_QSFP_PREFCLK_QSFP_N
REFCLK_SDI_PREFCLK_SDI_N
REFCLK_SMA_NREFCLK_SMA_P
PCIE_RX_P5PCIE_RX_N5
PCIE_RX_P6PCIE_RX_N6
PCIE_RX_P7PCIE_RX_N7
PCIE_RX_N4PCIE_RX_P4
PCIE_RX_N2PCIE_RX_P2
PCIE_RX_N3PCIE_RX_P3
PCIE_RX_P0PCIE_RX_N0
PCIE_RX_N1PCIE_RX_P1
PCIE_TX_P5PCIE_TX_N5
PCIE_TX_P6PCIE_TX_N6
PCIE_TX_N7PCIE_TX_P7
PCIE_TX_N4PCIE_TX_P4
PCIE_TX_N2PCIE_TX_P2
PCIE_TX_N3PCIE_TX_P3
PCIE_TX_P0PCIE_TX_N0
PCIE_TX_N1PCIE_TX_P1
REFCLK1_N9REFCLK1_P9
REFCLK_SDI_P9REFCLK_SDI_N9SDI_RX_P23SDI_RX_N23
SDI_TX_N23SDI_TX_P23
QSFP_RX_P[3:0]21QSFP_RX_N[3:0]21
QSFP_TX_N[3:0]21QSFP_TX_P[3:0]21
SFP_TX_N22SFP_TX_P22
SFP_RX_P22SFP_RX_N22
DP_ML_LANE_P[3:0]18DP_ML_LANE_N[3:0]18
PCIE_EDGE_REFCLK_N3PCIE_EDGE_REFCLK_P3
PCIE_RX_P[7:0]3PCIE_RX_N[7:0]3
PCIE_TX_N[7:0]3PCIE_TX_P[7:0]3
PCIE_OB_REFCLK_P10PCIE_OB_REFCLK_N10
REFCLK_DP_N10REFCLK_DP_P10
REFCLK_SFP_N10REFCLK_SFP_P10
REFCLK_QSFP_N10REFCLK_QSFP_P10
REFCLK_SMA_P10REFCLK_SMA_N10
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B11 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B11 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B11 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
ARRIA 10 - LEFT TRANSCEIVER BANK-1C
10AX115F1932C
U28F
REFCLK_GXBL1C_CHBNAN38
REFCLK_GXBL1C_CHTNAL38
REFCLK_GXBL1C_CHBPAN37
REFCLK_GXBL1C_CHTPAL37
GXBL1C_RX_CH0N,GXBL1C_REFCLK0NAW37
GXBL1C_RX_CH1N,GXBL1C_REFCLK1NBA37
GXBL1C_RX_CH2N,GXBL1C_REFCLK2NAY39
GXBL1C_RX_CH3N,GXBL1C_REFCLK3NAV39
GXBL1C_RX_CH4N,GXBL1C_REFCLK4NAT39
GXBL1C_RX_CH5N,GXBL1C_REFCLK5NAP39
GXBL1C_RX_CH0P,GXBL1C_REFCLK0PAW38
GXBL1C_RX_CH1P,GXBL1C_REFCLK1PBA38
GXBL1C_RX_CH2P,GXBL1C_REFCLK2PAY40
GXBL1C_RX_CH3P,GXBL1C_REFCLK3PAV40
GXBL1C_RX_CH4P,GXBL1C_REFCLK4PAT40
GXBL1C_RX_CH5P,GXBL1C_REFCLK5PAP40
GXBL1C_TX_CH0NBC37
GXBL1C_TX_CH1NBD39
GXBL1C_TX_CH2NBB39
GXBL1C_TX_CH3NBC41
GXBL1C_TX_CH4NBB43
GXBL1C_TX_CH5NBA41
GXBL1C_TX_CH0PBC38
GXBL1C_TX_CH1PBD40
GXBL1C_TX_CH2PBB40
GXBL1C_TX_CH3PBC42
GXBL1C_TX_CH4PBB44
GXBL1C_TX_CH5PBA42
R46410.0K
ARRIA 10 - LEFT TRANSCEIVER BANK-1G
10AX115F1932C
U28J
REFCLK_GXBL1G_CHBNU38
REFCLK_GXBL1G_CHTNR38
REFCLK_GXBL1G_CHBPU37
REFCLK_GXBL1G_CHTPR37
GXBL1G_RX_CH0N,GXBL1G_REFCLK0NR41
GXBL1G_RX_CH1N,GXBL1G_REFCLK1NP39
GXBL1G_RX_CH2N,GXBL1G_REFCLK2NN41
GXBL1G_RX_CH3N,GXBL1G_REFCLK3NM39
GXBL1G_RX_CH4N,GXBL1G_REFCLK4NL41
GXBL1G_RX_CH5N,GXBL1G_REFCLK5NK39
GXBL1G_RX_CH0P,GXBL1G_REFCLK0PR42
GXBL1G_RX_CH1P,GXBL1G_REFCLK1PP40
GXBL1G_RX_CH2P,GXBL1G_REFCLK2PN42
GXBL1G_RX_CH3P,GXBL1G_REFCLK3PM40
GXBL1G_RX_CH4P,GXBL1G_REFCLK4PL42
GXBL1G_RX_CH5P,GXBL1G_REFCLK5PK40
GXBL1G_TX_CH0NK43
GXBL1G_TX_CH1NJ41
GXBL1G_TX_CH2NH43
GXBL1G_TX_CH3NG41
GXBL1G_TX_CH4NF43
GXBL1G_TX_CH5NE41
GXBL1G_TX_CH0PK44
GXBL1G_TX_CH1PJ42
GXBL1G_TX_CH2PH44
GXBL1G_TX_CH3PG42
GXBL1G_TX_CH4PF44
GXBL1G_TX_CH5PE42
ARRIA 10 - LEFT TRANSCEIVER BANK-1D
10AX115F1932C
U28G
REFCLK_GXBL1D_CHBNAJ38
REFCLK_GXBL1D_CHTNAG38
REFCLK_GXBL1D_CHBPAJ37
REFCLK_GXBL1D_CHTPAG37
GXBL1D_RX_CH0N,GXBL1D_REFCLK0NAN41
GXBL1D_RX_CH1N,GXBL1D_REFCLK1NAM39
GXBL1D_RX_CH2N,GXBL1D_REFCLK2NAL41
GXBL1D_RX_CH3N,GXBL1D_REFCLK3NAK39
GXBL1D_RX_CH4N,GXBL1D_REFCLK4NAJ41
GXBL1D_RX_CH5N,GXBL1D_REFCLK5NAH39
GXBL1D_RX_CH0P,GXBL1D_REFCLK0PAN42
GXBL1D_RX_CH1P,GXBL1D_REFCLK1PAM40
GXBL1D_RX_CH2P,GXBL1D_REFCLK2PAL42
GXBL1D_RX_CH3P,GXBL1D_REFCLK3PAK40
GXBL1D_RX_CH4P,GXBL1D_REFCLK4PAJ42
GXBL1D_RX_CH5P,GXBL1D_REFCLK5PAH40
GXBL1D_TX_CH0NAY43
GXBL1D_TX_CH1NAW41
GXBL1D_TX_CH2NAV43
GXBL1D_TX_CH3NAU41
GXBL1D_TX_CH4NAT43
GXBL1D_TX_CH5NAR41
GXBL1D_TX_CH0PAY44
GXBL1D_TX_CH1PAW42
GXBL1D_TX_CH2PAV44
GXBL1D_TX_CH3PAU42
GXBL1D_TX_CH4PAT44
GXBL1D_TX_CH5PAR42
R46310.0K
ARRIA 10 - LEFT TRANSCEIVER BANK-1H
10AX115F1932C
U28K
REFCLK_GXBL1H_CHBNN38
REFCLK_GXBL1H_CHTNL38
REFCLK_GXBL1H_CHBPN37
REFCLK_GXBL1H_CHTPL37
GXBL1H_RX_CH0N,GXBL1H_REFCLK0NH39
GXBL1H_RX_CH1N,GXBL1H_REFCLK1NG37
GXBL1H_RX_CH2N,GXBL1H_REFCLK2NF39
GXBL1H_RX_CH3N,GXBL1H_REFCLK3NE37
GXBL1H_RX_CH4N,GXBL1H_REFCLK4ND39
GXBL1H_RX_CH5N,GXBL1H_REFCLK5NC37
GXBL1H_RX_CH0P,GXBL1H_REFCLK0PH40
GXBL1H_RX_CH1P,GXBL1H_REFCLK1PG38
GXBL1H_RX_CH2P,GXBL1H_REFCLK2PF40
GXBL1H_RX_CH3P,GXBL1H_REFCLK3PE38
GXBL1H_RX_CH4P,GXBL1H_REFCLK4PD40
GXBL1H_RX_CH5P,GXBL1H_REFCLK5PC38
GXBL1H_TX_CH0ND43
GXBL1H_TX_CH1NC41
GXBL1H_TX_CH2NB43
GXBL1H_TX_CH3NA41
GXBL1H_TX_CH4NB39
GXBL1H_TX_CH5NA37
GXBL1H_TX_CH0PD44
GXBL1H_TX_CH1PC42
GXBL1H_TX_CH2PB44
GXBL1H_TX_CH3PA42
GXBL1H_TX_CH4PB40
GXBL1H_TX_CH5PA38
J161
2 3 4 5
ARRIA 10 - LEFT TRANSCEIVER BANK-1E
10AX115F1932C
U28H
REFCLK_GXBL1E_CHBNAE38
REFCLK_GXBL1E_CHTNAC38
REFCLK_GXBL1E_CHBPAE37
REFCLK_GXBL1E_CHTPAC37
GXBL1E_RX_CH0N,GXBL1E_REFCLK0NAG41
GXBL1E_RX_CH1N,GXBL1E_REFCLK1NAF39
GXBL1E_RX_CH2N,GXBL1E_REFCLK2NAE41
GXBL1E_RX_CH3N,GXBL1E_REFCLK3NAD39
GXBL1E_RX_CH4N,GXBL1E_REFCLK4NAC41
GXBL1E_RX_CH5N,GXBL1E_REFCLK5NAB39
GXBL1E_RX_CH0P,GXBL1E_REFCLK0PAG42
GXBL1E_RX_CH1P,GXBL1E_REFCLK1PAF40
GXBL1E_RX_CH2P,GXBL1E_REFCLK2PAE42
GXBL1E_RX_CH3P,GXBL1E_REFCLK3PAD40
GXBL1E_RX_CH4P,GXBL1E_REFCLK4PAC42
GXBL1E_RX_CH5P,GXBL1E_REFCLK5PAB40
GXBL1E_TX_CH0NAP43
GXBL1E_TX_CH1NAM43
GXBL1E_TX_CH2NAK43
GXBL1E_TX_CH3NAH43
GXBL1E_TX_CH4NAF43
GXBL1E_TX_CH5NAD43
GXBL1E_TX_CH0PAP44
GXBL1E_TX_CH1PAM44
GXBL1E_TX_CH2PAK44
GXBL1E_TX_CH3PAH44
GXBL1E_TX_CH4PAF44
GXBL1E_TX_CH5PAD44
R46210.0K
R46110.0K
ARRIA 10 - LEFT TRANSCEIVER BANK-1F
10AX115F1932C
U28I
REFCLK_GXBL1F_CHBNAA38
REFCLK_GXBL1F_CHTNW38
REFCLK_GXBL1F_CHBPAA37
REFCLK_GXBL1F_CHTPW37
GXBL1F_RX_CH0N,GXBL1F_REFCLK0NAA41
GXBL1F_RX_CH1N,GXBL1F_REFCLK1NW41
GXBL1F_RX_CH2N,GXBL1F_REFCLK2NY39
GXBL1F_RX_CH3N,GXBL1F_REFCLK3NV39
GXBL1F_RX_CH4N,GXBL1F_REFCLK4NU41
GXBL1F_RX_CH5N,GXBL1F_REFCLK5NT39
GXBL1F_RX_CH0P,GXBL1F_REFCLK0PAA42
GXBL1F_RX_CH1P,GXBL1F_REFCLK1PW42
GXBL1F_RX_CH2P,GXBL1F_REFCLK2PY40
GXBL1F_RX_CH3P,GXBL1F_REFCLK3PV40
GXBL1F_RX_CH4P,GXBL1F_REFCLK4PU42
GXBL1F_RX_CH5P,GXBL1F_REFCLK5PT40
GXBL1F_TX_CH0NAB43
GXBL1F_TX_CH1NY43
GXBL1F_TX_CH2NV43
GXBL1F_TX_CH3NT43
GXBL1F_TX_CH4NP43
GXBL1F_TX_CH5NM43
GXBL1F_TX_CH0PAB44
GXBL1F_TX_CH1PY44
GXBL1F_TX_CH2PV44
GXBL1F_TX_CH3PT44
GXBL1F_TX_CH4PP44
GXBL1F_TX_CH5PM44
J151
2 3 4 5
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Transceivers Right
FMC INTERFACE
FMCA_DP_M2C_P0FMCA_DP_M2C_N0
FMCA_DP_C2M_P0FMCA_DP_C2M_N0
FMCA_GBTCLK_M2C_P0FMCA_GBTCLK_M2C_N0
FMCA_DP_M2C_P1FMCA_DP_M2C_N1
FMCA_DP_M2C_P2FMCA_DP_M2C_N2
FMCA_DP_M2C_P3FMCA_DP_M2C_N3
FMCA_DP_M2C_P4FMCA_DP_M2C_N4
FMCA_DP_M2C_N5FMCA_DP_M2C_P5
FMCA_DP_M2C_P6FMCA_DP_M2C_N6
FMCA_DP_M2C_P7FMCA_DP_M2C_N7
FMCA_DP_M2C_N8FMCA_DP_M2C_P8
FMCA_DP_M2C_N9FMCA_DP_M2C_P9
FMCA_DP_M2C_N10FMCA_DP_M2C_P10
FMCA_DP_M2C_N11FMCA_DP_M2C_P11
FMCA_DP_M2C_P12FMCA_DP_M2C_N12
FMCA_DP_M2C_P13FMCA_DP_M2C_N13
FMCA_DP_M2C_N14FMCA_DP_M2C_P14
FMCA_DP_M2C_N15FMCA_DP_M2C_P15
FMCA_DP_C2M_P1FMCA_DP_C2M_N1
FMCA_DP_C2M_P2FMCA_DP_C2M_N2
FMCA_DP_C2M_P3FMCA_DP_C2M_N3
FMCA_DP_C2M_P4FMCA_DP_C2M_N4
FMCA_DP_C2M_P5FMCA_DP_C2M_N5
FMCA_DP_C2M_P6FMCA_DP_C2M_N6
FMCA_DP_C2M_P7FMCA_DP_C2M_N7
FMCA_DP_C2M_N8FMCA_DP_C2M_P8
FMCA_DP_C2M_N9FMCA_DP_C2M_P9
FMCA_DP_C2M_N10FMCA_DP_C2M_P10
FMCA_DP_C2M_N11FMCA_DP_C2M_P11
FMCA_DP_C2M_P12FMCA_DP_C2M_N12
FMCA_DP_C2M_P13FMCA_DP_C2M_N13
FMCA_DP_C2M_P14FMCA_DP_C2M_N14
FMCA_DP_C2M_P15FMCA_DP_C2M_N15
FMCB_DP_M2C_P0FMCB_DP_M2C_N0
FMCB_DP_C2M_P0FMCB_DP_C2M_N0
FMCB_DP_C2M_P1FMCB_DP_M2C_P1FMCB_DP_M2C_N1 FMCB_DP_C2M_N1
FMCB_DP_C2M_N2FMCB_DP_C2M_P2FMCB_DP_M2C_P2
FMCB_DP_M2C_N2
FMCB_DP_C2M_N3FMCB_DP_C2M_P3FMCB_DP_M2C_P3
FMCB_DP_M2C_N3
FMCB_DP_C2M_N4FMCB_DP_C2M_P4FMCB_DP_M2C_P4
FMCB_DP_M2C_N4
FMCB_DP_C2M_N5FMCB_DP_C2M_P5FMCB_DP_M2C_P5
FMCB_DP_M2C_N5
FMCB_DP_C2M_P6FMCB_DP_C2M_N6FMCB_DP_M2C_N6
FMCB_DP_M2C_P6
FMCB_DP_C2M_N7FMCB_DP_C2M_P7
FMCB_DP_M2C_N7FMCB_DP_M2C_P7
FMCB_DP_C2M_N8FMCB_DP_C2M_P8
FMCB_DP_M2C_N8FMCB_DP_M2C_P8
FMCB_DP_C2M_N9FMCB_DP_C2M_P9
FMCB_DP_M2C_N9FMCB_DP_M2C_P9
FMCB_DP_C2M_N10FMCB_DP_C2M_P10
FMCB_DP_M2C_N10FMCB_DP_M2C_P10
FMCB_DP_C2M_N11FMCB_DP_C2M_P11
FMCB_DP_M2C_N11FMCB_DP_M2C_P11
FMCB_DP_C2M_N12FMCB_DP_C2M_P12FMCB_DP_M2C_P12
FMCB_DP_M2C_N12
FMCB_DP_C2M_N13FMCB_DP_C2M_P13FMCB_DP_M2C_P13
FMCB_DP_M2C_N13
FMCB_DP_C2M_N14FMCB_DP_C2M_P14FMCB_DP_M2C_P14
FMCB_DP_M2C_N14
FMCB_DP_C2M_N15FMCB_DP_C2M_P15FMCB_DP_M2C_P15
FMCB_DP_M2C_N15
FMCA_GBTCLK_M2C_P1FMCA_GBTCLK_M2C_N1
FMCB_GBTCLK_M2C_P0FMCB_GBTCLK_M2C_N0
FMCB_GBTCLK_M2C_N1FMCB_GBTCLK_M2C_P1
REFCLK_FMCA_PREFCLK_FMCA_N REFCLK_FMCB_N
REFCLK_FMCB_P
REFCLK4_PREFCLK4_N
REFCLK4_N9REFCLK4_P9
FMCA_DP_M2C_P[15:0]19
FMCA_DP_M2C_N[15:0]19
FMCA_DP_C2M_N[15:0]19
FMCA_DP_C2M_P[15:0]19
FMCB_DP_M2C_N[15:0]20
FMCB_DP_M2C_P[15:0]20
FMCB_DP_C2M_P[15:0]20
FMCB_DP_C2M_N[15:0]20
FMCA_GBTCLK_M2C_P[1:0]19FMCA_GBTCLK_M2C_N[1:0]19
FMCB_GBTCLK_M2C_P[1:0]20FMCB_GBTCLK_M2C_N[1:0]20
REFCLK_FMCA_N10REFCLK_FMCA_P10
REFCLK_FMCB_P10REFCLK_FMCB_N10
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B12 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B12 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B12 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
ARRIA 10 - RIGHT TRANSCEIVER BANK-4H
10AX115F1932C
U28Q
REFCLK_GXBR4H_CHBNN7
REFCLK_GXBR4H_CHTNL7
REFCLK_GXBR4H_CHBPN8
REFCLK_GXBR4H_CHTPL8
GXBR4H_RX_CH0N, GXBR4H_REFCLK0NH6
GXBR4H_RX_CH1N, GXBR4H_REFCLK1NG8
GXBR4H_RX_CH2N, GXBR4H_REFCLK2NF6
GXBR4H_RX_CH3N, GXBR4H_REFCLK3NE8
GXBR4H_RX_CH4N, GXBR4H_REFCLK4ND6
GXBR4H_RX_CH5N, GXBR4H_REFCLK5NC8
GXBR4H_RX_CH0P, GXBR4H_REFCLK0PH5
GXBR4H_RX_CH1P, GXBR4H_REFCLK1PG7
GXBR4H_RX_CH2P, GXBR4H_REFCLK2PF5
GXBR4H_RX_CH3P, GXBR4H_REFCLK3PE7
GXBR4H_RX_CH4P, GXBR4H_REFCLK4PD5
GXBR4H_RX_CH5P, GXBR4H_REFCLK5PC7
GXBR4H_TX_CH0ND2
GXBR4H_TX_CH1NC4
GXBR4H_TX_CH2NB2
GXBR4H_TX_CH3NA4
GXBR4H_TX_CH4NB6
GXBR4H_TX_CH5NA8
GXBR4H_TX_CH0PD1
GXBR4H_TX_CH1PC3
GXBR4H_TX_CH2PB1
GXBR4H_TX_CH3PA3
GXBR4H_TX_CH4PB5
GXBR4H_TX_CH5PA7
ARRIA 10 - RIGHT TRANSCEIVER BANK-4G
10AX115F1932C
U28P
REFCLK_GXBR4G_CHBNU7
REFCLK_GXBR4G_CHTNR7
REFCLK_GXBR4G_CHBPU8
REFCLK_GXBR4G_CHTPR8
GXBR4G_RX_CH0N, GXBR4G_REFCLK0NR4
GXBR4G_RX_CH1N, GXBR4G_REFCLK1NP6
GXBR4G_RX_CH2N, GXBR4G_REFCLK2NN4
GXBR4G_RX_CH3N, GXBR4G_REFCLK3NM6
GXBR4G_RX_CH4N, GXBR4G_REFCLK4NL4
GXBR4G_RX_CH5N, GXBR4G_REFCLK5NK6
GXBR4G_RX_CH0P, GXBR4G_REFCLK0PR3
GXBR4G_RX_CH1P, GXBR4G_REFCLK1PP5
GXBR4G_RX_CH2P, GXBR4G_REFCLK2PN3
GXBR4G_RX_CH3P, GXBR4G_REFCLK3PM5
GXBR4G_RX_CH4P, GXBR4G_REFCLK4PL3
GXBR4G_RX_CH5P, GXBR4G_REFCLK5PK5
GXBR4G_TX_CH0NK2
GXBR4G_TX_CH1NJ4
GXBR4G_TX_CH2NH2
GXBR4G_TX_CH3NG4
GXBR4G_TX_CH4NF2
GXBR4G_TX_CH5NE4
GXBR4G_TX_CH0PK1
GXBR4G_TX_CH1PJ3
GXBR4G_TX_CH2PH1
GXBR4G_TX_CH3PG3
GXBR4G_TX_CH4PF1
GXBR4G_TX_CH5PE3
ARRIA 10 - RIGHT TRANSCEIVER BANK-4F
10AX115F1932C
U28O
REFCLK_GXBR4F_CHBNAA7
REFCLK_GXBR4F_CHTNW7
REFCLK_GXBR4F_CHBPAA8
REFCLK_GXBR4F_CHTPW8
GXBR4F_RX_CH0N, GXBR4F_REFCLK0NAA4
GXBR4F_RX_CH1N, GXBR4F_REFCLK1NW4
GXBR4F_RX_CH2N, GXBR4F_REFCLK2NY6
GXBR4F_RX_CH3N, GXBR4F_REFCLK3NV6
GXBR4F_RX_CH4N, GXBR4F_REFCLK4NU4
GXBR4F_RX_CH5N, GXBR4F_REFCLK5NT6
GXBR4F_RX_CH0P, GXBR4F_REFCLK0PAA3
GXBR4F_RX_CH1P, GXBR4F_REFCLK1PW3
GXBR4F_RX_CH2P, GXBR4F_REFCLK2PY5
GXBR4F_RX_CH3P, GXBR4F_REFCLK3PV5
GXBR4F_RX_CH4P, GXBR4F_REFCLK4PU3
GXBR4F_RX_CH5P, GXBR4F_REFCLK5PT5
GXBR4F_TX_CH0NAB2
GXBR4F_TX_CH1NY2
GXBR4F_TX_CH2NV2
GXBR4F_TX_CH3NT2
GXBR4F_TX_CH4NP2
GXBR4F_TX_CH5NM2
GXBR4F_TX_CH0PAB1
GXBR4F_TX_CH1PY1
GXBR4F_TX_CH2PV1
GXBR4F_TX_CH3PT1
GXBR4F_TX_CH4PP1
GXBR4F_TX_CH5PM1
ARRIA 10 - RIGHT TRANSCEIVER BANK-4E
10AX115F1932C
U28N
REFCLK_GXBR4E_CHBNAE7
REFCLK_GXBR4E_CHTNAC7
REFCLK_GXBR4E_CHBPAE8
REFCLK_GXBR4E_CHTPAC8
GXBR4E_RX_CH0N, GXBR4E_REFCLK0NAG4
GXBR4E_RX_CH1N, GXBR4E_REFCLK1NAF6
GXBR4E_RX_CH2N, GXBR4E_REFCLK2NAE4
GXBR4E_RX_CH3N, GXBR4E_REFCLK3NAD6
GXBR4E_RX_CH4N, GXBR4E_REFCLK4NAC4
GXBR4E_RX_CH5N, GXBR4E_REFCLK5NAB6
GXBR4E_RX_CH0P, GXBR4E_REFCLK0PAG3
GXBR4E_RX_CH1P, GXBR4E_REFCLK1PAF5
GXBR4E_RX_CH2P, GXBR4E_REFCLK2PAE3
GXBR4E_RX_CH3P, GXBR4E_REFCLK3PAD5
GXBR4E_RX_CH4P, GXBR4E_REFCLK4PAC3
GXBR4E_RX_CH5P, GXBR4E_REFCLK5PAB5
GXBR4E_TX_CH0NAP2
GXBR4E_TX_CH1NAM2
GXBR4E_TX_CH2NAK2
GXBR4E_TX_CH3NAH2
GXBR4E_TX_CH4NAF2
GXBR4E_TX_CH5NAD2
GXBR4E_TX_CH0PAP1
GXBR4E_TX_CH1PAM1
GXBR4E_TX_CH2PAK1
GXBR4E_TX_CH3PAH1
GXBR4E_TX_CH4PAF1
GXBR4E_TX_CH5PAD1
ARRIA 10 - RIGHT TRANSCEIVER BANK-4C
10AX115F1932C
U28L
REFCLK_GXBR4C_CHBNAN7
REFCLK_GXBR4C_CHTNAL7
REFCLK_GXBR4C_CHBPAN8
REFCLK_GXBR4C_CHTPAL8
GXBR4C_RX_CH0N, GXBR4C_REFCLK0NAW8
GXBR4C_RX_CH1N, GXBR4C_REFCLK1NBA8
GXBR4C_RX_CH2N, GXBR4C_REFCLK2NAY6
GXBR4C_RX_CH3N, GXBR4C_REFCLK3NAV6
GXBR4C_RX_CH4N, GXBR4C_REFCLK4NAT6
GXBR4C_RX_CH5N, GXBR4C_REFCLK5NAP6
GXBR4C_RX_CH0P, GXBR4C_REFCLK0PAW7
GXBR4C_RX_CH1P, GXBR4C_REFCLK1PBA7
GXBR4C_RX_CH2P, GXBR4C_REFCLK2PAY5
GXBR4C_RX_CH3P, GXBR4C_REFCLK3PAV5
GXBR4C_RX_CH4P, GXBR4C_REFCLK4PAT5
GXBR4C_RX_CH5P, GXBR4C_REFCLK5PAP5
GXBR4C_TX_CH0NBC8
GXBR4C_TX_CH1NBD6
GXBR4C_TX_CH2NBB6
GXBR4C_TX_CH3NBC4
GXBR4C_TX_CH4NBB2
GXBR4C_TX_CH5NBA4
GXBR4C_TX_CH0PBC7
GXBR4C_TX_CH1PBD5
GXBR4C_TX_CH2PBB5
GXBR4C_TX_CH3PBC3
GXBR4C_TX_CH4PBB1
GXBR4C_TX_CH5PBA3
ARRIA 10 - RIGHT TRANSCEIVER BANK-4D
10AX115F1932C
U28M
REFCLK_GXBR4D_CHBNAJ7
REFCLK_GXBR4D_CHTNAG7
REFCLK_GXBR4D_CHBPAJ8
REFCLK_GXBR4D_CHTPAG8
GXBR4D_RX_CH0N, GXBR4D_REFCLK0NAN4
GXBR4D_RX_CH1N, GXBR4D_REFCLK1NAM6
GXBR4D_RX_CH2N, GXBR4D_REFCLK2NAL4
GXBR4D_RX_CH3N, GXBR4D_REFCLK3NAK6
GXBR4D_RX_CH4N, GXBR4D_REFCLK4NAJ4
GXBR4D_RX_CH5N, GXBR4D_REFCLK5NAH6
GXBR4D_RX_CH0P, GXBR4D_REFCLK0PAN3
GXBR4D_RX_CH1P, GXBR4D_REFCLK1PAM5
GXBR4D_RX_CH2P, GXBR4D_REFCLK2PAL3
GXBR4D_RX_CH3P, GXBR4D_REFCLK3PAK5
GXBR4D_RX_CH4P, GXBR4D_REFCLK4PAJ3
GXBR4D_RX_CH5P, GXBR4D_REFCLK5PAH5
GXBR4D_TX_CH0NAY2
GXBR4D_TX_CH1NAW4
GXBR4D_TX_CH2NAV2
GXBR4D_TX_CH3NAU4
GXBR4D_TX_CH4NAT2
GXBR4D_TX_CH5NAR4
GXBR4D_TX_CH0PAY1
GXBR4D_TX_CH1PAW3
GXBR4D_TX_CH2PAV1
GXBR4D_TX_CH3PAU3
GXBR4D_TX_CH4PAT1
GXBR4D_TX_CH5PAR3
R33410.0K
R35110.0K
R35010.0KR33510.0K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
LED INTERFACE
PUSH BUTTON INTERFACE
MAXV DIPSWITCH
5M2210 System Controller
VCCINT 1.8V VCCIO 1.8V VCCIO
ON-BOARD USB BLASTER II
FPGA_DCLK
FPGA_nSTATUSFPGA_CONF_DONE
CLK_CONFIG
MV_CLK_50
FM_A21FM_A22
SENSE_SMB_CLK
Si570_EN
CLK125_ENCLOCK_I2C_SDA
CLOCK_I2C_SCL
PGM_SEL
MAX_CONF_DONE
PGM_LED0PGM_CONFIG
SENSE_SMB_DATA
OVERTEMP
TSENSE_ALERTn
OVERTEMPn
MAX_ERRORMAX_LOAD
SI516_FS
FM_D14FM_D15
FM_D10FM_D11FM_D12FM_D13
FM_D8FM_D9
FM_A1FM_A2FM_A3FM_A4FM_A5FM_A6FM_A7
FM_A14
FM_A8FM_A9
FM_A15
FM_A10FM_A11FM_A12FM_A13
FM_A19FM_A20
FM_A18
FM_A16FM_A17
FM_D1FM_D2FM_D3
FM_D0
FM_D4FM_D5FM_D6FM_D7
PGM_LED1PGM_LED2
FACTORY_LOAD
CLK_SELCLK_ENABLE
MAX_RESETn
MAX5_BEn1MAX5_BEn0
MAX5_OEn
MAX5_WEnMAX5_CSn
MAX5_CLK
MAX5_BEn2MAX5_BEn3
USB_M5_CLK
USB_CFG12
CLK_CONFIG
SDI_MF1_AUTO_SLEEP
SDI_MF2_MUTESDI_MF0_BYPASS
CPU_RESETn
MSEL1MSEL2
MSEL0
FMCA_C2M_PGFMCB_C2M_PG
SENSE_SDOSENSE_SDISENSE_SCKSENSE_CS0n
SDI_TX_SD_HDn
USB_CFG2USB_CFG3USB_CFG4USB_CFG5USB_CFG6
USB_CFG7USB_CFG8USB_CFG9USB_CFG10
USB_CFG0
USB_CFG1USB_CFG11
USB_CFG13USB_CFG14
FM_D28FM_D29FM_D30FM_D31
FM_D23
FM_D25FM_D26
FM_D27
FM_D24
FM_D20FM_D21FM_D22
FM_D19
FM_D16FM_D17FM_D18
FPGA_CONFIG_D23FPGA_CONFIG_D22
FPGA_CONFIG_D18FPGA_CONFIG_D19FPGA_CONFIG_D20FPGA_CONFIG_D21
FPGA_CONFIG_D16FPGA_CONFIG_D17
FPGA_CONFIG_D29FPGA_CONFIG_D30
FPGA_nCONFIGFPGA_CONFIG_D31
FPGA_CONFIG_D26FPGA_CONFIG_D27
FPGA_CONFIG_D28
FMCA_PRSNTnFMCB_PRSNTn
FLASH_CEn1
FLASH_OEn
FLASH_ADVn
FLASH_CEn0
FLASH_CLK
FLASH_RESETnFLASH_RDYBSYn0
FLASH_RDYBSYn1
FPGA_CONFIG_D8FPGA_CONFIG_D9FPGA_CONFIG_D10FPGA_CONFIG_D11FPGA_CONFIG_D12FPGA_CONFIG_D13FPGA_CONFIG_D14FPGA_CONFIG_D15
FPGA_CvP_CONFDONEFPGA_PR_ERROR
FM_A25FM_A24FM_A23FLASH_WEn
FPGA_CONFIG_D24
FPGA_CONFIG_D25
FPGA_CONFIG_D1FPGA_CONFIG_D2FPGA_CONFIG_D3
FPGA_CONFIG_D5FPGA_CONFIG_D6
FPGA_CONFIG_D4
FPGA_CONFIG_D0
FPGA_CONFIG_D7
CLK50_EN
FPGA_PR_READY
FPGA_PR_REQUEST
FPGA_PR_DONE
FM_A26
1.8V
1.8V
1.8V1.8V
1.8V
1.8V
1.8V1.8V
2.5V
CPU_RESETn7,24
MAX5_BEn[3:0]6
FLASH_RDYBSYn05,14
MAX5_WEn6
MAX5_OEn6MAX5_CSn6
MAX5_CLK8
M5_JTAG_TCK26M5_JTAG_TDI26
M5_JTAG_TMS26M5_JTAG_TDO26
FPGA_nCONFIG7
CLK_SEL9,24CLK_ENABLE24
SENSE_SMB_CLK29,30OVERTEMP29
FM_A[26:1]5,14
FM_D[31:0]5,14
SENSE_SMB_DATA29,30
FPGA_DCLK7,14FPGA_CONF_DONE7,35FPGA_nSTATUS7
FLASH_CEn05,14
TSENSE_ALERTn29
MV_CLK_509
OVERTEMPn29
FMCA_PRSNTn6,19,24,26FMCB_PRSNTn6,20,24,26
FLASH_ADVn5,14
FLASH_WEn5,14
FLASH_OEn5,14
FLASH_RESETn5,14FLASH_CLK5,14
CLK125_EN9
Si570_EN9CLK50_EN9
FPGA_CONFIG_D[31:0]7
FACTORY_LOAD24SI516_FS9,13,24
PGM_SEL24PGM_CONFIG24MAX_RESETn24
PGM_LED[2:0]24
MAX_ERROR24MAX_LOAD24MAX_CONF_DONE24
FLASH_CEn15,14FPGA_PR_DONE7FPGA_PR_REQUEST7FPGA_PR_READY7FPGA_PR_ERROR7FPGA_CvP_CONFDONE7
MSEL07MSEL17MSEL27
FLASH_RDYBSYn18,14
SI516_FS9,13,24CLOCK_I2C_SDA9,10CLOCK_I2C_SCL9,10
USB_CFG[14:0]26
USB_M5_CLK25
FMCA_C2M_PG19FMCB_C2M_PG20
SENSE_SCK29SENSE_SDI29
SENSE_CS0n29
SENSE_SDO29
SDI_MF2_MUTE4,23
SDI_TX_SD_HDn4,23
SDI_MF0_BYPASS4,23SDI_MF1_AUTO_SLEEP4,23
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B13 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B13 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B13 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C384
0.1uF
C397
0.1uF
X5
125MHz
VCC4
GND2
OUT3
EN1
C483
0.1uF
C141
0.1uF
MAX VBANK3
U16C
5M2210ZF256
IOB3/CLK2J12
IOB3/CLK3H12
DIFFIO_L11PH3
DIFFIO_L10PH2
DIFFIO_R1NC14
DIFFIO_R2PC15
DIFFIO_R3ND15
DIFFIO_R4PF14
DIFFIO_R6PE16
DIFFIO_R10PH14
DIFFIO_R4ND16
DIFFIO_R5NE15
DIFFIO_R7NF16
DIFFIO_R7PG14
DIFFIO_R11NH16
DIFFIO_R10NH15
DIFFIO_R9NG16
DIFFIO_R8NG15
IOB3_24F12
IOB3_21D13
IOB3_22D14
DIFFIO_R22NP14
DIFFIO_R20NM13
DIFFIO_R16NL11
IOB4_33T4
DIFFIO_R6NF15
DIFFIO_R17NL12
DIFFIO_R20PN16
DIFFIO_R13PJ14
DIFFIO_R14NK13
DIFFIO_R14PK16
DIFFIO_R15PK15
DIFFIO_R19PM15
DIFFIO_R18PM16
DIFFIO_R18NL13
DIFFIO_R17PL15
DIFFIO_R19NL14
DIFFIO_R15NK14
DIFFIO_R13NJ15
DIFFIO_R16PL16
DIFFIO_R3PE12
DIFFIO_R12NJ16
DIFFIO_R8PG13
DIFFIO_R9PG12
DIFFIO_R2NE13
DIFFIO_R5PF13
DIFFIO_R21PN15
DIFFIO_R21NN14
IOB3_23F11
DIFFIO_R22PP15
IOB3_25K12
IOB3_26M14
DIFFIO_B21PP12
C330
0.1uF
MAX VBANK4
U16D
5M2210ZF256
DIFFIO_L14PJ3
DIFFIO_B6NP7
DIFFIO_B13P/DEV_OEM8
DIFFIO_B8PM7
IOB4_31R4
DIFFIO_B5PR5
IOB4_32T10
DIFFIO_B2NP5
DIFFIO_B1NP4
DIFFIO_B3PR3
DIFFIO_B21NT15
DIFFIO_B19NR13
IOB4_29M12
DIFFIO_B19PT13
DIFFIO_B7NN7
DIFFIO_B10PN8
DIFFIO_B4NN6
DIFFIO_B3NN5
DIFFIO_B18PR12
DIFFIO_B18NP11
IOB3_27N13
DIFFIO_B9NT7
DIFFIO_B22NP13
DIFFIO_B20NR14
DIFFIO_B1PR1
DIFFIO_B2PT2
DIFFIO_B11NT9
DIFFIO_B12PR9
IOB1_4K4
DIFFIO_B20PN12
DIFFIO_B17PT12
DIFFIO_B16PP10
DIFFIO_B14NR10
DIFFIO_B14PM10
DIFFIO_B16NR11
DIFFIO_B17NN11
DIFFIO_B15PN10
DIFFIO_B15NT11
DIFFIO_B11PT8
DIFFIO_B10NR8
DIFFIO_B5NM6
IOB4_30N9
DIFFIO_B6PT5
DIFFIO_B12NP9 IOB4_28
M11
DIFFIO_B8NR7
DIFFIO_B9PP8
DIFFIO_B7PR6
DIFFIO_B4PP6
DIFFIO_R1PE14
C401
0.1uF
C426
0.1uF
C458
0.1uF
C427
0.1uF
C425
0.1uF
MAX VBANK1
U16A
5M2210ZF256
DIFFIO_L19PN1
IOB1/CLK0H5
IOB1/CLK1J5
DIFFIO_L9PG1
IOB1_1E2
DIFFIO_L6PF4
DIFFIO_L1NC2
DIFFIO_L3NE4
DIFFIO_L7NF6
DIFFIO_L7PF1
DIFFIO_L2NE3
DIFFIO_L3PD2
DIFFIO_L4PD1
DIFFIO_L2PC3
DIFFIO_L1PD3
DIFFIO_L6NF2
DIFFIO_L4NE5
DIFFIO_L8NG3
DIFFIO_L5PF3
DIFFIO_L21PN3
DIFFIO_L21NP2
DIFFIO_L20PN2
DIFFIO_L20NM3
DIFFIO_L8PG2
DIFFIO_L5NE1
DIFFIO_L19NM4
DIFFIO_L18PL4
DIFFIO_L18NL3
DIFFIO_L17PM1
DIFFIO_L17NM2
DIFFIO_L16PL2
DIFFIO_L16NK3
DIFFIO_L15PK5
DIFFIO_L15NL1
DIFFIO_B13N/DEV_CLRnM9
DIFFIO_L14NK2
DIFFIO_L13PJ4
DIFFIO_L13NK1
DIFFIO_L12PH4
DIFFIO_L12NJ2
DIFFIO_R12PJ13
DIFFIO_L11NJ1
DIFFIO_R11PH13
DIFFIO_L10NG5
DIFFIO_L9NG4
IOB1_2F5
IOB1_3H1
DIFFIO_B22PR16
IOB1_5L5
TMSN4TDOM5TDIL6TCKP3
C353
0.1uF
C398
0.1uF
C343
0.1uF
C456
0.1uF
C457
0.1uF
C128
2.2uF
C455
0.1uF
C400
0.1uF
C385
0.1uF
C399
0.1uF
MAX VPower
U16E
5M2210ZF256
GNDINTF7
GNDINTG6
GNDINTH7
GNDINTH9
GNDIOA1
GNDIOA16
GNDIOB15
GNDIOB2
GNDIOG10
GNDIOG7
GNDIOG8
GNDIOG9
GNDIOK10
GNDIOK7
GNDIOK8
GNDIOK9
GNDIOR15
GNDIOR2
GNDIOT1
GNDIOT16
VCCINTH8VCCINTH10VCCINTG11VCCINTF10
VCCIO1C1
VCCIO1H6
VCCIO1J6
VCCIO1P1
VCCIO2A14
VCCIO2A3
VCCIO2F8
VCCIO2F9
VCCIO3C16
VCCIO3H11
VCCIO3J11
VCCIO3P16
VCCIO4L8
VCCIO4L9
VCCIO4T14
VCCIO4T3
GNDINTJ10
VCCINTJ7
VCCINTL7
GNDINTJ8
GNDINTK11
VCCINTK6VCCINTJ9
GNDINTL10
GNDIOT6
C383
0.1uF
MAX VBANK2
U16B
5M2210ZF256
DIFFIO_T9PB8
DIFFIO_T9NA8
IOB2_7A15
DIFFIO_T16NB13
DIFFIO_T18NB16
DIFFIO_T15PE11
IOB2_11B10
DIFFIO_T6NE7
DIFFIO_T5PA5
IOB2_9A4
DIFFIO_T4PE6
DIFFIO_T17NB14
DIFFIO_T3PB4
IOB2_6A13
DIFFIO_T18PC13
DIFFIO_T2NC4
DIFFIO_T2PC5
DIFFIO_T1NB1
IOB2_15C6
DIFFIO_T7NB7
IOB2_10A6
DIFFIO_T3ND6
DIFFIO_T16PC11
DIFFIO_T8NA7
DIFFIO_T5ND7
DIFFIO_T15NB12
DIFFIO_T14PB11
DIFFIO_T14NA12
DIFFIO_T13PE10
DIFFIO_T13NA11
DIFFIO_T12PA10
IOB2_14C12
DIFFIO_T10NE9
IOB2_13C10
DIFFIO_T10PA9
DIFFIO_T17PD12
IOB2_8A2
DIFFIO_T1PD4
DIFFIO_T4NB5
IOB2_16C7
DIFFIO_T6PB6
DIFFIO_T12NC9
IOB2_12B3
DIFFIO_T11PB9
DIFFIO_T11ND9
DIFFIO_T8PD8
DIFFIO_T7PC8
IOB2_17D10
IOB2_18D11
IOB2_19D5
IOB2_20E8
C402
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FLASHFM BUS
- When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software.- When using dual x16 flash devices for an equivalent x32 (x16||x16) flash device a word consists of 32 data bits so addressing starts with FM_A1 mapped to address bit 2 in software.
FLASH 1-Gbit FLASH 1-Gbit
FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3FPGA_DCLKFPGA_nCSO
FM_A17
FM_A2
FM_D15
FM_A21
FM_A6
FM_A1
FM_D0
FM_D4
FLASH_RDYBSYn1
FM_A25
FM_A10
FM_D8
FLASH_WEnFLASH_OEn
FLASH_WPn FLASH_WPnFLASH_ADVn
FLASH_CLK
FLASH_RESETn
FM_A14
FM_D12
FM_A18
FM_A3
FM_D1
FM_A22
FM_A7
FM_D5
FLASH_WEn
FLASH_RESETn
FLASH_RDYBSYn0
FLASH_WPn
FM_A11
FM_A17
FM_A25
FM_A1
FM_A6
FM_A21
FM_A2
FM_A22
FM_A3
FM_A18
FM_A14
FM_A10
FM_A23
FM_A4
FM_A19
FM_A15
FM_A11
FM_A7
FM_A5
FM_A20
FM_A16
FM_A12
FM_A8
FM_A13
FM_A9
FM_A24
FM_D9
FM_A15
FM_D13
FM_A19
FM_A4
FM_D2
FM_D31
FM_D19
FM_D22
FM_D27
FM_D21
FM_D26
FM_D20
FM_D25
FM_D29
FM_D17
FM_D23
FM_D28
FM_D16
FM_D30
FM_D18
FM_D24
FM_A23
FM_A8
FM_D6
FM_A12
FM_D10
FM_A16
FM_D14
FM_A20
FM_A26
FM_A5
FM_D3
FM_A26
FM_A24
FM_A9
FM_D7
FM_A13
FM_D11
1.8V
1.8V
1.8V
1.8V
1.8V 1.8V
1.8V
1.8V1.8V
1.8V
1.8V
1.8V
FPGA_AS_DATA07FPGA_AS_DATA17FPGA_AS_DATA27FPGA_AS_DATA37
FPGA_DCLK 7,13FPGA_nCSO 7
FLASH_CLK 5,13
FLASH_OEn 5,13FLASH_CEn0 5,13FLASH_RESETn 5,13
FLASH_CEn1 5,13
FLASH_ADVn 5,13FLASH_WEn 5,13
FLASH_RDYBSYn18,13
FM_A[26:1] 5,13
FLASH_RDYBSYn05,13
FM_D[31:0] 5,13
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B14 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B14 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B14 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C311
0.1uF
R437 DNI
R286 10.0K
U29
EPCQ1024L
S#C2 DQ1
D2
W#/VPP/DQ2C4
VSSB3
DQ0D3
CB2
HOLD#/DQ3D4
VCCB4
NC1A2
NC2A3
NC3A4
NC4A5
NC5B1
NC6B5
NC7C1
NC8C3
NC9C5
NC10D1
NC11D5
NC12E1
NC13E2
NC14E3
NC15E4
NC16E5
PC28FxxxP30B85FLASH
U5
PC28F00AG18
A1A1
A2B1
A3C1
A4D1
A5D2
A6A2
A7C2
A8A3
A9B3
A10C3
A11D3
A12C4
A13A5
A14B5
A15C5
A16D7
A17D8
A18A7
A19B7
A20C7
A21C8
A22A8
NC(64M)/A23G1
CE#B4
OE#F8
WE#G8
WP#C6
VCCA6
RESET#D4
VCCH3
D0F2
D1E2
D2G3
D3E4
D4E5
D5G5
D6G6
D7H7
D8E1
D9E3
D10F3
D11F4
D12F5
D13H5
D14G7
D15E7
WAITF7
GNDB2
GNDH4GNDH2
CLKE6
ADV#F6
NC/A26(1G)B8
RFU3E8RFU2F1RFU1G2RFU0H1
NC(64M,128M)/A24H8
NC/A25(512M)B6
VPPA4
VCCQD6VCCQD5
VCCQG4
GNDH6
R278 10.0KC322
0.1uF
PC28FxxxP30B85FLASH
U4
PC28F00AG18
A1A1
A2B1
A3C1
A4D1
A5D2
A6A2
A7C2
A8A3
A9B3
A10C3
A11D3
A12C4
A13A5
A14B5
A15C5
A16D7
A17D8
A18A7
A19B7
A20C7
A21C8
A22A8
NC(64M)/A23G1
CE#B4
OE#F8
WE#G8
WP#C6
VCCA6
RESET#D4
VCCH3
D0F2
D1E2
D2G3
D3E4
D4E5
D5G5
D6G6
D7H7
D8E1
D9E3
D10F3
D11F4
D12F5
D13H5
D14G7
D15E7
WAITF7
GNDB2
GNDH4GNDH2
CLKE6
ADV#F6
NC/A26(1G)B8
RFU3E8RFU2F1RFU1G2RFU0H1
NC(64M,128M)/A24H8
NC/A25(512M)B6
VPPA4
VCCQD6VCCQD5
VCCQG4
GNDH6
C313
0.1uF
C294
0.1uF
C566
0.1uF
R414 DNI
C321
0.1uF
R280 10.0K
R413 DNI
C296
0.1uF
R438 DNI
C293
0.1uF
R428 DNI
C292
0.1uF
C320
0.1uF
C319
0.1uF
C295
0.1uF
R407 DNI
R279 10.0K
C547
0.1uF
R266 10.0K C312
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet
SGMII Mode (default)
Place near 88E1111 PHY
88E1111-B2-CAA1C000 EOL88E1111-B2-NDC2C000 Replacement
DVDD = 1.0VDVDD = 1.2V
ENET_DVDD = 1.0V/0.207A
ENET_LED_RX
ENET_LED_LINK10
ENET_LED_TX
ENET_LED_LINK100
ENET_LED_LINK1000
ENET_2p5V_MDC
ENET_LED_TX
ENET_2p5V_INTn
MDI_P1MDI_N1MDI_P2MDI_N2
ENET_2p5V_RESETn
MDI_P3
ENET_LED_RX
ENET_LED_LINK1000ENET_LED_LINK100ENET_LED_LINK10
MDI_N3
ENET_XTAL_25MHZ
MDI_N0
ENET_RSET
ENET_2p5V_MDIO
MDI_P0MDI_P1MDI_N1MDI_P2MDI_N2MDI_P3MDI_N3
MDI_N0MDI_P0 ENET_LED_RX
ENET_LED_LINK1000
ENET_2p5V_MDIOENET_2p5V_MDCENET_2p5V_INTnENET_2p5V_RESETn
ENET_MDIOENET_MDCENET_INTnENET_RESETn
ENET_LED_LINK10
2.5V
ENET_DVDD
2.5V
2.5V
2.5V
ENET_DVDD
2.5V
2.5V
2.5V
1.8V
1.8V2.5V
2.5V
1.8V
ENET_DVDD
2.5V
5.0V
ENET_TX_N8ENET_TX_P8
ENET_RX_P8ENET_RX_N8
ENET_MDIO8
ENET_RESETn8ENET_INTn8ENET_MDC8
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B15 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B15 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B15 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
X6
25.00MHz
VCC4
GND2
OUT3
EN1
C429
0.1uF
R371 49.9
C432 0.01uF
D26
GREEN_LED
R433 4.70K
R41710.0K
R434 4.70K
J9
HFJ11-1G02E
TD0_P1
TD0_N2
TD1_P3
TD1_N6
TD2_P4
TD2_N5
TD3_P7
TD3_N8
VCC9
GND10
GN
D_T
AB
11G
ND
_TA
B12
C388
0.1uF
R370 49.9
U15B
88E1111
NC113
VSS97
DVDD1
DVDD6
DVDD10
DVDD15
DVDD57
DVDD62
DVDD67
DVDD71
DVDD85
AVDD32
AVDD36
AVDD35
AVDD40
AVDD45
AVDD78
VD
DO
X26
VD
DO
X48
VD
DO
5
VD
DO
21
VD
DO
88
VD
DO
96
VD
DO
H72
VD
DO
H66
VD
DO
H52
NC251
R540
R384 220
R386 220
C433 0.01uF
C461
0.1uF
C404
0.1uF
R387 220
C403
0.1uF
C127
10uF
D27
GREEN_LED
R385 220
R418 DNI
R318 49.9
C386
0.1uF
R356 49.9
R380 49.9
R419 DNI
C462 0.01uF
R354 49.9
R94 15.0K
C587
1uF
R317 49.9
C586
0.01uF
D29
GREEN_LED
U59
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R420 4.70K
C387
0.1uF
U25
LTC3025-1
BIAS1
GND2
ADJ5
OUT4
SHDN6
EP_GND7
IN3
R421 4.70K
C430
0.1uF
D28
GREEN_LED
D30
GREEN_LEDGMII/MII/TBI INTERFACE
TEST
SGMII INTERFACE
JTAGMDI INTERFACE
MGMT
U15A
88E1111
COMA27
RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22
XTAL155
XTAL254
VSSC53
RSET30
SEL_FREQ56
MDI3_P42
MDI3_N43
MDI2_P39
MDI2_N41
MDI1_P33
MDI1_N34
MDI0_P29
MDI0_N31
MDIO24
MDC25
INT_N23
HSDAC_P37
HSDAC_N38
GTX_CLK8
TX_CLK4
TX_EN9
RXCLK2
RX_DV94
CRS84
COL83
S_CLK_P79
S_CLK_N80
S_IN_P82
S_IN_N81
S_OUT_P77
S_OUT_N75
LED_TX68
LED_RX69
LED_DUPLEX70
LED_LINK100073
LED_LINK10074
LED_LINK1076
RXD095
RXD192
RXD293
RXD391
RXD490
RXD589
RXD687
RXD786
RX_ER3
TXD011
TXD112
TXD214
TXD316
TXD417
TXD518
TXD619
TXD720
TX_ER7
TMS46 TDO50 TDI44 TCK49 TRST_N47
C126
1uF
R355 49.9
C431
0.1uF
C597
0.1uF
R388 220
R93
10.0K
C459
0.1uF
C484
2.2uF
C405
0.1uF
C354 0.01uF
R550
C428
0.1uF
R431 DNI
R634.99K
R432 DNI
R864.70K
C460
0.1uF
C569
0.1uF
C507
22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
External Memory Interface Connector Map
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B16 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B16 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B16 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
External Memory Interface - HiLo connector
MEMORY INTERFACE
POWER CONTROL
VDD DEFAULT IS 1.2VVDD_1.2V_SET NOT USED.
VDD_1.8V_SET NOT USEDNO SUPPORTED 1.8V EMIF.
VDDQ_1.1V_SET and VDDQ_1.8V_SET NOT USEDNO SUPPORTED 1.1V or 1.8V EMIF PLANNED.
VDDQ DEFAULT IS 1.2VVDDQ_1.2V_SET NOT USED.
Place nearHILO connectorJ14 VDD pins
Place nearHILO connectorJ14 VDDQ pins
MEM_ADDR_CMD0
VDD_1.25V_SETVDD_1.35V_SETVDD_1.5V_SET
VDDQ_1.25V_SETVDDQ_1.35V_SETVDDQ_1.5V_SET
MEM_DQ_ADDR_CMD0MEM_ADDR_CMD1 MEM_DQ_ADDR_CMD1MEM_ADDR_CMD2 MEM_DQ_ADDR_CMD2MEM_ADDR_CMD3 MEM_DQ_ADDR_CMD3MEM_ADDR_CMD4 MEM_DQ_ADDR_CMD4MEM_ADDR_CMD5 MEM_DQ_ADDR_CMD5MEM_ADDR_CMD6 MEM_DQ_ADDR_CMD6MEM_ADDR_CMD7 MEM_DQ_ADDR_CMD7MEM_ADDR_CMD8 MEM_DQ_ADDR_CMD8MEM_ADDR_CMD9MEM_ADDR_CMD10MEM_ADDR_CMD11MEM_ADDR_CMD12MEM_ADDR_CMD13MEM_ADDR_CMD14MEM_ADDR_CMD15MEM_ADDR_CMD16MEM_ADDR_CMD17MEM_ADDR_CMD18MEM_ADDR_CMD19MEM_ADDR_CMD20MEM_ADDR_CMD21MEM_ADDR_CMD22MEM_ADDR_CMD23MEM_ADDR_CMD24MEM_ADDR_CMD25MEM_ADDR_CMD26MEM_ADDR_CMD27MEM_ADDR_CMD28MEM_ADDR_CMD29MEM_ADDR_CMD30MEM_ADDR_CMD31
MEM_DQS_ADDR_CMD_PMEM_DQS_ADDR_CMD_N
MEM_CLK_PMEM_CLK_N
MEM_DMA0 MEM_DMB0MEM_DMA1 MEM_DMB1MEM_DMA2 MEM_DMB2MEM_DMA3 MEM_DMB3
MEM_DQA0 MEM_DQB0MEM_DQA1 MEM_DQB1MEM_DQA2 MEM_DQB2MEM_DQA3 MEM_DQB3MEM_DQA4 MEM_DQB4MEM_DQA5 MEM_DQB5MEM_DQA6 MEM_DQB6MEM_DQA7 MEM_DQB7MEM_DQA8 MEM_DQB8MEM_DQA9 MEM_DQB9MEM_DQA10 MEM_DQB10MEM_DQA11 MEM_DQB11MEM_DQA12 MEM_DQB12MEM_DQA13 MEM_DQB13MEM_DQA14 MEM_DQB14MEM_DQA15 MEM_DQB15MEM_DQA16 MEM_DQB16MEM_DQA17 MEM_DQB17MEM_DQA18 MEM_DQB18MEM_DQA19 MEM_DQB19MEM_DQA20 MEM_DQB20MEM_DQA21 MEM_DQB21MEM_DQA22 MEM_DQB22MEM_DQA23 MEM_DQB23MEM_DQA24 MEM_DQB24MEM_DQA25 MEM_DQB25MEM_DQA26 MEM_DQB26MEM_DQA27 MEM_DQB27MEM_DQA28 MEM_DQB28MEM_DQA29 MEM_DQB29MEM_DQA30 MEM_DQB30MEM_DQA31 MEM_DQB31MEM_DQA32 MEM_DQB32MEM_DQA33 MEM_DQB33
MEM_DQSA_P0MEM_DQSA_N0
MEM_DQSB_P0MEM_DQSB_N0
MEM_DQSA_P1MEM_DQSA_N1 MEM_DQSB_N1
MEM_DQSB_P1
MEM_DQSB_N2MEM_DQSA_P2MEM_DQSA_N2
MEM_DQSB_P2
MEM_DQSB_N3MEM_DQSA_P3MEM_DQSA_N3
MEM_DQSB_P3
MEM_QKA_P0MEM_QKA_P1
MEM_QKB_P0MEM_QKB_P1
MEM_VDDQ
MEM_VDD 2.5V
3.3V
MEM_VREF
MEM_VDD
MEM_VDDQ
MEM_DQA[33:0]4,8
MEM_DMA[3:0]4,8
MEM_DQSA_P[3:0]4,8
MEM_DQSA_N[3:0]4,8
MEM_DQ_ADDR_CMD[8:0]4
MEM_DQS_ADDR_CMD_P4MEM_DQS_ADDR_CMD_N4
MEM_QKA_P[1:0]4
MEM_DMB[3:0]4,8
MEM_DQB[33:0]4,8
MEM_DQSB_N[3:0]4,8
MEM_DQSB_P[3:0]4,8
MEM_QKB_P[1:0]4
MEM_ADDR_CMD[31:0]4,8
MEM_CLK_P4MEM_CLK_N4
VDD_1.25V_SET34VDD_1.35V_SET3,34VDD_1.5V_SET34
VDDQ_1.25V_SET45
VDDQ_1.5V_SET45VDDQ_1.35V_SET45
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B17 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B17 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B17 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C728
10uF
C732
0.1uF
HiLo EMI - POWER
VDD = 1.2(DEFAULT)(1.2V, 1.25V, 1.35V, 1.8V)
VDDQ = 1.2(DEFAULT)(1.1V,1.2V, 1.25V,1.35V, 1.8V)
VEXT = 2.5V
J14B
HLS-180324-B-12
VDDC7
VDDC9
VDDC11
VDDC13
VDDD6
VDDD8
VDDD10
VDDD12
VDDD14
VDDE7
VDDE9
VDDE11
VDDE13
VDDF6
VDDF8
VDDF10
VDDQF12
VDDQF14
VDDQG7
VDDQG9
VDDQG11
VDDQG13
VDDQH6
VDDQH8
VDDQH10
VDDQH12
VEXTL11
VEXTL13
VEXTM8
VEXTM10
VEXTM12
VEXTM14
VEXTN7
VEXTN9
VEXTN11
VEXTN13
VEXTP8
VEXTP10
VEXTP12
VEXTP14
2.5V/3.3V (VTT)J7
2.5V/3.3V (VTT)J9
2.5V/3.3V (VTT)K6
2.5V/3.3V (VTT)K8
2.5V/3.3V (VTT)L7
2.5V/3.3V (VTT)L9
VREFH14
2.5V/3.3V (VTT)J11
VREFJ13
2.5V/3.3V (VTT)K10
2.5V/3.3V (VTT)K12
VREFK14
VDD_1.2V_SETG15
VDD_1.25V_SETE15
VDD_1.35V_SETJ15
VDD_1.5V_SETL15
VDD_1.8V_SETN16
VDDQ_1.8V_SETR11
VDDQ_1.35V_SETR14 VDDQ_1.25V_SETR15 VDDQ_1.2V_SETP16
VDDQ_1.5V_SETR12
VDDQ_1.1V_SETN15
C730
1uF
HiLo EMI - EMI SIGNALSJ14A
HLS-180324-B-12
MEM_CLK_PV1
MEM_CLK_NV2
MEM_ADDR_CMD0F1
MEM_ADDR_CMD1H1
MEM_ADDR_CMD2F2
MEM_ADDR_CMD3G2
MEM_ADDR_CMD4H2
MEM_ADDR_CMD5J2
MEM_ADDR_CMD6K2
MEM_ADDR_CMD7G3
MEM_ADDR_CMD8J3
MEM_ADDR_CMD9L3
MEM_ADDR_CMD10E4
MEM_ADDR_CMD11F4
MEM_ADDR_CMD12G4
MEM_ADDR_CMD13H4
MEM_ADDR_CMD14J4
MEM_ADDR_CMD15K4
MEM_ADDR_CMD16M1
MEM_ADDR_CMD17M2
MEM_ADDR_CMD18N2
MEM_ADDR_CMD19L4
MEM_ADDR_CMD20P5
MEM_ADDR_CMD21M5
MEM_ADDR_CMD22P1
MEM_ADDR_CMD23R4
MEM_ADDR_CMD24M4
MEM_ADDR_CMD25R3
MEM_ADDR_CMD26L2
MEM_ADDR_CMD27K1
MEM_ADDR_CMD28P2
MEM_ADDR_CMD29N4
MEM_ADDR_CMD30P4
MEM_DQS_ADDR_CMD_PV4
MEM_DQS_ADDR_CMD_NV5
MEM_DQ_ADDR_CMD0R6
MEM_DQ_ADDR_CMD1T1
MEM_DQ_ADDR_CMD2R2
MEM_DQ_ADDR_CMD3T2
MEM_DQ_ADDR_CMD4U2
MEM_DQ_ADDR_CMD5U3
MEM_DQ_ADDR_CMD6T4
MEM_DQ_ADDR_CMD7U4
MEM_DQ_ADDR_CMD8T5
MEM_DMA0B10
MEM_DMA1C4
MEM_DMA2B17
MEM_DMA3F17
MEM_DQA0A4
MEM_DQA1B4
MEM_DQA2B5
MEM_DQA3B6
MEM_DQA4A8
MEM_DQA5B8
MEM_DQA6B9
MEM_DQA7A10
MEM_DQA8B1
MEM_DQA9B2
MEM_DQA10C2
MEM_DQA11C3
MEM_DQA12E3
MEM_DQA13D4
MEM_DQA14D1
MEM_DQA15D2
MEM_DQA16A12
MEM_DQA17B12
MEM_DQA18B13
MEM_DQA19B14
MEM_DQA20C15
MEM_DQA21A16
MEM_DQA22B16
MEM_DQA23A18
MEM_DQA24C16
MEM_DQA25D16
MEM_DQA26E16
MEM_DQA27F16
MEM_DQA28D17
MEM_DQA29C18
MEM_DQA30D18
MEM_DQA31E18
MEM_DQA32E2
MEM_DQA33G16
MEM_DQSA_P0A6
MEM_DQSA_P1A2
MEM_DQSA_P2A14
MEM_DQSA_P3F18
MEM_DQSA_N0A7
MEM_DQSA_N1A3
MEM_DQSA_N2A15
MEM_DQSA_N3G18
MEM_QKA_N0A11
MEM_DQSB_N0J18
MEM_DQSB_N1V18
MEM_DQSB_N2V17
MEM_DQSB_N3V9
MEM_DQSB_P0H18
MEM_DQSB_P1U18
MEM_DQSB_P2V16
MEM_DQSB_P3V8
MEM_QKB_N0M18
MEM_DMB0M16
MEM_DMB1U16
MEM_DMB2U11
MEM_DMB3U6
MEM_DQB0H16
MEM_DQB1J16
MEM_DQB2K16
MEM_DQB3L16
MEM_DQB4H17
MEM_DQB5K17
MEM_DQB6K18
MEM_DQB7L18
MEM_DQB8M17
MEM_DQB9N18
MEM_DQB10P17
MEM_DQB11P18
MEM_DQB12R18
MEM_DQB13T16
MEM_DQB14T17
MEM_DQB15T18
MEM_DQB16U15
MEM_DQB17T14
MEM_DQB18U14
MEM_DQB19V14
MEM_DQB20T13
MEM_DQB21T12
MEM_DQB22U12
MEM_DQB23V12
MEM_DQB24T10
MEM_DQB25U10
MEM_DQB26V10
MEM_DQB27T9
MEM_DQB28T8
MEM_DQB29U8
MEM_DQB30U7
MEM_DQB31V6
MEM_DQB32R16
MEM_DQB33T6
CONFIG0L6
CONFIG1M6
RFU0D5
RFU1F5
RFU2H5
RFU3K5
RFU4N6
RFU5R7
MEM_ADDR_CMD31N3
MEM_QKA_N1B18
MEM_QKB_N1V13
RFU6R8
C729
0.1uF
C733
1uF
C731
10uF
HiLo EMI - GNDJ14C
HLS-180324-B-12
GNDA1
GNDA5
GNDA9
GNDA13
GNDA17
GNDB3
GNDB7
GNDB11
GNDB15
GNDC1
GNDC5
GNDC6
GNDC8
GNDC10
GNDC12
GNDC14
GNDC17
GNDD3
GNDD7
GNDD9
GNDD11
GNDD13
GNDD15
GNDE1
GNDE5
GNDE6
GNDE8
GNDE10
GNDE12
GNDE14
GNDE17
GNDF3
GNDF7
GNDF9
GNDF11
GNDF13
GNDF15
GNDG1
GNDG5
GNDG6
GNDG8
GNDG10
GNDG12
GNDG14
GNDG17
GNDH3
GNDH7
GNDH9
GNDH11
GNDH13
GNDH15
GNDJ1
GNDJ5
GNDJ6
GNDJ8
GNDJ10
GNDJ12
GNDJ14
GNDJ17
GNDK3
GNDK7
GNDK9
GNDK11
GNDK13
GNDK15
GNDL1
GNDL5
GNDL8
GNDL10
GNDL12
GNDL14
GNDL17
GNDM3
GNDM7
GNDM9
GNDM11
GNDM13
GNDM15
GNDN1
GNDN5
GNDN8
GNDN10
GNDN12
GNDN14
GNDN17
GNDP3
GNDP6
GNDP7
GNDP9
GNDP11
GNDP13
GNDP15
GNDR1
GNDR5
GNDR9
GNDR10
GNDR13
GNDR17
GNDT3
GNDT7
GNDT11
GNDT15
GNDU1
GNDU5
GNDU9
GNDU13
GNDU17
GNDV3
GNDV7
GNDV11
GNDV15
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Display Port (x4)DISPLAYPORT INTERFACE
Auxilary Channel -> Bidirctional LVDS 1Mbps/(720Mbps optional).
Quartus IO Standard = BLVDS TX -> DIFF SSTL-1.8 RX -> LVDSFogBugz Case 135234 & 147387
1) TX uses diff sstl18 configuration, which is able to meet peak-to-peak differential voltage and common mode voltage spec for DP.2) RX uses LVDS input, but user need to ensure pin voltage at NF receiver end is <1.9v. a. If the channel is AC couple, then user need to choose the correct Vbias_RX so that Vpin < 1.9v. The spec is 0 – 2v, which is quitewide. Selecting Vbias_Rx at 2v region will cause NF device to have reliability issue. b. If the channel is DC couple, user need to make sure TX common mode voltage + ground reference differences between Tx and Rx will notcause Vpin for NF to be higher than 1.9v.
Usually 3.3V forDP, but Arria 10is 1.8V LVDS.
DP_3p3V_HOT_PLUG
DP_ML_LANE_P0DP_ML_LANE_N0
DP_ML_LANE_P1DP_ML_LANE_N1
DP_ML_LANE_P2DP_ML_LANE_N2
DP_ML_LANE_P3DP_ML_LANE_N3
DP_AUX_CPDP_AUX_CN
DP_AUX_CH_PDP_AUX_CH_N
DP_AUX_CP
DP_3p3V_CONFIG1DP_3p3V_CONFIG2
VBIAS_DP
DP_ML_LANE_CP1DP_ML_LANE_CN1
DP_ML_LANE_CN3DP_ML_LANE_CP3
DP_ML_LANE_CP2DP_ML_LANE_CN2
DP_ML_LANE_CN0DP_ML_LANE_CP0
DP_3p3V_RETURN DP_RTN
DP_AUX_CN
DP_RETURNDP_CONFIG1DP_CONFIG2
DP_HOT_PLUGDP_3p3V_RETURNDP_3p3V_HOT_PLUG
DP_3p3V_CONFIG1DP_3p3V_CONFIG2
3.3V
1.8V
3.3V
3.3V 3.3V
GND_DP
GND_DP GND_DP
3.3V
1.8V
1.8V
1.8V 3.3V
DP_AUX_CH_N4DP_AUX_CH_P4
DP_HOT_PLUG4
DP_ML_LANE_P[3:0]11
DP_ML_LANE_N[3:0]11
DP_RETURN4
DP_CONFIG14DP_CONFIG24
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B18 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B18 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B18 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R589DNI
C40 0.1uFC50 0.1uF
C306
1uF
C51 0.1uF
C290
0.1uF
R27710.0K
R2671M
C39 0.1uF
C30 0.1uF
R268 DNI
VDD GND IO6 IO5
IO3 IO4IO2IO1
D41
824016467
4
81 2 3
56
R285 100K
C56 0.1uF
R269 0
C57 0.1uF
R27549.9
R262 DNI
R265DNI
R26410.0K
C31 0.1uF
C305
0.1uF
F1500mA, Resettable
J5
0472720024
ML_LANE_0P1
ML_LANE_0N3
GND5
ML_LANE_2P7
ML_LANE_2N9
GND11
GND2
ML_LANE_1P4
ML_LANE_1N6
GND8
ML_LANE_3P10
ML_LANE_3N12
CONFIG214 CONFIG113
AUX_CH_P15
GND16
HP_DETECT18
DP_PWR20
AUX_CH_N17
RTN19
MH121
MH222 MH3
23
MH424
C3230.1uF
C291 0.1uF
R271 1MR270 1M
C3310.1uF
C2974.7nF
R263 100K
C304
10uF
VDD GND IO6 IO5
IO3 IO4IO2IO1
D39
824016467
4
81 2 3
56
C310
0.1uF
R27649.9
R281 100K
U47
ST2149B
VL1
IO VL12
IO VL23
IO VL34
IO VL45
GND6
VCC11
IO VCC110
IO VCC29
IO VCC38
IO VCC47
OE12
C309 0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FMC Port A
FMC INTERFACE
CLK2_BIDIR, CLK3_BIDIR,and CLK_DIR only on HighPincount versions.
PG_M2C only on HighPincount versions.
A10_VCCIO_FMCA limited to 1.8V
LVDS P/N NEED TO BE MATCHED BY +/-10ps WITH COMPENSATION ON BOARD FOR PACKAGE DELAYS.
FMCA_DP_C2M_N0FMCA_DP_C2M_P0
FMCA_C2M_PG
FMCA_GA0FMCA_GA1
FMCA_DP_M2C_N0FMCA_DP_M2C_P0
FMCA_CLK_M2C_N1
FMCA_CLK_M2C_P0
FMCA_CLK_M2C_P1FMCA_CLK_M2C_N0
FMCA_M2C_PG
FMCA_GBTCLK_M2C_P0FMCA_GBTCLK_M2C_N0
FMCA_GBTCLK_M2C_N1FMCA_GBTCLK_M2C_P1
FMCA_LA_RX_P0FMCA_LA_RX_N0
FMCA_LA_TX_P0FMCA_LA_TX_N0
FMCA_LA_RX_CLK_N0FMCA_LA_RX_CLK_P0
FMCA_LA_RX_CLK_P1FMCA_LA_RX_CLK_N1
FMCA_JTAG_RST
FMCA_DP_C2M_N10FMCA_DP_C2M_P10
FMCA_DP_M2C_N10FMCA_DP_M2C_P10
FMCA_DP_C2M_P11FMCA_DP_C2M_N11
FMCA_DP_M2C_P11FMCA_DP_M2C_N11
FMCA_DP_C2M_P12FMCA_DP_C2M_N12
FMCA_DP_M2C_P12FMCA_DP_M2C_N12
FMCA_DP_C2M_P13FMCA_DP_C2M_N13
FMCA_DP_M2C_P13FMCA_DP_M2C_N13
FMCA_DP_C2M_P14FMCA_DP_C2M_N14
FMCA_DP_M2C_P14FMCA_DP_M2C_N14
FMCA_DP_C2M_P15FMCA_DP_C2M_N15
FMCA_DP_M2C_P15FMCA_DP_M2C_N15
FMCA_DP_C2M_P1FMCA_DP_C2M_N1
FMCA_DP_M2C_P1FMCA_DP_M2C_N1
FMCA_DP_C2M_P2FMCA_DP_C2M_N2
FMCA_DP_M2C_P2FMCA_DP_M2C_N2
FMCA_DP_C2M_P3FMCA_DP_C2M_N3
FMCA_DP_M2C_P3FMCA_DP_M2C_N3
FMCA_DP_C2M_P4FMCA_DP_C2M_N4
FMCA_DP_M2C_P4FMCA_DP_M2C_N4
FMCA_DP_C2M_P5FMCA_DP_C2M_N5
FMCA_DP_M2C_P5FMCA_DP_M2C_N5
FMCA_DP_C2M_P6FMCA_DP_C2M_N6
FMCA_DP_M2C_P6FMCA_DP_M2C_N6
FMCA_DP_C2M_P7FMCA_DP_C2M_N7
FMCA_DP_M2C_P7FMCA_DP_M2C_N7
FMCA_DP_C2M_P8FMCA_DP_C2M_N8
FMCA_DP_M2C_P8FMCA_DP_M2C_N8
FMCA_DP_C2M_P9FMCA_DP_C2M_N9
FMCA_DP_M2C_P9FMCA_DP_M2C_N9
FMCA_LA_TX_N1FMCA_LA_TX_P1
FMCA_LA_TX_N2FMCA_LA_TX_P2
FMCA_LA_TX_N3FMCA_LA_TX_P3
FMCA_LA_TX_N4FMCA_LA_TX_P4
FMCA_LA_TX_N5FMCA_LA_TX_P5
FMCA_LA_TX_N6FMCA_LA_TX_P6
FMCA_LA_TX_N7FMCA_LA_TX_P7
FMCA_LA_TX_N8FMCA_LA_TX_P8
FMCA_LA_TX_N9FMCA_LA_TX_P9
FMCA_LA_TX_N10FMCA_LA_TX_P10
FMCA_LA_TX_N11FMCA_LA_TX_P11
FMCA_LA_TX_N12FMCA_LA_TX_P12
FMCA_LA_TX_N13FMCA_LA_TX_P13
FMCA_LA_TX_N14FMCA_LA_TX_P14
FMCA_LA_TX_N15FMCA_LA_TX_P15
FMCA_LA_TX_N16FMCA_LA_TX_P16
FMCA_LA_RX_N1FMCA_LA_RX_P1
FMCA_LA_RX_N2FMCA_LA_RX_P2
FMCA_LA_RX_N3FMCA_LA_RX_P3
FMCA_LA_RX_N4FMCA_LA_RX_P4
FMCA_LA_RX_N5FMCA_LA_RX_P5
FMCA_LA_RX_N6FMCA_LA_RX_P6
FMCA_LA_RX_N7FMCA_LA_RX_P7
FMCA_LA_RX_N8FMCA_LA_RX_P8
FMCA_LA_RX_N9FMCA_LA_RX_P9
FMCA_LA_RX_N10FMCA_LA_RX_P10
FMCA_LA_RX_N11FMCA_LA_RX_P11
FMCA_LA_RX_N12FMCA_LA_RX_P12
FMCA_LA_RX_N13FMCA_LA_RX_P13
FMCA_LA_RX_N14FMCA_LA_RX_P14
VREF_FMCA
3.3V
12V
A10_VCCIO_FMCA
3.3V 3.3V
VREF_FMCA
A10_VCCIO_FMCA
FMCA_DP_C2M_P[15:0]12
FMCA_DP_C2M_N[15:0]12
FMCA_JTAG_TDI25
FMCA_DP_M2C_N[15:0]12
FMCA_DP_M2C_P[15:0]12
FMCA_GA[1:0]5
FMCA_JTAG_TMS25
FMCA_JTAG_TCK25
FMCA_JTAG_TDO25
FMCA_PRSNTn 6,13,24,26
FMCA_C2M_PG13
FMCA_3P3V_SCL 5FMCA_3P3V_SDA 5
FMCA_LA_RX_P[14:0]5
FMCA_LA_RX_N[14:0]5
FMCA_LA_TX_P[16:0]5
FMCA_LA_TX_N[16:0]5
FMCA_CLK_M2C_N[1:0]8
FMCA_CLK_M2C_P[1:0]8
FMCA_LA_RX_CLK_P[1:0]8
FMCA_LA_RX_CLK_N[1:0]8
FMCA_GBTCLK_M2C_P[1:0]12FMCA_GBTCLK_M2C_N[1:0]12
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B19 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B19 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B19 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R239DNI
J1C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R240DNI
C261
0.1uF
C262
0.1uF
R249 10.0K
J1B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
J1E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
R246 10.0K
J1F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
J1D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
J1A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
R250 10.0K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FMC Port B
FMC INTERFACE
CLK2_BIDIR, CLK3_BIDIR,and CLK_DIR only on HighPincount versions.
PG_M2C only on HighPincount versions.
A10_VCCIO_FMCB limited to 1.8V
LVDS P/N NEED TO BE MATCHED BY +/-10ps WITH COMPENSATION ON BOARD FOR PACKAGE DELAYS.
FMCB_DP_C2M_N0FMCB_DP_C2M_P0
FMCB_C2M_PG
FMCB_GA0FMCB_GA1
FMCB_DP_M2C_N0FMCB_DP_M2C_P0
FMCB_CLK_M2C_N1
FMCB_CLK_M2C_P0
FMCB_CLK_M2C_P1FMCB_CLK_M2C_N0
FMCB_M2C_PG
FMCB_GBTCLK_M2C_P0FMCB_GBTCLK_M2C_N0
FMCB_GBTCLK_M2C_N1FMCB_GBTCLK_M2C_P1
FMCB_LA_RX_P0FMCB_LA_RX_N0
FMCB_LA_TX_P0FMCB_LA_TX_N0
FMCB_LA_RX_CLK_N0FMCB_LA_RX_CLK_P0
FMCB_LA_RX_CLK_P1FMCB_LA_RX_CLK_N1
FMCB_JTAG_RST
FMCB_DP_M2C_N10FMCB_DP_M2C_P10
FMCB_DP_C2M_P1FMCB_DP_C2M_N1
FMCB_DP_M2C_P1FMCB_DP_M2C_N1
FMCB_DP_C2M_P2FMCB_DP_C2M_N2
FMCB_DP_M2C_P2FMCB_DP_M2C_N2
FMCB_DP_C2M_P3FMCB_DP_C2M_N3
FMCB_DP_M2C_P3FMCB_DP_M2C_N3
FMCB_DP_C2M_P4FMCB_DP_C2M_N4
FMCB_DP_M2C_P4FMCB_DP_M2C_N4
FMCB_DP_C2M_P5FMCB_DP_C2M_N5
FMCB_DP_M2C_P5FMCB_DP_M2C_N5
FMCB_DP_C2M_P6FMCB_DP_C2M_N6
FMCB_DP_M2C_P6FMCB_DP_M2C_N6
FMCB_DP_C2M_P7FMCB_DP_C2M_N7
FMCB_DP_M2C_P7FMCB_DP_M2C_N7
FMCB_DP_C2M_P8FMCB_DP_C2M_N8
FMCB_DP_M2C_P8FMCB_DP_M2C_N8
FMCB_DP_C2M_P9FMCB_DP_C2M_N9
FMCB_DP_M2C_P9FMCB_DP_M2C_N9
FMCB_DP_C2M_N10FMCB_DP_C2M_P10
FMCB_DP_M2C_P11FMCB_DP_M2C_N11
FMCB_DP_M2C_P12FMCB_DP_M2C_N12
FMCB_DP_M2C_P13FMCB_DP_M2C_N13
FMCB_DP_M2C_P14FMCB_DP_M2C_N14
FMCB_DP_M2C_P15FMCB_DP_M2C_N15
FMCB_DP_C2M_N11FMCB_DP_C2M_P11
FMCB_DP_C2M_N12FMCB_DP_C2M_P12
FMCB_DP_C2M_N13FMCB_DP_C2M_P13
FMCB_DP_C2M_N14FMCB_DP_C2M_P14
FMCB_DP_C2M_N15FMCB_DP_C2M_P15
FMCB_LA_TX_N1FMCB_LA_TX_P1
FMCB_LA_TX_N2FMCB_LA_TX_P2
FMCB_LA_TX_N3FMCB_LA_TX_P3
FMCB_LA_TX_N4FMCB_LA_TX_P4
FMCB_LA_TX_N5FMCB_LA_TX_P5
FMCB_LA_TX_N6FMCB_LA_TX_P6
FMCB_LA_TX_N7FMCB_LA_TX_P7
FMCB_LA_TX_N8FMCB_LA_TX_P8
FMCB_LA_TX_N9FMCB_LA_TX_P9
FMCB_LA_TX_N10FMCB_LA_TX_P10
FMCB_LA_TX_N11FMCB_LA_TX_P11
FMCB_LA_TX_N12FMCB_LA_TX_P12
FMCB_LA_TX_N13FMCB_LA_TX_P13
FMCB_LA_TX_N14FMCB_LA_TX_P14
FMCB_LA_TX_P15FMCB_LA_TX_N15
FMCB_LA_TX_N16FMCB_LA_TX_P16
FMCB_LA_RX_N1FMCB_LA_RX_P1
FMCB_LA_RX_N2FMCB_LA_RX_P2
FMCB_LA_RX_N3FMCB_LA_RX_P3
FMCB_LA_RX_N4FMCB_LA_RX_P4
FMCB_LA_RX_N5FMCB_LA_RX_P5
FMCB_LA_RX_N6FMCB_LA_RX_P6
FMCB_LA_RX_N7FMCB_LA_RX_P7
FMCB_LA_RX_N8FMCB_LA_RX_P8
FMCB_LA_RX_N9FMCB_LA_RX_P9
FMCB_LA_RX_N10FMCB_LA_RX_P10
FMCB_LA_RX_N11FMCB_LA_RX_P11
FMCB_LA_RX_N12FMCB_LA_RX_P12
FMCB_LA_RX_N13FMCB_LA_RX_P13
FMCB_LA_RX_N14FMCB_LA_RX_P14
VREF_FMCB
3.3V
12V
3.3V 3.3V
VREF_FMCB
A10_VCCIO_FMCB
A10_VCCIO_FMCB
FMCB_DP_C2M_P[15:0]12
FMCB_DP_C2M_N[15:0]12
FMCB_JTAG_TDI25
FMCB_DP_M2C_N[15:0]12
FMCB_DP_M2C_P[15:0]12
FMCB_GA[1:0]6
FMCB_JTAG_TMS25
FMCB_JTAG_TCK25
FMCB_JTAG_TDO25
FMCB_CLK_M2C_P[1:0]8
FMCB_CLK_M2C_N[1:0]8
FMCB_PRSNTn 6,13,24,26
FMCB_C2M_PG13
FMCB_3P3V_SCL 6FMCB_3P3V_SDA 6
FMCB_LA_RX_CLK_P[1:0]8
FMCB_LA_RX_CLK_N[1:0]8
FMCB_LA_RX_P[14:0]6
FMCB_LA_RX_N[14:0]6
FMCB_LA_TX_P[16:0]6
FMCB_LA_TX_N[16:0]6
FMCB_GBTCLK_M2C_P[1:0]12FMCB_GBTCLK_M2C_N[1:0]12
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B20 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B20 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B20 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
J2D
ASP-134486-01
DP0_C2M_NC3 DP0_C2M_PC2
DP0_M2C_NC7DP0_M2C_PC6
DP1_C2M_NA23 DP1_C2M_PA22
DP1_M2C_NA3DP1_M2C_PA2
DP2_C2M_NA27 DP2_C2M_PA26
DP2_M2C_NA7DP2_M2C_PA6
DP3_C2M_NA31 DP3_C2M_PA30
DP3_M2C_NA11DP3_M2C_PA10
DP4_C2M_NA35 DP4_C2M_PA34
DP4_M2C_NA15DP4_M2C_PA14
DP5_C2M_NA39 DP5_C2M_PA38
DP5_M2C_NA19DP5_M2C_PA18
DP6_C2M_NB37 DP6_C2M_PB36
DP6_M2C_NB17DP6_M2C_PB16
DP7_C2M_NB33 DP7_C2M_PB32
DP7_M2C_NB13DP7_M2C_PB12
DP8_C2M_NB29 DP8_C2M_PB28
DP8_M2C_NB9DP8_M2C_PB8
DP9_C2M_NB25 DP9_C2M_PB24
DP9_M2C_NB5DP9_M2C_PB4
GBTCLK0_M2C_ND5GBTCLK0_M2C_PD4
GBTCLK1_M2C_NB21GBTCLK1_M2C_PB20
J2C
ASP-134486-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11J31
HB_N12F32
HB_N13E31
HB_N14K35
HB_N15J34
HB_N16F35
HB_N17_CCK38
HB_N18J37
HB_N19E34
HB_N2F23
HB_N20F38
HB_N21E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11J30
HB_P12F31
HB_P13E30
HB_P14K34
HB_P15J33
HB_P16F34
HB_P17_CCK37
HB_P18J36
HB_P19E33
HB_P2F22
HB_P20F37
HB_P21E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
J2E
ASP-134486-01
CLK_DIRB1
CLK0_M2C_NH5CLK0_M2C_PH4
CLK1_M2C_NG3CLK1_M2C_PG2
CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34
GA1D35
PG_C2MD1
PG_M2CF1
PRSNT_M2C_LH2
RES0B40
SCLC30 SDAC31
TCKD29TDID30TDOD31TMSD33TRSTD34
3P3VAUXD32
3P3VD40
3P3VC39
3P3VD36
3P3VD38
12P0VC35
12P0VC37
VADJE39
VADJF40
VADJG39
VADJH40
VIO_B_M2CK40
VIO_B_M2CJ39
VREF_B_M2CK1
VREF_A_M2CH1
C260
0.1uF
J2A
ASP-134486-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16G19
LA_N17D21
LA_N18_CCC23
LA_N19H23
LA_N2H8
LA_N20G22
LA_N21H26
LA_N22G25
LA_N23D24
LA_N24H29
LA_N25G28
LA_N26D27
LA_N27C27
LA_N28H32
LA_N29G31
LA_N3G10
LA_N30H35
LA_N31G34
LA_N32H38
LA_N33G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16G18
LA_P17D20
LA_P18_CCC22
LA_P19H22
LA_P2H7
LA_P20G21
LA_P21H25
LA_P22G24
LA_P23D23
LA_P24H28
LA_P25G27
LA_P26D26
LA_P27C26
LA_P28H31
LA_P29G30
LA_P3G9
LA_P30H34
LA_P31G33
LA_P32H37
LA_P33G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
R237DNI
J2B
ASP-134486-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12F14
HA_N13E13
HA_N14J16
HA_N15F17
HA_N16E16
HA_N17_CCK17
HA_N18J19
HA_N19F20
HA_N2K8
HA_N20E19
HA_N21K20
HA_N22J22
HA_N23K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12F13
HA_P13E12
HA_P14J15
HA_P15F16
HA_P16E15
HA_P17_CCK16
HA_P18J18
HA_P19F19
HA_P2K7
HA_P20E18
HA_P21K19
HA_P22J21
HA_P23K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
R247 10.0K
J2F
ASP-134486-01
GNDK2
GNDK3
GNDK6
GNDK9
GNDK12
GNDK15
GNDK18
GNDK21
GNDK24
GNDK27
GNDK30
GNDK33
GNDK36
GNDK39
GNDJ1
GNDJ4
GNDJ5
GNDJ8
GNDJ11
GNDJ14
GNDJ17
GNDJ20
GNDJ23
GNDJ26
GNDJ29
GNDJ32
GNDJ35
GNDJ38
GNDJ40
GNDH3
GNDH6
GNDH9
GNDH12
GNDH15
GNDH18
GNDH21
GNDH24
GNDH27
GNDH30
GNDH33
GNDH36
GNDH39
GNDD2
GNDD3
GNDD6
GNDD7
GNDD10
GNDD13
GNDD16
GNDD19
GNDD22
GNDD25
GNDD28
GNDD37
GNDD39
GNDC1
GNDC4
GNDC5
GNDC8
GNDC9
GNDC12
GNDC13
GNDC16
GNDC17
GNDC20
GNDC21
GNDC24
GNDC25
GNDC28
GNDC29
GNDC32
GNDC33
GNDC36GNDC38GNDC40GNDB2GNDB3GNDB6GNDB7GNDB10GNDB11GNDB14GNDB15GNDB18GNDB19GNDB22GNDB23GNDB26GNDB27GNDB30GNDB31GNDB34GNDB35GNDB38GNDB39GNDA1GNDA4GNDA5GNDA8GNDA9GNDA12GNDA13GNDA16GNDA17GNDA20GNDA21GNDA24GNDA25GNDA28GNDA29GNDA32GNDA33GNDA36GNDA37GNDA40GNDG1GNDG4GNDG5GNDG8GNDG11GNDG14GNDG17GNDG20GNDG23GNDG26GNDG29GNDG32GNDG35GNDG38GNDG40GNDF2GNDF3GNDF6GNDF9GNDF12GNDF15GNDF18GNDF21GNDF24GNDF27GNDF30GNDF33GNDF36GNDF39GNDE1GNDE4GNDE5GNDE8GNDE11GNDE14GNDE17GND
E20
GNDE23
GNDE26
GNDE29
GNDE32
GNDE35
GNDE38
GNDE40
R248 10.0K
R238DNI
C259
0.1uF
R245 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Quad Small Form-factor Pluggable (QSFP) Interface
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.
NOTE 2: Assuming that the SFP RD 100-ohm termination on the Host Board FPGAdevice will be implemented via the on-chip termination circuit.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
NOTE 4: 1uH inductors should have a DC Resistance of less than 0.1-ohm.
Maximum power is <= 3.5W (1.06 A)Maximum inrush current = 1.3A
QSFP INTERFACE
QSFP_VCCR
QSFP_VCC
QSFP_TX_P0
QSFP_TX_P1
QSFP_TX_P2
QSFP_TX_P3
QSFP_TX_N0
QSFP_TX_N1
QSFP_TX_N2
QSFP_TX_N3
QSFP_RX_P0QSFP_RX_N0
QSFP_RX_P1QSFP_RX_N1
QSFP_RX_N2QSFP_RX_P2
QSFP_RX_N3QSFP_RX_P3
QSFP_3p3V_MOD_SELn
QSFP_3p3V_RSTn
QSFP_3p3V_SCLQSFP_3p3V_SDA
QSFP_3p3V_INTERRUPTnQSFP_3p3V_MOD_PRSn
QSFP_3p3V_LP_MODE
QSFP_VCCT
QSFP_SDA
QSFP_MOD_SELnQSFP_RSTnQSFP_SCL
QSFP_MOD_PRSn
QSFP_LP_MODEQSFP_INTERRUPTn
QSFP_3p3V_SDA
QSFP_3p3V_MOD_SELnQSFP_3p3V_RSTnQSFP_3p3V_SCL
QSFP_3p3V_MOD_PRSnQSFP_3p3V_INTERRUPTnQSFP_3p3V_LP_MODE
QSFP_3p3V_SDA
QSFP_3p3V_MOD_SELnQSFP_3p3V_RSTnQSFP_3p3V_SCL
QSFP_3p3V_MOD_PRSnQSFP_3p3V_INTERRUPTnQSFP_3p3V_LP_MODE
QSFP_VCCT
QSFP_VCCR
3.3V
QSFP_VCC
QSFP_VCCTQSFP_VCCR
QSFP_VCC
3.3V
GND_QSFP_CAGE GND_QSFP_CAGE
GND_QSFP_CAGE
1.8V
1.8V3.3V
1.8V
1.8V
3.3V
QSFP_RSTn4QSFP_SCL4QSFP_SDA4
QSFP_MOD_SELn4
QSFP_LP_MODE4
QSFP_MOD_PRSn4QSFP_INTERRUPTn4
QSFP_TX_P[3:0]11
QSFP_TX_N[3:0]11
QSFP_RX_N[3:0]11
QSFP_RX_P[3:0]11
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B21 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B21 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B21 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C705
0.1uF
C6514.7nF
R500 4.70K
C658
0.1uF
C686
0.1uF
L19
1.0uH
1 2
C684
0.1uF
R46510.0K
C662
0.1uF
C656
22uF
R485 4.70K
C673
0.1uF
QSFP_CAGE1C696
1uF
C695
22uF
C685
0.1uF
R517 4.70KR501 4.70K
J18
QSFP_AND_CAGE
CAGE_GND49
CAGE_GND39
CAGE_GND40
CAGE_GND41
CAGE_GND42
CAGE_GND43
CAGE_GND44
CAGE_GND45
CAGE_GND46
CAGE_GND47
CAGE_GND48
CAGE_GND50
INTn28
VCCT29 VCCR10
LP_MODE31
MOD_SELn8
MOD_PRSn27
SCL11
SDA12
VCC30
TD1_N37 TD1_P36
TD2_N2 TD2_P3
TD3_P33
TD3_N34
RD1_N18RD1_P17
RD2_N21RD2_P22
RD3_P14
RD3_N15
GND1
GND4
GND32GND26GND23GND20GND19GND16GND13GND7
GND35
GND38
TD4_P6
TD4_N5
RD4_N24RD4_P25
RSTn9
C663
1uF
U65
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
L21
1.0uH
1 2
R528 4.70K
U68
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
L20
1.0uH
1 2
R516 4.70K
R486 4.70K
C657
22uF
C694
22uF
C674
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP+) Transceiver Cage & Connector
Small Form Factor Pluggable Plus (SFP+) Connector
Level I power is < 1W (0.3 A)Level II power is < 1.5W (0.45 A)Level II Instantaneous peak current per rail 600mA
SFP+ INTERFACE
SFP modules have RS1 connected to GND.If using SFP+ Rate Select pin are defined as: RS1=0 -> TX datarates <= 4.25GB/sRS1=1 -> TX datarates > 4.25GB/s
RS0=0 -> RX datarates <= 4.25GB/sRS0=1 -> RX datarates > 4.25GB/s
NOTE 1: Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.
NOTE 2: Assuming that the SFP RD 100-ohm termination on the Host Board FPGAdevice will be implemented via the on-chip termination circuit.
NOTE 3: DC blocking capacitors are in the module for RX and TX.
SFP_RX_NSFP_RX_P
SFP_SCLSFP_SDA
SFP_TX_PSFP_TX_N
SFP_TX_FAULT
SFP_RS0SFP_RS1
SFP_TX_DISABLE
SFP_MOD0_PRSNTnSFP_RX_LOS
SFP_3p3V_TX_DIS
SFP_3p3V_RS1SFP_3p3V_RS0
SFP_3p3V_TX_FLT
SFP_3p3V_MOD0_PRSNTnSFP_3p3V_RX_LOS
SFP_3p3V_TX_DISSFP_3p3V_TX_FLT
SFP_3p3V_RX_LOS
SFP_3p3V_RS1SFP_3p3V_RS0SFP_3p3V_RS1
SFP_3p3V_RS0
SFP_3p3V_TX_FLT
SFP_3p3V_TX_DIS
SFP_3p3V_MOD0_PRSNTn
SFP_3p3V_RX_LOS
SFP_SCLSFP_SDA
SFP_MOD1_SCLSFP_MOD2_SDA
SFP_SCLSFP_SDA
SFP_3p3V_MOD0_PRSNTn
SFP_VCCR
SFP_VCCT3.3VSFP_VCCR SFP_VCCT
GND_SFP_CAGE GND_SFP_CAGE
3.3V
1.8V
1.8V3.3V
1.8V
1.8V
3.3V
GND_SFP_CAGE
SFP_TX_FAULT4SFP_MOD0_PRSNTn4
SFP_RX_N11SFP_RX_P11
SFP_MOD1_SCL4SFP_MOD2_SDA4
SFP_TX_P11SFP_TX_N11
SFP_RS04SFP_RS14
SFP_RX_LOS4
SFP_TX_DISABLE4
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B22 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B22 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B22 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R429 4.70K
C567
22uF
L16 4.7uH1 2
C568
0.1uF
J12
SFP+_AND_CAGE
CAGE_GND21
CAGE_GND22
CAGE_GND23
CAGE_GND24
CAGE_GND25
CAGE_GND26
CAGE_GND27
CAGE_GND28
CAGE_GND29
CAGE_GND30
CAGE_GND31
CAGE_GND32
CAGE_GND33
CAGE_GND34
VEET1
VEET17
VEET20
RS19
VEER10
VEER11
VEER14
TD_P18
TD_N19
RX_LOS8
TX_FAULT2
VCCT16
VCCR15
RD_P13
RD_N12
TX_DISABLE3
RS07
MOD_ABS6
SCL5
SDA4
CAGE_GND35
CAGE_GND36
CAGE_GND37
CAGE_GND38
CAGE_GND39
CAGE_GND40
MH141
MH242
C6524.7nF
L17 4.7uH1 2
C622
0.1uF
R440 4.70K
U62
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
C625
1uF
R454 4.70K
R439 4.70K
C596
0.1uF
B1
SFP+_CAGE
C623
0.1uF
R453 4.70K
C626
0.1uF
R430 4.70K
C595
22uF
C620
0.1uF
C585
0.1uF
C624
0.1uF
R416 4.70K
R46610.0K
R415 4.70K
C621
1uF
U61
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
SDI Cable Driver, Equalizer, and SMB
75 Ohm Single-Ended Impedance
MODE_SEL = 0 -> HARDWARE MODE
DISABLE SDO1 ->
Layout Notes (M22468) SDI Cable Driver:- The RSET resistor should be located close to pin 5. - Remove GND under pin 5 and the RSET resistor.- The 49.9-ohm resistors should be placed close to device pins 16 and 1 (SDIP/SDIN).
Layout Notes (M22544) SDI Cable Equalizer:- The AGC 33nF capacitor should be located close to the device pins 8 and 9 (AGC+/AGC-). - Clear GND under the AGC 33nF capacitor.
M22468 Pin compatible to:M22428 (Gen2 3G/6G SDI Cable Driver)M23428 (12G Cable Driver)
M22544 Pin Compatible to:M23544 (12G EQ + Reclocker)
Layout Notes:DNI for resistors andcapacitors for GEN2 devices. Minimize stubs in layout.
Pin 4 -> GEN2 EQ Control:Float = no input EQLow = 2dB EQHigh = 4dB EQ
75 Ohm Single-Ended Impedance
100 Ohm Differential Impedance
100 Ohm Differential Impedance
1uF and 10uF for 12G
75-ohm for 12G
4.7uF for 12G
4.7uF for 12G
DNI 75-ohm to SDI_AVDD resitors for 12G.
DNI for 12G
Pull-down for 12G
SDI_IN_P1
SDI_EQIN_P1SDI_EQIN_N1SDI_EQIN_N
SDI_EQIN_P
SDO_NSDO_P
SDI_TX_RSET
SDI_TXCAP_PSDI_TXCAP_N
SDI_SD_HDn
AGCnAGXp
MODE_SEL
MF0_BYPASSMF1_AUTO_SLEEPMF2_MUTE
MF0_BYPASS
MUTEREF
MF2_MUTE
MF1_AUTO_SLEEP
MF3_xSD
MF2_MUTE
MF0_BYPASSMF1_AUTO_SLEEP
SDI_TX
SDI_TXBNC_P
SDI_TXDRV_P
SDI_TXBNC
SDI_TXDRV_N
SDI_SD_HDn
SDI_TX_RSETSDI_TXDRV_TERM
SDI_AVDD
1.8V
1.8V
2.5V
SDI_AVDD3.3V
2.5V_SDI 2.5V
2.5V_SDI
2.5V_SDI
2.5V_SDI
2.5V
SDI_AVDD
SDI_AVDD
SDI_AVDD
1.8V
SDI_AVDD 1.8V
SDI_RX_P11SDI_RX_N11
SDI_TX_N 11
SDI_TX_P 11
SDI_MF2_MUTE4,13
SDI_MF0_BYPASS4,13SDI_MF1_AUTO_SLEEP4,13
SDI_TX_SD_HDn4,13
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B23 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B23 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B23 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
U66
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R194 75
L11 5.6nH1 2
R192 0
C207 4.7uF
R206 75
C683
0.01uF
SDI CABLE DRIVERU41
M22468
SDIN1
AVDD2
AVSS3
NC4
RSET5
MUTE26
AVDD7
AVSS8
SD/XHD9
SDO2N10SDO2P11
SDO1N12SDO1P13
MUTE114
AVSS15
SDIP16
CNTR_PAD17
C703
1uF
C224
0.01uF
L10 3.9nH1 2
R20275
C233 1uF
C237 4.7uF
U73
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
C236
0.1uF
R534 0
L6 DNI
R203
37.4
R205 75
C234 1uF
R191 10.0K
C204 4.7uF
C223 33nF
R499 49.9
R212 75
R526 DNI
R201 75
C671
0.1uF
C681
0.01uF
R163 DNI
C691
0.1uF
C203 4.7uF
C213 4.7uF
L12 3.9nH1 2
R173 10.0K
C682
0.01uF
R204 10.0K
D33
GREEN_LED
R174 DNI
SDI CABLE EQUALIZERU40
M22544VEE_PAD
25
AGC-9
SDO1N17
SDO0P15
MUTEREF11
MF322
AGC+8
SDO1P18
MODE_SEL6
SDO0N14
SDIP3
MF010
xCS13
MF119
VCC20
MF221
SDO1_DISABLE7
VEE5VEE2
VCC24
VEE1
VEE23VEE16VEE12
SDIN4
C702
0.1uF
R535 DNI
C206
0.01uF
C670
1uF
J21SMB
1
2 3 4 5
C235
0.1uF
L7 120 Ohm FB
J20SMB
1
2345
R193 75
R177
49.9
R176
49.9
C247 4.7uF
R175 10.0K
C704
0.1uF
R525 750
C205
0.01uF
R162 DNI
C672
0.1uF
L5120 Ohm FB
C690
0.1uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PUSH BUTTON INTERFACE
LED INTERFACE
User I/O
DIPSWITCH INTERFACE
CLK_ENABLE
MAX_LOAD RES_MAX_LOAD
CLK_SEL
RES_MAX_ERRORMAX_ERROR
USER_DIPSW5
USER_DIPSW1
USER_DIPSW7
USER_DIPSW0
USER_DIPSW2
USER_DIPSW4USER_DIPSW3
USER_DIPSW6
MAX_CONF_DONE RES_CONF_DONEn
PCIE_LED_X4
PCIE_LED_X1
PCIE_LED_X8
PCIE_LED_G2
MAX_RESETn
CPU_RESETn
USER_PB0
USER_PB1
USER_PB2
USER_LED_G0
USER_LED_R0
USER_LED_G1
USER_LED_R1
USER_LED_G2
USER_LED_R2
USER_LED_G3
USER_LED_R3
USER_LED_G4
USER_LED_R4
USER_LED_G5
USER_LED_R5
USER_LED_G6
USER_LED_R6
USER_LED_G7
USER_LED_R7
PGM_SEL
PGM_CONFIG
RESn_PGM_LED1
RESn_PGM_LED2
PGM_LED1
PGM_LED2
PGM_LED0 RESn_PGM_LED0
PCIE_LED_G3
FMCA_RX_LED RESn_FMAC_RX_LED
FMCA_TX_LED RESn_FMCA_TX_LED
FMCA_PRSNTn
FMCB_RX_LED RESn_FMCB_RX_LED
FMCB_TX_LED RESn_FMCB_TX_LED
FMCB_PRSNTn
SPI_SS_DISP
I2C_SDA_DISPI2C_SCL_DISP
I2C_SDA_DISPI2C_SCL_DISP
SPI_SS_DISP
FACTORY_LOADSI516_FS
RZQ_B2K
2.5V
2.5V
1.8V
2.5V
2.5V 2.5V
1.8V
1.8V
2.5V
2.5V
5.0V
1.8V5.0V
1.8V
2.5V
USER_DIPSW[7:0]6
CPU_RESETn7,13
FMCA_RX_LED6FMCA_TX_LED6
USER_PB[2:0]6
USER_LED_R[7:0]6
PCIE_LED_X17
PCIE_LED_X87PCIE_LED_X47
PCIE_LED_G27
FMCA_PRSNTn6,13,19,26
OVERTEMPn13,29
USER_LED_G[7:0]6
PGM_SEL13PGM_CONFIG13MAX_RESETn13
PGM_LED[2:0]13
MAX_ERROR13MAX_LOAD13MAX_CONF_DONE13
CLK_SEL9,13CLK_ENABLE13FACTORY_LOAD13SI516_FS9,13
PCIE_LED_G37
DISP_I2C_SDA4DISP_I2C_SCL4
DISP_SPISS4
CLOCK_SDA4,9
FMCB_TX_LED6FMCB_RX_LED6
FMCB_PRSNTn6,13,20,26
RZQ_B2K4
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B24 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B24 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B24 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
S1
PB Switch1 2
SPACER2
R228 75
R550 22.0
R529 10.0K
R242 22.0
R232 75D36
YELLOW_LED
R12 10.0K
D14 GREEN_LED
D16 RED_LED
RN1B 10K2 15
RN1E 10K5 12
C193
0.1uF
R231 75
R235 22.0
D12 GREEN_LED
G
R
D3 LED_GR1 3
24
R548 22.0
C194
1uF
R229 75
D15 GREEN_LED
R225 75
R224 75
G
R
D7 LED_GR1 3
24
R48
4D
NI
R220 75
R545169, 0.1%
D35YELLOW_LED
R221 75
SPACER1
R233 22.0
RN1C 10K3 14
S5
PB Switch1 2
D1 GREEN_LED
S4
PB Switch1 2
D17 GREEN_LED
R255 22.0
R551 22.0
B2
2x16 LCD I2C
D18 GREEN_LED
R254 22.0
R244 22.0
R537 10.0K
R218 75
RN1F 10K6 11
D11GREEN_LED
R226 75
R230 75
C654
0.1uF
D34YELLOW_LED
S3
PB Switch1 2
G
R
D9 LED_GR1 3
24
G
R
D5 LED_GR1 3
24
RN1H 10K8 9
U64
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R518 10.0K
RN1D 10K4 13
R8 10.0K
R234 22.0
R222 75
R549 22.0
D38YELLOW_LED
OPEN
SW6
DIPSWITCH5
123456
789
10
G
R
D8 LED_GR1 3
24
S7
PB Switch1 2
R7 10.0K
R13 10.0K
R236 22.0
SPACER3
R243 22.0
R48
2D
NI
D13 GREEN_LED
G
R
D6 LED_GR1 3
24
S2
PB Switch1 2
D21GREEN_LED
S6
PB Switch1 2
R536240, 0.1%
RN1A 10K1 16
J10
LCD_HEADER
123456789
10
R219 75
R547 22.0
R9 10.0K
R10 10.0K
SW2
DIPSWITCH8
12345678
161514131211109
D2 GREEN_LED
D37YELLOW_LED
R48
3D
NI
R216 22.0
R217 75 G
R
D10 LED_GR1 3
24
G
R
D4 LED_GR1 3
24
RN1G 10K7 10
R223 75
R11 10.0K
R253 22.0
D20 GREEN_LED
R530 10.0K
R227 75
R241 22.0
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
On-Board USB Blaster II - Part 1 ARRIA 10 USB INTERFACE
JTAG INTERFACE
PLACE NEAR CY7C68013A
IFCLK = 48MHz
CAN WE USE MAX II TO LEVEL TRANSLATE USB_CLK?
MAX V USB INTERFACE
C_USB_MAX_TDOC_USB_MAX_TMS
C_USB_MAX_TCK
C_USB_MAX_TDI
FX2_D_NFX2_D_P
FX2_WAKEUPVBUS_5V
VBUS_5V
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
24M_XTALIN24M_XTALOUT
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_CLK
FX2_RESETn
FX2_SDA MAX_SDA
FX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SCLFX2_SDA
FX2_RESETn
FX2_PD2FX2_PD0C_USB_MAX_TCK
C_USB_MAX_TDIFX2_PD3C_USB_MAX_TDOFX2_PD1C_USB_MAX_TMSFX2_PA0
USB_FPGA_CLK FX2_CLKUSB_M5_CLK
FX2_PA0
FX2_PA2
FX2_CLK
FX2_PA1FX2_PB1
FX2_PA4
FX2_PB2
FX2_PA6FX2_PB5
FX2_SLWRn
FX2_PD5
FX2_PA5
FX2_SCL
FX2_PD6
FX2_PB7
FX2_PD4
FX2_PB4
FMCA_JTAG_TDI
FMCA_JTAG_TDO
FMCA_JTAG_TCK
FMCA_JTAG_TMS
FMCB_JTAG_TMS
FMCB_JTAG_TCK
FMCB_JTAG_TDO
FMCB_JTAG_TDI
FX2_FLAGC
FX2_PA3
FX2_FLAGBFX2_PB0
FX2_SLRDn
FX2_PB6
FX2_PD7
FX2_PB3
FX2_FLAGA
FX2_RESETnMAX_SDA
FX2_PA7
3.3V3.3V
3.3V3.3V
3.3V
3.3V
1.8V 3.3V
1.8V
USB_FPGA_CLK8
FMCA_JTAG_TMS19
FMCA_JTAG_TDI19
FMCA_JTAG_TCK19
FMCA_JTAG_TDO19
FMCB_JTAG_TDI20
FMCB_JTAG_TMS20FMCB_JTAG_TDO20
FMCB_JTAG_TCK20
USB_M5_CLK13
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B25 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B25 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B25 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
U45
TPD2EUSB30D-
2D+1
GND3
R15 2.00K
C284
0.1uF
C267
0.1uF
C274
0.1uF
R16 0
C283
0.1uF
C5050.1uF
R25 0
C270
0.1uF
J23
DNI
11
33
55
77
22
44
66
88
99
1010
R26 0
C266
0.1uF
C2754.7nF
R256
20.0K
Y1
24.00MHz
1 3
24
R502 1.00K
C273
0.1uF
U2
MAX811
GND1
RESET2
VCC4
MR3
C271
0.1uF
MAX IIBANK4
U49D
EPM1270_M256FBGA
IOB4/DEV_CLRnY13
IOB4/DEV_OEW12
IOB4_1U13
IOB4_2U14
IOB4_3U15
IOB4_4U16
IOB4_5U4
IOB4_6U5
IOB4_7U6
IOB4_8U7
IOB4_9U8
IOB4_10V14
IOB4_11V15
IOB4_12V16
IOB4_13V17
IOB4_14V18
IOB4_15V4
IOB4_16V5
IOB4_17V6
IOB4_18V7
IOB4_20W11
IOB4_21W13
IOB4_22W14
IOB4_23W15
IOB4_24W16
IOB4_25W17
IOB4_26W18
IOB4_27W3
IOB4_28W4
IOB4_29W5
IOB4_30W6
IOB4_32W8
IOB4_33W9
IOB4_34Y1
IOB4_35Y10
IOB4_36Y11
IOB4_37Y12
IOB4_38Y14
IOB4_39Y15
IOB4_40Y16
IOB4_41Y17
IOB4_42Y18
IOB4_43Y19
IOB4_44Y2
IOB4_45Y3
IOB4_46Y4
IOB4_47Y5
IOB4_48Y6
IOB4_49Y7
IOB4_50Y8
IOB4_51Y9
IOB4_31W7
IOB4_19W10
VBUSD-D+ID
J3MICRO_USB_CONN
12345
6789
R257 10.0K
C265
12pF
C264
12pF
R2581M
R260 DNI
C5060.1uF
R14 2.00K
R531 1.00K
C268
0.1uF
U58
MAX13042
VLB2
IO_VL4C1 IO_VL3C2 IO_VL2C3 IO_VL1C4
GNDB4
VCCB1
IO_VCC1A4
IO_VCC2A3
IO_VCC3A2
IO_VCC4A1
ENB3
R259100K
C282 0.1uF
C5041uF
R24 0
R23 0
MAX IIBANK1
U49A
EPM1270_M256FBGA
IOB1_21G4
IOB1_22H1
IOB1_23H2
IOB1/GCLK0K1
IOB1/GCLK1L1
IOB1_1B1
IOB1_2C1
IOB1_3C2
IOB1_4C3
IOB1_5C4
IOB1_6D1
IOB1_7D2
IOB1_8D3
IOB1_9D4
IOB1_10E1
IOB1_11E2
IOB1_12E3
IOB1_13E4
IOB1_14F1
IOB1_15F2
IOB1_16F3
IOB1_17F4
IOB1_18G1
IOB1_19G2
IOB1_20G3
IOB1_24H4
IOB1_25J1
IOB1_26J2
IOB1_27K2
IOB1_28L2
IOB1_29M1
IOB1_30M2
IOB1_31N1
IOB1_32N2
IOB1_33N4
IOB1_34P1
IOB1_35P2
IOB1_36P3
IOB1_37P4
IOB1_38R1
IOB1_39R2
IOB1_40R3
IOB1_41R4
IOB1_42T1
IOB1_43T2
IOB1_44T4
IOB1_45U1
IOB1_46U3
IOB1_47V1
TMST3TDOV2TDIU2TCKW2
IOB1_48V3
IOB1_49W1
U1
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC3
DMINUS9
AGND6
VCC11
GND12
PD752
CLKOUT54
XTALOUT4
AVCC7
DPLUS8
AGND10
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND26
GND28
GND41
PB119
PB321PB220
VCC17
VCC27
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND53
VCC43
PA336
CTL130CTL029
PD045
RESET42
PA538
GND56
VCC55
PA235
PA033
CTL231
VCC32
EXPOSED_PAD57
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
ARRIA 10 USB INTERFACE
JTAG INTERFACE
MAX V USB INTERFACE
On-Board USB Blaster II - Part 2
PLACE NEAR MAX II (U25)USB Blaster Programming Header(uses JTAG mode only)
Logic 0 = Device JTAG BypassLogic 1 = Device JTAG Enable
USB_DISABLEn
FMCB_JTAG_BYPASSnFMCA_JTAG_BYPASSnM5_JTAG_BYPASSnA10_JTAG_BYPASSn
USB_SCLUSB_SDAUSB_FULLUSB_EMPTY
RESn_JTAG_TXJTAG_TX
RESn_SC_RXSC_RX
RESn_SC_TXSC_TX
RESn_JTAG_RXJTAG_RX
FMCA_JTAG_MASTERnFMCB_JTAG_MASTERn
USB_DISABLEn
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
USB_FULL
USB_ADDR1
USB_ADDR0
USB_CFG11
A10_JTAG_TMS
M5_JTAG_TDOM5_JTAG_TDI
M5_JTAG_TMSM5_JTAG_TCK
A10_JTAG_TCK
A10_JTAG_TDOUSB_DATA6
USB_RDn
USB_WRnA10_JTAG_BYPASSn
FMCA_PRSNTn
FMCB_PRSNTn
FMCB_JTAG_MASTERn
FMCA_JTAG_MASTERn
FMCA_JTAG_BYPASSn
M5_JTAG_BYPASSn
JTAG_TX
USB_OEn
USB_RESETn
JTAG_RXUSB_DATA0USB_DATA2
USB_DATA1
USB_DATA7
USB_CFG10 USB_CFG8
USB_CFG9
USB_DATA3
FMCB_JTAG_BYPASSn
SC_RX
USB_DATA4
USB_CFG1
USB_CFG0
USB_CFG6
USB_CFG5
USB_CFG4
USB_CFG3
USB_CFG2
USB_CFG7
SC_TX
USB_CFG13
USB_CFG14
USB_DATA5
USB_CFG12
USB_SDA
USB_SCL
USB_EMPTY
A10_JTAG_TDI
C_JTAG_TDI
C_JTAG_TCKC_JTAG_TDOC_JTAG_TMS
J17_JTAG_TDI
J17_JTAG_TCKJ17_JTAG_TDOJ17_JTAG_TMS
J17_JTAG_TDI
J17_JTAG_TCKJ17_JTAG_TDOJ17_JTAG_TMS
J17_JTAG_TCK
3.3V 3.3V2.5V
1.8V
2.5V
3.3V
3.3V
1.8V 1.8V 1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V 2.5V
2.5V 2.5V2.5V
USB_DATA[7:0]5
USB_FULL8USB_EMPTY8
USB_SDA8
USB_RESETn5USB_OEn5USB_RDn5USB_WRn5
USB_ADDR[1:0]5
USB_SCL8
USB_CFG[14:0]13
A10_JTAG_TMS7
A10_JTAG_TDI7
A10_JTAG_TCK7
A10_JTAG_TDO7
M5_JTAG_TDI13
M5_JTAG_TMS13M5_JTAG_TDO13
M5_JTAG_TCK13
FMCA_PRSNTn6,13,19,24FMCB_PRSNTn6,13,20,24
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B26 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B26 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B26 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R314 22.0
C34
0.1uF
D24 GREEN_LED
R488 10.0K
C43
0.1uF
R45 1.00k
R491 DNI
C32
0.1uF
R40 1.00k
R477 1.00k
D25 GREEN_LED
C19
0.1uF
C33
0.1uF
R3110.0K
R33 1.00k
D22 GREEN_LED
MAX IIBANK2
U49B
EPM1270_M256FBGA
IOB2_1A1
IOB2_2A10
IOB2_3A11
IOB2_4A12
IOB2_5A13
IOB2_6A14
IOB2_7A15
IOB2_8A16
IOB2_9A17
IOB2_10A18
IOB2_11A19
IOB2_12A2
IOB2_13A20
IOB2_14A3
IOB2_15A4
IOB2_16A5
IOB2_17A6
IOB2_18A7
IOB2_20A9
IOB2_21B10
IOB2_22B11
IOB2_23B12
IOB2_24B13
IOB2_25B14
IOB2_26B15
IOB2_27B16
IOB2_28B17
IOB2_29B18
IOB2_30B19
IOB2_31B2
IOB2_32B3
IOB2_33B4
IOB2_34B5
IOB2_36B7
IOB2_37B8
IOB2_38B9
IOB2_39C14
IOB2_40C15
IOB2_41C16
IOB2_42C17
IOB2_43C5
IOB2_44C6
IOB2_45C7
IOB2_46D13
IOB2_47D14
IOB2_48D15
IOB2_49D16
IOB2_50D5
IOB2_51D6
IOB2_52D7
IOB2_53D8
IOB2_19A8
IOB2_35B6
R474 10.0K
C7420.1uF
R473 10.0K
J17
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
R504 1.00k
R46 DNI
R311 22.0
C41
0.1uF
MAX IIBANK3
U49C
EPM1270_M256FBGA
IOB3/GCLK3L20
IOB3_24J19
IOB3_1B20
IOB3_2C18
IOB3_3C19
IOB3_4C20
IOB3_5D17
IOB3_6D18
IOB3_7D19
IOB3_8D20
IOB3_9E17
IOB3_10E18
IOB3_11E19
IOB3_12E20
IOB3_13F17
IOB3_14F18
IOB3_15F19
IOB3_16F20
IOB3_17G17
IOB3_18G18
IOB3_19G19
IOB3_20G20
IOB3_21H17
IOB3_23H20
IOB3/GCLK2M20
IOB3_25J20
IOB3_26K19
IOB3_27K20
IOB3_28L19
IOB3_29M19
IOB3_30N17
IOB3_31N19
IOB3_32N20
IOB3_33P17
IOB3_35P19
IOB3_36P20
IOB3_37R17
IOB3_38R18
IOB3_39R19
IOB3_40R20
IOB3_41T17
IOB3_42T18
IOB3_43T19
IOB3_44T20
IOB3_45U17
IOB3_46U18
IOB3_47U19
IOB3_48U20
IOB3_49V19
IOB3_50V20
IOB3_51W19
IOB3_52W20
IOB3_53Y20
IOB3_22H19
IOB3_34P18
C17
0.1uF
R43 10.0K
C7410.1uF
R5031.00k
R467 1.00k
R313 22.0
R3010.0K
C42
0.1uF
C18
0.1uF
R44 10.0K
C664 DNI
R27 1.00k
R312 22.0
C35
0.1uF
MAX IIPower
U49E
EPM1270_M256FBGA
GNDINTJ4
GNDINTU12
GNDINTM17
GNDINTD12
GNDIOH3
GNDIOJ3
GNDIOM4
GNDION3
GNDIOU9
GNDIOV8
GNDIOV9
GNDIOV13
GNDIOH18
GNDIOJ17
GNDION18
GNDIOC8
GNDIOD9
GNDIOC12
GNDIOC13
GNDIOM18
VCCINTD11VCCINTL17VCCINTU11VCCINTK4
VCCIO1K3
VCCIO1L3
VCCIO1L4
VCCIO1M3
VCCIO2C9
VCCIO2C10
VCCIO2D10
VCCIO2C11
VCCIO3J18
VCCIO3K17
VCCIO3K18
VCCIO3L18
VCCIO4U10
VCCIO4V10
VCCIO4V11
VCCIO4V12
C7401uF
R39 1.00k
D23 GREEN_LED
R321.00k
U76
MAX13042
VLB2
IO_VL4C1 IO_VL3C2 IO_VL2C3 IO_VL1C4
GNDB4
VCCB1
IO_VCC1A4
IO_VCC2A3
IO_VCC3A2
IO_VCC4A1
ENB3
R487 10.0K
OPEN
SW4
DIPSWITCH4
12345
678
R42 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power Tree
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C27 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C27 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C27 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C28 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C28 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C28 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
ADDR = 01
Voltage &Temp Sense
TSENSE_FAN_CNTL
OVERTEMPn RESn_LED_FAN
SENSE5_SCK
SENSE5_SCK
SENSE5_CS0nSENSE5_SDO
SENSE5_SDO
SENSE5_CS0n
SENSE5_SDI
SENSE5_SDI
3.3V
12V
3.3V
3.3V
2.5V
5.0V
5.0V
5.0V 2.5V
2.5V
OVERTEMP13
TSENSE_ALERTn13OVERTEMPn13
TEMPDIODE_N 7SENSE_SMB_CLK13,30SENSE_SMB_DATA13,30
TEMPDIODE_P 7
SENSE_SDO13
SENSE_SCK13SENSE_SDI13
SENSE_CS0n13
A10_VCCRT_GXB_SENSE_N 39A10_VCCRT_GXB_SENSE_P 39
A10_VCCRAM_SENSE_N 38
A10_VCCPT_SENSE_N 41A10_VCCPT_SENSE_P 41
A10_VCCRAM_SENSE_P 38
A10_VCCIO_1.8V_SENSE_N 42A10_VCCIO_1.8V_SENSE_P 42
A10_VCCIO_MEM_SENSE_P 45A10_VCCIO_MEM_SENSE_N 45
A10_VCCIO_FMCA_SENSE_P 43A10_VCCIO_FMCA_SENSE_N 43
A10_VCCIO_FMCB_SENSE_P 44A10_VCCIO_FMCB_SENSE_N 44
A10_VCC_SENSE_P 35A10_VCC_SENSE_N 35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B29 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B29 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B29 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Q3
FDV305N
R50
610
.0K
J19
22_23_2021
12
R472 22.0
R18
10.0
K
R505 10.0K
R19
10.0
K
U71
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R17 200
R50
710
.0K
C227
0.1uF
C6970.1uF
C228
0.1uF
R5390
U46
MAX1619
ADD16
ADD010
SMBCLK14
SMBDATA12DXP
3
DXN4
VCC1
OVERTn9
ALERTn11
STBYn15 GND1
2
GND27
GND38
NC15
NC213
NC316
C69810uFU44
LTC2418
CH021
CH122
CH223
CH324
CH425
CH526
CH627
CH728
CH81
CH92
CH103
CH114
CH125
CH136
CH147
CH158
COM10
GND15
VCC9
REF+11
REF-12
F019
CSn16SCK18SDI20SDO17
NC113
NC214
B3
FAN_2pin_Conn
R21
10.0
K
D32 RED_LED
R20
10.0
K
R5330
C244
1uF
C60.1uF
R538DNI
R52
210
.0K
R52
110
.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LTC2977Address Select = 7'h5C
I2C Interface
these GND connections needs to be placed close to a GND pin of the BGA!
4V
Power Sequence Controller
PM_CNTL1
PM_ASEL0PM_ASEL1
PM_CNTL1
PM_SHARE_CLK
PM_RSTn
PM_ALERTLT_SCLLT_SDA
PM_ASEL0
POWER_EN
PM_ALERTPM_PWRGD
PM_ASEL1
PM_FAULTB00PM_FAULTB01PM_FAULTB10PM_FAULTB11
LT_SCLLT_SDA
PM_SHARE_CLK
PM_PWRGD
PM_FAULTB10
PM_FAULTB00
PM_FAULTB11
PM_FAULTB01
PM_ALERT
PM_CNTL1PM_RSTn
LT_SCLLT_SDA
POWER_EN
VDD33
12V_OUT
VDD33
A10_VCC
A10_VCCRT_GXB
3.3V
A10_VCCIO_1.8V
A10_VCCPT
12V
VDD33
SENSE_SMB_CLK 13,29SENSE_SMB_DATA 13,29
EN_POWER_SEQ 31,32
POWER_EN 31
EN_12V 31
EN_A10_VCC 35,36,49
EN_A10_VCCIO 34,42,43,44,45,49
EN_A10_GROUP2 38,39,49EN_A10_1.8V 41,49
VDAC_VCC35
VDAC_VCCRT39
VDAC_VCCPT41
VDAC_VCCIO_1.8V42
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B30 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B30 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B30 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R747 200
J24
2x6HDR
11
22
33
44
55
66
77
88
99
1010
1212
1111 R756
10K
R72310K
C815 0.1uF
C817 0.1uF
R72610K
GNDPAD
U81
LTC2977
VOUT_EN48
VOUT_EN59
VOUT_EN610
VOUT_EN711
VIN_EN12
NC13
VIN_SNS14
VPWR15
VDD33_OUT16
VDD33_IN17
VDD2518WP
19 PWRGD20SHARE_CLK
21
WDI/RESET22
FAULTB0023
FAULTB0124
FAULTB1025
FAULTB1126
SDA27 SCL28
ALERTB29
CONTROL030
CONTROL131
ASEL032
ASEL133
REFP34
REFM35VSENSEP0
36
VSENSEM037
VDACM038VDACP039
VDACP140
VDACM141
VSENSEP142
VSENSEM143
VDACP244
VDACM245
VSENSEP246
VSENSEM247
VSENSEP348
VSENSEM349
VDACP350
VDACM351
VSENSEP452
VSENSEM61
VSENSEP72
VSENSEM73
VOUT_EN04
VOUT_EN15
VOUT_EN26
VOUT_EN37
VSENSEM453
VDACM454VDACP455
VDACP556
VDACM557
VDACM658VDACP659
VDACP760
VDACM761
VSENSEP562
VSENSEM563
VSENSEP664
E-PAD65
C820 0.1uF
R73010K
R738 200
R7225.49K
R749 200
C814 0.1uF
R746 200
R72410K
C822
0.1uf
C810 0.1uF
R744 200
C811 0.1uF
C821
0.1uf
R742 200R74049.9K
R75210K
R72510K
R75110K
R72910K
C818 0.1uF
R1001 0
R748 200
R75310K
C813 0.1uF
R73210K
C823
0.1uf
R72710K
C819 0.1uF
OPEN
SW7
DIPSW06
12345 11
10987
6 12
R72810K
R739 200
R745 200
R754 200
R1000 0
R743 200
C8080.1uf
C812 0.1uF
C816 0.1uF
R741 200
R73110K
R75810K
C809 0.1uF
R735100K
R75710K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - Select Power Input
DC_IN_ATX(Voltage Selected by LTC4357)
12V_PCIE ATX(2x4 ATX)
DC_IN -> 12V(Laptop Supply)
0V
12V
12V 12V from 12V_ATX_IN12V
0V
12V
12V from DC_IN->12V
12V from 12V_ATX_IN
SHOULD SHIELD JUST BETIED DIRECTLY TO GND?
12VDC Input
REVERSE VOLTAGE PROTECTION
DC_IN = 12V from a laptop power supply.
Sense0 = GND Sense1 = GND A 2 x 4 auxiliary power connector is plugged into thecard. The card can draw up to150 W from the auxiliary power connector.
12V ATX INPUT (12.5A)
12V from ATX
Power On Switch
ENABLE WITHOUT SWITCH IFBOARD IS IN PC CHASSIS.
2.98V
EN_12V
POWER_EN
EN_POWER_SEQ
SGND
12V_PCIE
DC_INPUT
12V_ATX
DC_IN_12V 12V
12V_OUT
12V_OUT
12V_OUT
12V_OUT
DC_INPUT
DC_INPUT12V_PCIE
3.3V_PCIE_MUX3.3V_PCIE
3.3V_PCIE
12V_OUT
EN_12V30
EN_POWER_SEQ30,32
POWER_EN30
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B31 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B31 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B31 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R520.0K
R323 5.49M
C929
47uF20V
U52
LTC4365-1
VIN4
VOUT6
GA
TE5
UV3
GND1
OV2
FAULT7SHDN
8
GND9
R328 DNI R340 0
R325
200k
R992
0
C116
47uF20V
C434
47uF20V
R316
0.003
R327 DNI
U87
LTC4365-1
VIN4
VOUT6
GA
TE5
UV3
GND1
OV2
FAULT7SHDN
8
GND9
C784
100uF
U54
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
R956
0
R3931M
C726
4.7nF
U86FDMC2514SDC
5
123
4C793
100uF
R660.4K
U50
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
R160.4K
C930
47uF20V
U27FDMC2514SDC
5
123
4
SW1SW_SLIDE_DPDT
1
236
5
4
C783
100uF
U13FDMC2514SDC
5
123
4
R991 DNI
J13
PD-40S
GND3VOUT2VOUT1
GND4
SGND5
SGND6
SGND7
SGND8
SGND9
C792
100uF
R324100K
U22FDMC2514SDC
5
123
4
R953
10K
J4
PCIe 2x4 ATX
12V1
12V2
12V3
GND8
SENSE14 SENSE06
GND5
GND7
U17FDMC2514SDC
5
123
4
U55
LTC4357
OUT1
GND4VDD6
NC5
GATE3
IN2
EP_GND7
C928 DNI
C5264.7nF
D31
MMBD1205
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power - 12V to 3.3V
RemoteSense NearU35
connect AGND toPGND through asingle via
This output is set a little higher than3.3V (3.45V) by R1004 to give it priorityover 3.3V_PCIe through the MUX.
3.3V_MUX
12V
12V
12V
12V
EN_POWER_SEQ30,31
3p3V_PGOOD 35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C32 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C32 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C32 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
V47
RS
NS
1S
NS
2
C1008
100uF
C1003
22uF
C996
100uF
C986
100uF
C1092 220pF
C1006
10uF
C1005
22uF
C997
100uF
C1013
100uF
U90C
LTM4620A
GND1A6
GND2A7
GND3B6
GND4B7
GND5D1
GND6D2
GND7D3
GND8D4
GND9D9
GND10D10
GND11D11
GND12D12
GND13E1
GND14E2
GND15E3
GND16E4
GND17E10
GND18E11
GND19E12
GND20F1
GND21F2
GND22F3
GND23F10
SGND1C7
SGND2D6
SGND3G6
SGND4G7
SGND5F6
SGND6F7
GND24F11
GND25F12
GND26G1
GND27G3
GND28G10
GND29G12
GND30H1
GND31H2
GND32H3
GND33H4
GND34H5
GND35H6
GND36H7
GND37H9
GND38H10
GND39H11
GND40H12
GND41J1
GND42J5
GND43J8
GND44J12
GND45K1
GND46K5
GND47K6
GND48K7
GND49K8
GND50K12
GND51L1
GND52L12
GND53M1
GND54M12
C1093 100pF
C988
22uF
C1010
100uF
C1002
10uF
C991
100uF
C987
22uFR1003
10.0K
C1009
100uF
U89C
LTM4620A
GND1A6
GND2A7
GND3B6
GND4B7
GND5D1
GND6D2
GND7D3
GND8D4
GND9D9
GND10D10
GND11D11
GND12D12
GND13E1
GND14E2
GND15E3
GND16E4
GND17E10
GND18E11
GND19E12
GND20F1
GND21F2
GND22F3
GND23F10
SGND1C7
SGND2D6
SGND3G6
SGND4G7
SGND5F6
SGND6F7
GND24F11
GND25F12
GND26G1
GND27G3
GND28G10
GND29G12
GND30H1
GND31H2
GND32H3
GND33H4
GND34H5
GND35H6
GND36H7
GND37H9
GND38H10
GND39H11
GND40H12
GND41J1
GND42J5
GND43J8
GND44J12
GND45K1
GND46K5
GND47K6
GND48K7
GND49K8
GND50K12
GND51L1
GND52L12
GND53M1
GND54M12
C1007
100uF
R10024.70K
R1006
10.0K
C989
10uF
C1004
22uF
C995
100uF
U90B
LTM4620A
VIN1M2
VIN2M3
VIN3M4
VIN4M5
VIN5M6
VIN6M7
VIN7M8
VIN8M9
VIN9M10
VIN10M11
VIN11L2
VIN12L3
VOUT1_1A1
VOUT1_2A2
VOUT1_3A3
VOUT1_4A4
VOUT1_5A5
VOUT1_6B1
VOUT1_7B2
VOUT1_8B3
VOUT1_9B4
VOUT1_10B5
VOUT1_11C1
VOUT1_12C2
VOUT1_13C3
VOUT1_14C4VIN13
L4
VIN14L5
VIN15L6
VIN16L7
VIN17L8
VIN18L9
VIN19L10
VIN20L11
VIN21J2
VIN22J3
VIN23J4
VIN24J9
VIN25J10
VIN26J11
VIN27K2
VIN28K3
VIN29K4
VIN30K9
VIN31K10
VIN32K11
VOUT2_1A8
VOUT2_2A9
VOUT2_3A10
VOUT2_4A11
VOUT2_5A12
VOUT2_6B8
VOUT2_7B9
VOUT2_8B10
VOUT2_9B11
VOUT2_10B12
VOUT2_11C9
VOUT2_12C10
VOUT2_13C11
VOUT2_14C12
C990
100uF
U89B
LTM4620A
VIN1M2
VIN2M3
VIN3M4
VIN4M5
VIN5M6
VIN6M7
VIN7M8
VIN8M9
VIN9M10
VIN10M11
VIN11L2
VIN12L3
VOUT1_1A1
VOUT1_2A2
VOUT1_3A3
VOUT1_4A4
VOUT1_5A5
VOUT1_6B1
VOUT1_7B2
VOUT1_8B3
VOUT1_9B4
VOUT1_10B5
VOUT1_11C1
VOUT1_12C2
VOUT1_13C3
VOUT1_14C4VIN13
L4
VIN14L5
VIN15L6
VIN16L7
VIN17L8
VIN18L9
VIN19L10
VIN20L11
VIN21J2
VIN22J3
VIN23J4
VIN24J9
VIN25J10
VIN26J11
VIN27K2
VIN28K3
VIN29K4
VIN30K9
VIN31K10
VIN32K11
VOUT2_1A8
VOUT2_2A9
VOUT2_3A10
VOUT2_4A11
VOUT2_5A12
VOUT2_6B8
VOUT2_7B9
VOUT2_8B10
VOUT2_9B11
VOUT2_10B12
VOUT2_11C9
VOUT2_12C10
VOUT2_13C11
VOUT2_14C12
R100412.7K
C1012
100uF
C1001
4.7uF
U90A
LTM4620A
COMP1E6
DIFFPE8
PGOOD1G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2D7
RUN2F9
CLKOUTG5
FSETC6
SW1G2
SW2G11
VFB1D5
PGOOD2G8
PHASMDG4
TRACK1E5
TRACK2D8
DIFFOUTF8
DIFFNE9
COMP2E7
INTVCCH8
EXTVCCJ7
VOUTS1C5
VOUTS2C8
C998
100uF
C999
22uF
C984
22uF
C993
4.7uF
V48
RS
NS
1S
NS
2
C985
10uF
C994 0.01uF
C1011
100uF
R10054.70K
C992
100uF
C983
22uFU89A
LTM4620A
COMP1E6
DIFFPE8
PGOOD1G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2D7
RUN2F9
CLKOUTG5
FSETC6
SW1G2
SW2G11
VFB1D5
PGOOD2G8
PHASMDG4
TRACK1E5
TRACK2D8
DIFFOUTF8
DIFFNE9
COMP2E7
INTVCCH8
EXTVCCJ7
VOUTS1C5
VOUTS2C8
C1000
100uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power 1 - DC Input to 3.3V Output
POWER LED
ADD DNI RESITOR TOOUTPUT, IN CASE NEEDEDFOR MIN LOAD.
3.3V_MUXVCCP
3.3V_MUXVCC
LT3082_SET
5.0V
3.3V3.3V_OUT
3.3V_PCIE_MUX
3.3V_MUX
12V 5.0V
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B33 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B33 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B33 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
D19BLUE LED
C6661uF
R493DNI
C659
DNI
C665
DNI
C1095
DNI
D43 LTC4352CDD
VIN1
CPO10
SOURCE12
GATE11
OUT8
UV
3
OV
4S
TATU
S5
FAU
LT6
VCC2
REV7
EP13
GND9
U35FDMC2514SDC
5
1 2 3
4
C1094
DNI
C699
0.1uFC667
DNI
U88FDMC2514SDC
5
1 2 3
4
R1650.00025U36
LT3082
OUT1
OUT2
NC13
SET4NC2
5
NC36
IN7
IN8
EPAD_VOUT9
U39FDMC2514SDC
5
1 2 3
4
R492499K
C6770.1uF
R2521.00k
D42 LTC4352CDD
VIN1
CPO10
SOURCE12 GATE11 OUT8
UV
3
OV
4S
TATU
S5
FAU
LT6
VCC2
REV7EP13GND9
C676
2.2uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - MEM_VDD, 2.5V
Arria 10 2.5V (2.5V/2.307A)
Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.
VFB=0.75VIFB=5nA
Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM
Resistor for LLM mode only. Open (DNI) for PWM mode.
SS -> 22nF * 80kOhm = 1.76msec +/-25%
connect AGND toPGND through asingle via
8A
External Memory Interface Connectorwill GND the required SET pin togenerate VDDQ voltage for memoryinterface. The default vaule is 1.2V.
POWER CONTROL
2.5V_LLM
2.5V_FB
2.5V_PGOOD
2.5V_RLLM
2.5V_SS
EN_A10_VCCIO 2.5V_ENABLE
MEM_VDD_PGOOD
EN_A10_VCCIO
VDD_1.35V_SET
VDD_1.25V_SET
VDD_1.5V_SET
VDD_1.3V_SET
3.3V
2.5V
3.3V
3.3V
3.3V
MEM_VDD
3.3V
3.3V
3.3V
3.3V
VDD_1.3V_SET3
EN_A10_VCCIO30,42,43,44,45,49
VDD_1.35V_SET3,17
VDD_1.25V_SET17
VDD_1.5V_SET17
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B34 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B34 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B34 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R806316K
R805DNI
R8000
C346
22uF
U51
EN6337
NC
(SW
)11
NC
(SW
)22
NC
33
NC
44
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
NC
(SW
)12
12
PGND13
PGND14
PGND15
PGND16
PGND17
PGND18
PVIN19
NC
2525
NC
2424
NC
2323
NC
2222
PVIN21 PVIN20
NC
(SW
)38
38N
C(S
W)3
737
NC
(SW
)36
36N
C(S
W)3
535
NC
(SW
)34
34
AVIN33
AGND32
VFB31
SS30
RLLM29
POK28
ENA27
SYNC/LLM26
PGND39
R796160K
R79810.0K
C870
15nF
R331 0
R79715K
C347
47uf
R809DNI
R34884.5K
R795DNI
C41315pF
EN6360QI
U9
EN6360QI
PVIN35
PVIN36
PVIN37
PVIN38
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
ENABLE51
AVIN52
VOUT16
VOUT17
VOUT18
VOUT19
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
PGND28
PGND29
PGND30
PGND31
PGND32
PGND33
PGND34
NC1111
NC1212
NC1313
NC1414
NC1515
NC2525
NC4444
NC4545
NC5959
NC6464
NC6565
NC6666
NC6767
NC6868
NC(SW)2626
NC(SW)2727
NC(SW)6262
NC(SW)6363
VFB55
AGND53
VDDB46
BGND47
POK50
PGND(THRM)69
SS57
FQADJ60
EN_PB61
VSENSE58
S_IN48
S_OUT49
M/S54
EAOUT56
R803634K
C865
22pF
C868
47uf
R346 DNI
R343 DNIC338
47ufR344 0
C866
22uFC863
22uF
C867
22uF
R799160K
C869
100UF
R579560
R794DNI
R347200k
C871
0.22uF
C864
22uF
R810 3.57K
R793 0
C412 22nFR804316K
R807DNI
R808 0
R345 10.0K
R8021.87M
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCC
Default Strapping VID[5:0] = 100011 = 0.95V
A10_VCC (0.9V)
PLACE RESISTOR PADS OVERLAPPINGSO THAT A RESISTOR CAN BEPOPULATED TO PULL-UP TO A10_VCCOR ROUTE A10_VCC_VCCLSENSE_P.
PLACE RESISTOR PADS OVERLAPPINGSO THAT A RESISTOR CAN BEPOPULATED TO PULL-DOWN TO GND ORROUTE A10_VCC_VCCLSENSE_N.
Route as diff pair
Place R261 and R357 side-by-side on top layer androute as kelvin sense to both resistors equallyusing star routing through the 1K resistors. The1K resistors are for limiting eddie currentbackflow.
Default Vout = 0.9Vset by Vfb resistors
U34_ITH
TKSS_LTC3877
EN_A10_VCC
A10_VCC_VID0A10_VCC_VID1A10_VCC_VID2A10_VCC_VID3A10_VCC_VID4A10_VCC_VID5
VFB_LTC3877
VID_READY
A10_VCC_VID0A10_VCC_VID1A10_VCC_VID2A10_VCC_VID3
VID0VID1VID2VID3
VID_READY
A10_VCC_VID4 VID4A10_VCC_VID5 VID5
A10_VCCIO_PGOOD
FPGA_USER_MODE
VID_SELECTED
VID_SELECTEDFPGA_USER_MODE VID_READY
A10_VCC_PGOOD
U34_CLKOUT
A10_VCCIO_PGOOD
VFB_LTC3877
VID_READY
VFB_LTC3877
12V
U34_INTVCC
U34_INTVCC
1.8V3.3V1.8V3.3V
3.3V
1.8V
1.8V
U34_INTVCC
A10_VCC
A10_VCC
A10_VCC_SENSE
U34_INTVCC
FPGA_CONF_DONE 7,13FPGA_VID_EN 7
VID_EN 6,7EN_A10_VCC30,36,49
VID[5:0]6
U34_ITH36
U34_CLKOUT36
A10_VCC_PGOOD36
A10_VCCIO_1.8V_PGOOD 42
A10_VCCIO_FMCA_PGOOD 43
A10_VCCIO_FMCB_PGOOD 44
A10_VCCIO_MEM_PGOOD 45
A10_VCC_VCCLSENSE_N46A10_VCC_VCCLSENSE_P46
A10_VCC_SENSE_P 29
A10_VCC_SENSE_N 29
TKSS_LTC387736
3p3V_PGOOD32
VDAC_VCC30
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C35 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C35 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
C35 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R1048DNI
R101620K
R514 DNI
R1039DNI
R1072 0 C1030 0.1uF
C1031 220pf
V54
RSNS1
SNS2
C102947pF
C1019
330uF
C1088
330uF
R1007
2.20
C1091
220uF
C1016
0.1uF
C1026 0.22uF
R1040665
R10127.32K
R1032 DNI
C232
1uF
C1090
220uF
C1038
330uF
R1022 DNI
C1035 0.22uF
A0&B0=O0
A1&B1=O1
A2&B2=O2
A3&B3=O3
U72
74VCX08BQX
A01
B02 O0
3
A14
B15 O1
6
GND7
O38
B39 A3
10
O211
B212 A213
VCC14
EPAD_NC15
R1043DNI
Q42BSC010NE2LSI
5 6 7 8
123
4
9
C246
0.1uF
C1014
22uF
C1037
330uF
R117 0
R1028
20K
R102610.7K
Q41BSC050NE2LS
5 6 7 8
123
4
9
gnd-pad
U91LTC3877EUK
TK/SS12
ITH17
VFB16
VID338
VID_EN35
ITH28
TK/SS29
PGOOD221
CHL_SEL34
PGOOD120
TG224
BOOST225
VID536
BG226
EXTVCC27 INTVCC28
VID437
SW223
SNS1-44SNSD1+43
DIFFOUT5
VID239
ILIM15
SNSA1+1
VIN29
BG130
BOOST131
TG132
SW133
CLKOUT22
PHASMD19
MODE/PLLIN18
FREQ17
VID140
ITEMP42
RUN16
VOSNS1+3
VID041
SGND/PGND45
VOSNS1-4
VFB2+10
VFB2-11
SNSA2+12
SNS2-13SNSD2+14
U69
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R10420
C1087
330uF
R10354.70K
R64 0
C230
1uF
C1017
4.7uF
C1033
22uF
C1039
220uF
R1077 DNI
R1017100K NTC
C1023
220uF
C229
0.1uF
R10881K
R101810.0K
U70
MAX3378_UCSP
VLB2
IO VL1A1
IO VL2A2
IO VL3A3
IO VL4A4
GNDB4
VCCB1
IO VCC1C1
IO VCC2C2
IO VCC3C3
IO VCC4C4
TSB3
R1075 DNI
C1021
10uF
R1021 DNI
Q39BSC050NE2LS
5 6 7 8
123
4
9
C1022
330uF
R10413.32K
R10464.70K
C1024 0.1uF
R10891K
R10474.70K
R10384.70K
R519 DNI
R10143.32K
R1013665
R512 0
C1034 0.22uF
R10454.70K
R101530.1K
R10344.70K
C10283300pF
D45 CMDSH-3
R10871K
R1033DNI
C1027 0.22uF
R1071 0
L25
0.25uH
V53RSNS
1SNS
2
C1015
22uF
R1031 DNI
R357
0.00025
R532 DNI
R1008100K
C1089
10uF
R10901K
R10100
C231
0.1uF
R1029 10.0K
C1018
330uF
R1044DNI
R114 0
C10250.1uF
D44 CMDSH-3
R397 0
Q40BSC010NE2LSI
5 6 7 8
123
4
9
C245
0.1uF
R1076 0
C1041
10uF
R101986.6K
C1032
22uF
C1040
220uF
L26
0.25uH
R261
0.00025
R513 DNI
C1020
220uF
R1037DNI
R520 10.0K
R515 0
R1036DNI
R1020DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCC
A10_VCC_PGOOD
A10_VCC_SENSE
U94_INTVCC
U94_INTVCC
U94_INTVCC
12V
EN_A10_VCC30,35,49
U34_ITH35
U34_CLKOUT35
A10_VCC_PGOOD35
TKSS_LTC387735
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B36 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B36 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B36 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C1052
220uF
C1050
330uF
R1064 0
C1064
330uF
C1061
22uF
R1061 0
R1056
2.20 R1057665
R10660
C1058
0.22uF
Q45BSC050NE2LS
5 6 7 8
123
4
9
C1060 0.1uF
L27
0.25uH
C1062
22uF
R1060 DNI
Q43BSC050NE2LS
5 6 7 8
123
4
9
R1073 0
D46 CMDSH-3
C1056 0.1uF
C1065
330uF
C1054
0.1uF
C1055
4.7uF
R1059
DNI
D47 CMDSH-3
Q472N7002
R1067
DNI
C105710nF
R1065665
C1051
330uF
R10580
C1067
220uFQ46BSC010NE2LSI
5 6 7 8
123
4
9
R1063 100K
C1063
0.22uF
C1048
22uF
C1066
220uF
R1062 78.7K
C105947pF
Q44BSC010NE2LSI
5 6 7 8
123
4
9
C1053
220uF
L28
0.25uH
R1074 0
LTC3874IUFD#PBFU95
LTC3874IUFD#PBF
MODE01
ISENSE0+2
ISENSE0-3
RUN04
RUN15
ISENSE1-6
ISENSE1+7
MODE18
ITH19
FREQ10
ILIM11
SYNC12
PHASMD13
TG114
SW115
BOOST116
BG117
EXTVCC18 INTVCC19 VIN20
BG021
BOOST022
SW023
TG024
FAULT1B25
FAULT0B26
LOWDCR27
ITH028
GND29
C1049
22uF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
This page intentionally left blank
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B37 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B37 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B37 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCRAM
connect AGNDto PGNDthrough a singlevia
12A
Arria 10 - VCCRAM (0.95V/5.117A)
EN_A10_GROUP2
A10_VCCRAM_PGOOD
3.3V
3.3V
A10_VCCRAM_LOW A10_VCCRAM
A10_VCCRAM_LOW
A10_VCCRAM
A10_VCCRAM_SENSE_N29
A10_VCCRAM_SENSE_P29
EN_A10_GROUP230,39,49
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B38 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B38 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B38 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R822DNI
R819274K
R814DNI
C880
0.22uF
C875
47uf
C876
100UF
C873
47uf
R820DNI
C879
0.015uF
C874
47uf
R81710.0K
C877
47uf
V34SENSE_PAD
RSNS1
SNS2
V33SENSE_PAD
RSNS1
SNS2
R950DNI
R8214.42K
R813160K
C87227pFR812
0
C878
47uf
R816 0
R818 0
R81512K
U10
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC29 29
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
R8110.003
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
40A
Power - A10 VCCRT GXB
RemoteSense NearFPGA Powerballs
Arria 10 - VCCRT_GXB (1.03V/17A)
connect AGND toPGND through asingle via
A10_VCCRT_GXB_LOW A10_VCCRT_GXB
A10_VCCRT_GXB_LOW
A10_VCCRT_GXB
12V
A10_VCCRT_GXB_SENSE_N29
A10_VCCRT_GXB_SENSE_P29
EN_A10_GROUP230,38,49
VDAC_VCCRT30
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B39 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B39 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B39 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C1077
100uF
C1075
100uF
C1073
22uF
C1083 2.2uF
C1078
22uF
R107084.5K
C1072
100uF
U96
LTM4637EV#PBF
VIN1A1
VIN2A2
VIN3A3
VIN4A4
VIN5A5
VIN6A6
VIN7B1
VIN8B2
VIN9B3
VIN10B4
VIN11B5
VIN12B6
VIN13C1
VIN14C2
VIN15C3
VIN16C4
VIN17C5
VIN18C6
VOUT1J1
VOUT2J2
VOUT3J3
VOUT4J4
VOUT5J5
VOUT6J6
VOUT7J7
VOUT8J8
VOUT9J9
VOUT10J10
VOUT11K1
VOUT12K2
VOUT13K3
VOUT14K4
VOUT15K5
VOUT16K6
VOUT17K7
VOUT18K8
VOUT19K9
VOUT20K10
VOUT21K11
VOUT22L1
VOUT23L2
VOUT24L3
VOUT25L4
VOUT26L5
VOUT27L6
VOUT28L7
VOUT29L8
VOUT30L9
VOUT31L10
VOUT32L11
VOUT33M1
VOUT34M2
VOUT35M3
VOUT36M4
VOUT37M5
VOUT38M6
VOUT39M7
VOUT40M8
VOUT41M9
VOUT42M10
VOUT43M11
GND1B7
GND2B9
GND3C7
GND4C9
GND5D1
GND6D2
GND7D3
GND8D4
GND9D5
GND10D6
GND11D8
GND12E1
GND13E2
GND14E3
GND15E4
GND16E5
GND17E6
GND18E7
GND19E9
GND20F1
GND21F2
GND22F3
GND23F4
GND24F5
GND25F6
GND26F7
GND27F8
GND28F9GND29G1GND30G2GND31G3GND32G4GND33G5GND34G6GND35G7GND36G8GND37G9GND38H1GND39H2GND40H3GND41H4GND42H5GND43H6GND44H7GND45H8GND46H9
PGOOD1F11
PGOOD2G12
SGND1G11
SGND2H11
SGND3H12
TEMPD10
MODE_PLLINA8
FSETB12
TRACK/SSA9
VFBF12
COMPA11
RUNA10
INTVCC1A7
INTVCC2D9
EXTVCCE12
VOUT_LCLL12
VOSNS+J12
VOSNS-M12
DIFFOUTK12
MTP1A12 MTP2B11 MTP3C10 MTP4C11 MTP5C12 MTP6D11 MTP7D12
R1069
0.00025
C1069
22uF
V51SENSE_PAD
RSNS1
SNS2
C1082
100UF
C1085
330pF
R1068
100K
V50
RS
NS
1S
NS
2
R1078 DNI
V49
RS
NS
1S
NS
2
C1074
100uF
C1079
22uF
C1076
100uF
C1071
10uF
V52SENSE_PAD
RSNS1
SNS2
C1081
10uF
C1070
10uFC1080
10uF
C1068
100uF
C1084
1nF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
This page intentionally left blank
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B40 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B40 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B40 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCPT & 1.8V
connect AGNDto PGNDthrough a singlevia
12A
Arria 10 VCCA_PLL, VCCH_GXB, VCCPT (1.8V/10.229A)
A10_1.8V_PGOOD
EN_A10_1.8V
3.3V
3.3V
A10_1.8V_LOW A10_VCCPT A10_1.8V
A10_1.8V_LOW
A10_VCCPT
A10_VCCPT_SENSE_N29
A10_VCCPT_SENSE_P29
EN_A10_1.8V30,49
VDAC_VCCPT30
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B41 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B41 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B41 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C902
47uf
V45SENSE_PAD
RSNS1
SNS2
V46SENSE_PAD
RSNS1
SNS2
C90447UF
R8500.00025
R860DNI
R952DNI
R85780.6K
L24
10A, RDC 4mOhm
C907
0.015uF
C905
47uf
C908
0.22uF
C906
47uf
C903
100UF
R85510.0K
R854 0
R85312K
R8594.42K
R852160K
R851
0
U31
EN63A0QI
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
PVIN44
PVIN45
PVIN46
PVIN47
PVIN48
PVIN49
PVIN50
PVIN51
PGND32
PGND33
PGND34
PGND35
PGND36
PGND37
PGND38
PGND(THRM)77
POK58
VFB63
ENABLE59 AVIN60
S_OUT57
AGND61
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC1515
NC1616
NC1717
NC1818
NC1919
NC29 29
NC30(SW)3030
NC30(SW)3131
NC(SW)7070
NC(SW)7171
NC7272
NC7373
NC7474
NC7575
NC7676
SS65
EN_PB69
EAOUT64
S_IN56
BGND55
VDDB54
VSENSE66
FQADJ68
NC(XREF)67
M/S62
NC5252
NC5353
R1079 DNI
R858DNI
C901
47uf
R849DNI
C899
47uf
R856 0
C900
27pF
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCIO 1.8V
Arria 10 VCCIO_1.8V & 1.8V (1.8V/2.08A)
Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.
VFB=0.75VIFB=5nA
Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM
Resistor for LLM mode only. Open (DNI) for PWM mode.
SS -> 22nF * 80kOhm = 1.76msec +/-25%
1.8V_LLM
1.8V_VFB
A10_VCCIO_1.8V_PGOOD
1.8V_RLLM
1.8V_SS
EN_A10_VCCIO 1.8V_ENABLE
1.8V
A10_VCCIO_1.8V
3.3V
3.3V
3.3V
1.8V A10_VCCIO_1.8V3.3V
3.3V
A10_VCCIO_1.8V_SENSE_N29
A10_VCCIO_1.8V_SENSE_P29
EN_A10_VCCIO34,43,44,45,49
A10_VCCIO_1.8V_PGOOD35
VDAC_VCCIO_1.8V30
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B42 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B42 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B42 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
V21SENSE_PAD
RSNS1
SNS2
V24SENSE_PAD
RSNS1
SNS2
R584560
C53215pF
R398 10.0K
R395 DNI
R400200k
C531 22nF
C468
47uf
R950.003
R401143.0K
R396 0
C467
22uF
C442
47uf
R1080 DNI
U57
EN6337
NC
(SW
)11
NC
(SW
)22
NC
33
NC
44
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
NC
(SW
)12
12
PGND13
PGND14
PGND15
PGND16
PGND17
PGND18
PVIN19
NC
2525
NC
2424
NC
2323
NC
2222
PVIN21 PVIN20
NC
(SW
)38
38N
C(S
W)3
737
NC
(SW
)36
36N
C(S
W)3
535
NC
(SW
)34
34
AVIN33
AGND32
VFB31
SS30
RLLM29
POK28
ENA27
SYNC/LLM26
PGND39
R390 0
C131
47UF
R399 DNI
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCIO FMCA
1.2VR1084 1.35VR1085
VCCIO FMCA SELECT
1.5V
NONEInstalled
FMCA Voltage
1.8VR1086(Default)
Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.
VFB=0.75VIFB=5nA
Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM
Resistor for LLM mode only. Open (DNI) for PWM mode.
SS -> 22nF * 80kOhm = 1.76msec +/-25%
Arria 10 VCCIO_FMCA & FMCA_VADJ (1.2V/3.5A)Variable 1.2V, 1.35V, 1.5V, 1.8V
Install only one
FMCA_ADJ_VFB
FMCA_ADJ_VFB
A10_VCCIO_FMCA_PGOOD
EN_A10_VCCIO A10_FMCA_ENABLE
3.3V
3.3V
3.3V
3.3V
3.3V
A10_VCCIO_FMCAFMCA_ADJ
FMCA_ADJ
A10_VCCIO_FMCA
A10_VCCIO_FMCA_SENSE_N29
A10_VCCIO_FMCA_SENSE_P29
EN_A10_VCCIO34,42,44,45,49
A10_VCCIO_FMCA_PGOOD35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B43 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B43 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B43 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R864 0
C909
22uF
R1084 DNI
C910
47uf
R409 249K
V38SENSE_PAD
RSNS1
SNS2
C91215pF
R863 DNI
U20
EN6347QIN
C(S
W)1
1
NC
(SW
)22
NC
33
NC
44
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
NC
(SW
)12
12
PGND13
PGND14
PGND15
PGND16
PGND17
PGND18
PVIN19
NC
2525
NC
2424
NC
2323
NC
2222
PVIN21 PVIN20
NC
(SW
)38
38N
C(S
W)3
737
NC
(SW
)36
36N
C(S
W)3
535
NC
(SW
)34
34
AVIN33
AGND32
VFB31
SS30
RLLM29
POK28
ENA27
SYNC/LLM26
PGND39
C913 22nF
V37SENSE_PAD
RSNS1
SNS2
R1085 DNI
R86110.0K
R868 DNI
R1086 0
R865200k
R394 499K
R866 0
R869560
R867332K
R389 1M
R8620.003
C911
47uf
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCIO FMCB
1.2VR1083 1.35VR1082
VCCIO FMCB SELECT
1.5V
NONEInstalled
FMCA Voltage
1.8VR1081(default)
Default to internal pull-up on LLMto allow automatic engagement ofLight Load Mode.
VFB=0.75VIFB=5nA
Min (VIN - VOUT) = 315mV for PWMMin (VIN - VOUT) = 800mV for LLM
Resistor for LLM mode only. Open (DNI) for PWM mode.
SS -> 22nF * 80kOhm = 1.76msec +/-25%
Arria 10 VCCIO_FMCB & FMCB_VADJ (1.2V/3.5A)Variable 1.2V, 1.35V, 1.5V, 1.8V
Install only one
FMCB_ADJ_VFB
FMCB_ADJ_VFB
A10_VCCIO_FMCB_PGOOD
EN_A10_VCCIO A10_FMCB_ENABLE
FMCB_ADJ
A10_VCCIO_FMCB
3.3V
3.3V
3.3V
3.3V
3.3V
A10_VCCIO_FMCBFMCB_ADJ
A10_VCCIO_FMCB_SENSE_N29EN_A10_VCCIO3,45,49
A10_VCCIO_FMCB_SENSE_P29A10_VCCIO_FMCB_PGOOD35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B44 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B44 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B44 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R877 DNI
C918 22nF
C914
22uF
R872 DNI
R87010.0K
R1083 DNI
R875 0
R878560
R874200k C917
15pF
V42SENSE_PAD
RSNS1
SNS2
R1082 DNIR1081 0
V41SENSE_PAD
RSNS1
SNS2
R326 249K
R8710.003
C916
47uf
U23
EN6347QI
NC
(SW
)11
NC
(SW
)22
NC
33
NC
44
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
NC
(SW
)12
12
PGND13
PGND14
PGND15
PGND16
PGND17
PGND18
PVIN19
NC
2525
NC
2424
NC
2323
NC
2222
PVIN21 PVIN20
NC
(SW
)38
38N
C(S
W)3
737
NC
(SW
)36
36N
C(S
W)3
535
NC
(SW
)34
34
AVIN33
AGND32
VFB31
SS30
RLLM29
POK28
ENA27
SYNC/LLM26
PGND39
R873 0
C915
47uf
R876332K
R329 499KR330 1M
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Power - A10 VCCIO MEMPOWER CONTROL
connect AGND toPGND through asingle via
8AArria 10 VCCIO_MEM & MEM_VDDQ (1.2V/4.7A)Variable 1.2V, 1.25V, 1.35V, 1.5V
External Memory Interface Connectorwill GND the required SET pin togenerate VDDQ voltage for memoryinterface. The default vaule is 1.2V.
A10_VCCIO_MEM_PGOOD
EN_A10_VCCIO
VDDQ_1.35V_SET
VDDQ_1.25V_SET
VDDQ_1.5V_SET
MEM_VDDQ
A10_VCCIO_MEM
MEM_VDDQ A10_VCCIO_MEM
3.3V
3.3V
3.3V
VDDQ_1.35V_SET17VDDQ_1.25V_SET17
VDDQ_1.5V_SET17A10_VCCIO_MEM_SENSE_N29
EN_A10_VCCIO49A10_VCCIO_MEM_SENSE_P29
A10_VCCIO_MEM_PGOOD35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B45 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B45 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B45 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
R880DNI
C922
100UF
R884DNI
R892 0
R8790.003
R883 0
C926
15nF
C920
22uF
R88510.0K
R8891.87M
V40SENSE_PAD
RSNS1
SNS2
V39SENSE_PAD
RSNS1
SNS2
C921
47uf
R893DNI
R895 3.57K
C925
22pF
R88215K
C919
22uFC923
22uF
R888DNI
C924
22uF
R881160K
C927
0.22uF
R891316K
R894DNI
EN6360QI
U24
EN6360QI
PVIN35
PVIN36
PVIN37
PVIN38
PVIN39
PVIN40
PVIN41
PVIN42
PVIN43
ENABLE51
AVIN52
VOUT16
VOUT17
VOUT18
VOUT19
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
PGND28
PGND29
PGND30
PGND31
PGND32
PGND33
PGND34
NC1111
NC1212
NC1313
NC1414
NC1515
NC2525
NC4444
NC4545
NC5959
NC6464
NC6565
NC6666
NC6767
NC6868
NC(SW)2626
NC(SW)2727
NC(SW)6262
NC(SW)6363
VFB55
AGND53
VDDB46
BGND47
POK50
PGND(THRM)69
SS57
FQADJ60
EN_PB61
VSENSE58
S_IN48
S_OUT49
M/S54
EAOUT56
R886160K
R887
0
R890634K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Power
IS THIS VREFP_ADC/VREFN_ADC?VREFP_ADC up to 10mA?
VFEF_ADC R valuebased on 20ma for1.25V zener
RREF_BLRREF_BR
RREF_TRRREF_TL
A10_VREF_ADC_P
A10_VREF_ADC_N
A10_VCC A10_VCC
A10_VCCRT_GXB A10_VCCRT_GXB
A10_1.8V
A10_1.8V
A10_VCCPT
A10_VCCPT
A10_VCCIO_MEM
MEM_VREF
A10_VCCIO_FMCA
A10_VCCIO_FMCB
A10_VCCIO_1.8V A10_VCCIO_1.8V
A10_VCCIO_1.8V
A10_VCCIO_1.8V
A10_VCCIO_1.8V
A10_VCCIO_1.8V
VREF_FMCA
VREF_FMCB
A10_VCCRAM
A10_VCCIO_1.8V
A10_VCC_VCCLSENSE_P 35A10_VCC_VCCLSENSE_N 35
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B46 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B46 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B46 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
V7
SENSE_PADRSNS
1SNS
2
ARRIA 10 - POWERVCCIO (1.2V, 1.5V, 1.8V)
ANALOG PWR (1.8V)
CONFIG PWR (1.2V, 1.5V, 1.8V)
IO PRE-DRIVER PWR (1.8V)
BATTERY PWR (1.5V, 1.8V)
MEM PWR0.95VES/0.9V
10AX115F1932C
U28S
VCCA_PLLAB22 VCCA_PLLAB23
VCCBATAL23
VCCIO2AAR28
VCCIO2AAU29
VCCIO2AAV27
VCCIO2IAK33
VCCIO2IAL31
VCCIO2IAM29
VCCIO2JAA31
VCCIO2JAD30
VCCIO2JW30
VCCIO2KP30
VCCIO2KT31
VCCIO2KV32
VCCIO2LJ30
VCCIO2LK28
VCCIO2LM29
VCCIO3AAR23
VCCIO3AAU24
VCCIO3AAV22
VCCIO3BAM19
VCCIO3BAP20
VCCIO3BAR18
VCCIO3CAN12
VCCIO3CAP15
VCCIO3CAR13
VCCIO3DAC12
VCCIO3DAD15
VCCIO3DAE13
VCCIO3EAB14
VCCIO3EW15
VCCIO3EY13
VCCIO3FK13
VCCIO3FM14
VCCIO3FN12
VCCIO3GK18
VCCIO3GL21
VCCIO3GM19
VCCIO3HJ25
VCCIO3HK23
VCCIO3HM24
VSIGN_0P19
VSIGN_1N18
VSIGP_0N19
VSIGP_1P18
VCCPGMAK21
VCCPGMAK22
VCCPTAH16
VCCPTAH19
VCCPTAH21
VCCPTAH25
VCCPTAH28
VCCPTAJ22
VCCPTU16
VCCPTU18
VCCPTU20
VCCPTU22
VCCPTU23
VCCPTU26
VCCPTU28
VREFB2AN0AT27
VREFB2IN0AR30
VREFB2JN0AB30
VREFB2KN0R32
VREFB2LN0K32
VREFB3AN0AN23
VREFB3BN0AN18
VREFB3CN0AT12
VREFB3DN0AD11
VREFB3EN0AA12
VREFB3FN0K15
VREFB3GN0L17
VREFB3HN0M22
VREFN_ADCP21VREFP_ADCR21
VCCERAMAC15
VCCERAMAC16
VCCERAMAC18
VCCERAMAC23
VCCERAMAC29
VCCERAMAC21
VCCERAMAC26
VCCERAMAC28
ARRIA 10 - TRANSCEIVER PWR
ANALOG RX PWR(0.9V, 1.0V, 1.1V)
ANALOG TX PWR(0.9V, 1.0V, 1.1V)
TX BUFFER PWR(1.8V)
10AX115F1932C
U28T
VCCH_GXBLAB36
VCCH_GXBLAF36
VCCH_GXBLAK36
VCCH_GXBLK36
VCCH_GXBLP36
VCCH_GXBLV36
VCCR_GXBL1CAM37
VCCR_GXBL1CAM38
VCCR_GXBL1DAH37
VCCR_GXBL1DAH38
VCCR_GXBL1EAD37
VCCR_GXBL1EAD38
VCCR_GXBL1FY37
VCCR_GXBL1FY38
VCCR_GXBL1GT37
VCCR_GXBL1GT38
VCCR_GXBL1HM37
VCCR_GXBL1HM38
VCCT_GXBL1CAK37
VCCT_GXBL1CAK38
VCCT_GXBL1DAF37
VCCT_GXBL1DAF38
VCCT_GXBL1EAB37
VCCT_GXBL1EAB38
VCCT_GXBL1FV37
VCCT_GXBL1FV38
VCCT_GXBL1GP37
VCCT_GXBL1GP38
VCCT_GXBL1HK37VCCT_GXBL1HK38
VCCH_GXBRAB9 VCCH_GXBRAF9 VCCH_GXBRAK9 VCCH_GXBR
K9 VCCH_GXBRP9 VCCH_GXBRV9
VCCR_GXBR4CAM7
VCCR_GXBR4CAM8
VCCR_GXBR4DAH7
VCCR_GXBR4DAH8
VCCR_GXBR4EAD7
VCCR_GXBR4EAD8
VCCR_GXBR4FY7
VCCR_GXBR4FY8
VCCR_GXBR4GT7
VCCR_GXBR4GT8
VCCR_GXBR4HM7
VCCR_GXBR4HM8
VCCT_GXBR4CAK7
VCCT_GXBR4CAK8
VCCT_GXBR4DAF7
VCCT_GXBR4DAF8
VCCT_GXBR4EAB7
VCCT_GXBR4EAB8
VCCT_GXBR4FV7
VCCT_GXBR4FV8
VCCT_GXBR4GP7
VCCT_GXBR4GP8
VCCT_GXBR4HK7
VCCT_GXBR4HK8
RREF_TRA10
RREF_TLA35
RREF_BRBD10
RREF_BLBD35
R332 2.0K
R451 2.0K
C36
0.1uF
R337 2.0K
V8 SENSE_PAD
RSNS1
SNS2
R284680
D40
LT1389
GND4
VOUT6
GND5
NC11
NC22
NC33
NC77
NC88
FB1
120ohm, 800mA
1 2
CORE PWR(0.83V, 0.86V,0.9V)
ARRIA 10 - POWER
Periphery PWR(0.83V, 0.86V, 0.9V)
10AX115F1932C
U28R
VCCR24
VCCT15
VCCT17
VCCT18
VCCT19
VCCT20
VCCT22
VCCT24
VCCT29
VCCLSENSEAF22
VCCAA15
VCCAA17
VCCAA18
VCCAA19
VCCAA20
VCCAA22
VCCAA23
VCCAA24
VCCAA25
VCCAA27
VCCAA28
VCCAA29
VCCAB15
VCCAB16
VCCAB17
VCCAB18
VCCAB20
VCCAB21
VCCAB25
VCCAB26
VCCAB27
VCCAB28
VCCAC14
VCCAC19
VCCAC20
VCCAC24
VCCAC25
VCCAC30
VCCAD16
VCCAD17
VCCAD18
VCCAD19
VCCAD21
VCCAD22
VCCAD23
VCCAD24
VCCAD26
VCCAD27
VCCAD28
VCCAD29
VCCAE16
VCCAE17
VCCAE19
VCCAE20
VCCAE21
VCCAE22
VCCAE24
VCCAE25
VCCAE26
VCCAE27
VCCAE29
VCCAF17
VCCAF18
VCCAF19
VCCAF20
VCCAF24
VCCAF27
VCCAF29
VCCAG17
VCCAG22
VCCAG26
VCCAG28
VCCAH23
VCCAH26
VCCAJ16
VCCAJ18 VCCAJ23 VCCAJ26 VCCAJ28 VCCAK16 VCCAK19 VCCAK24
VCCR16 VCCR19 VCCR27 VCCR29 VCCT23 VCCT25 VCCT27 VCCT28 VCCT30 VCCU17 VCCU27 VCCV16 VCCV18 VCCV19 VCCV23 VCCV24 VCCV28 VCCV29 VCCW16 VCCW17 VCCW18 VCCW19 VCCW21 VCCW22 VCCW23 VCCW24 VCCW26 VCCW27 VCCW28 VCCW29 VCCY16 VCCY17 VCCY19 VCCY20 VCCY21 VCCY22 VCCY24 VCCY25 VCCY26 VCCY27 VCCY29
GNDSENSEAF23 ADCGND
R20
VCCAK27
VCCR22
VCCR17
VCCAJ21
VCCAK17
VCCAK29
VCCAJ29
VCCAJ24
VCCAK20 VCCAK26
VCCAJ27
VCCAG18
VCCAF28VCCAF25
VCCAG23
VCCAG16
VCCAJ17
VCCAH18VCC
AH29
VCCAH24 VCC
AG27VCC
AJ19
VCCPAH30
VCCPAG25
VCCPAH15
VCCPAG15
VCCPAH20
VCCPAG20
VCCPAG21
VCCPAG30
VCCPU15
VCCPV30
VCCPU21
VCCPV26VCCPV25
VCCPV20VCCPV15
VCCPV21
VCCPU30VCCPU25
R447 2.0K
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Arria 10 Ground
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B47 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B47 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B47 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
ARRIA 10 - GND
10AX115F1932C
U28V
GNDAL21
GNDAL26
GNDAL35
GNDAL36
GNDAL39
GNDAL40
GNDAL43
GNDAL44
GNDAL5
GNDAL6
GNDAL9
GNDAM10
GNDAM14
GNDAM22
GNDAM24
GNDAM3
GNDAM34
GNDAM36
GNDAM4
GNDAM41
GNDAM42
GNDAM9
GNDAN1
GNDAN17
GNDAN2
GNDAN22
GNDAN27
GNDAN32
GNDAN35
GNDAN36
GNDAN39
GNDAN40
GNDAN43
GNDAN44
GNDAN5
GNDAN6
GNDAN9
GNDAP10
GNDAP25
GNDAP3
GNDAP30
GNDAP35
GNDAP36
GNDAP37
GNDAP38
GNDAP4
GNDAP41
GNDAP42
GNDAP7
GNDAP8
GNDAP9
GNDAR1
GNDAR2
GNDAR33
GNDAR38
GNDAR39
GNDAR40
GNDAR43
GNDAR44
GNDAR5
GNDAR6
GNDAR7
GNDAR8
GNDAT11
GNDAT16
GNDAT21
GNDAT26
GNDAT3
GNDAT31
GNDAT36
GNDAT38
GNDAT4
GNDAT41
GNDAT42
GNDAT7
GNDAU1
GNDAU14
GNDAU19
GNDAU2
GNDAU34
GNDAU38
GNDAU39
GNDAU40
GNDAU43
GNDAU44
GNDAU5
GNDAU6
GNDAU7
GNDAU9
GNDAV12
GNDAV17
GNDAV3
GNDAV32
GNDAV36
GNDAV37
GNDAV38
GNDAV4
GNDAV41
GNDAV42
GNDAV7
GNDAV8
GNDAV9
GNDAW1
GNDAW10
GNDAW15
GNDAW2
GNDAW20
GNDAW25
GNDAW30
GNDAW35
GNDAW36
GNDAW39
GNDAW40
GNDAW43
GNDAW44
GNDAW5
GNDAW6
GNDAW9
GNDAY13
GNDAY18
GNDAY23
GNDAY28
GNDAY3
GNDAY33
GNDAY36
GNDAY37
GNDAY38
GNDAY4
GNDAY41
GNDAY42
GNDAY7
GNDAY8
GNDAY9
GNDB10
GNDB11
GNDB14
GNDB19
GNDB24
GNDB29
GNDB3
GNDB34
GNDB35
GNDB36
GNDB37
GNDB38
GNDB4
GNDB41
GNDB42
GNDB7
GNDB8
GNDB9
GNDBA1
ARRIA 10 - GND
10AX115F1932C
U28W
GNDBA11
GNDBA16
GNDBA2
GNDBA21
GNDBA26
GNDBA31
GNDBA36
GNDBA39
GNDBA40
GNDBA43
GNDBA44
GNDBA5
GNDBA6
GNDBA9
GNDBB14
GNDBB19
GNDBB24
GNDBB29
GNDBB3
GNDBB34
GNDBB36
GNDBB37
GNDBB38
GNDBB4
GNDBB41
GNDBB42
GNDBB7
GNDBB8
GNDBB9
GNDBC1
GNDBC12
GNDBC17
GNDBC2
GNDBC22
GNDBC27
GNDBC32
GNDBC34
GNDBC36
GNDBC39
GNDBC40
GNDBC43
GNDBC44
GNDBC5
GNDBC6
GNDBC9
GNDBD11
GNDBD15
GNDBD2
GNDBD20
GNDBD25
GNDBD3
GNDBD30
GNDBD36
GNDBD37
GNDBD38
GNDBD4
GNDBD41
GNDBD42
GNDBD43
GNDBD7
GNDBD8
GNDBD9
GNDC1
GNDC12
GNDC17
GNDC2
GNDC22
GNDC27
GNDC32
GNDC36
GNDC39
GNDC40
GNDC43
GNDC6
GNDC9
GNDD10
GNDD15
GNDD20
GNDD25
GNDD3
GNDD30
GNDD35
GNDD36
GNDD37
GNDD38
GNDD4
GNDD41
GNDD42
GNDD7
GNDD8
GNDD9
GNDE1
GNDE13
GNDE18
GNDE2
GNDE23
GNDE28
GNDE33
GNDE36
GNDE39
GNDE40
GNDE43
GNDE44
GNDE5
GNDE6
GNDE9
GNDF11
GNDF16
GNDF21
GNDF26
GNDF3
GNDF31
GNDF36
GNDF37
GNDF38
GNDF4
GNDF41
GNDF42
GNDF7
GNDF8
GNDF9
GNDG1
GNDG14
GNDG19
GNDG2
GNDG24
GNDG29
GNDG34
GNDG36
GNDG39
GNDG40
GNDG43
GNDG44
GNDG5
GNDG6
GNDG9
GNDH12
GNDH17
GNDH22
GNDH27
GNDH3
GNDH32
GNDH36
GNDH37
GNDH38
GNDH4
GNDH41
GNDH42
GNDC5 GND
C44
ARRIA 10 - NC/DNU
10AX115F1932C
U28Y
NC1M25
NC2N29
NC3P27
NC4P28
NC5P29
NC6P31
NC7P32
NC8R25
NC9R26
NC10M26
NC11M27
NC12M28
NC13M30
NC14M31
NC15N23
NC16N24
NC17N25
NC18N26
NC19N28
NC20N30
NC21N31
NC22P22
NC23P23
NC24P24
NC25P26
DNU3AR27DNU2AP29DNU1AN28
DNU4BC10
DNU5BC11
DNU6BC35
DNU7BD34
ARRIA 10 - GND
10AX115F1932C
U28U
GNDA11
GNDA16
GNDA2
GNDA21
GNDA26
GNDA31
GNDA34
GNDA36
GNDA39
GNDA40
GNDA43
GNDA5
GNDA6
GNDA9
GNDAA1
GNDAA10
GNDAA11
GNDAA16
GNDAA2
GNDAA21
GNDAA26
GNDAA35
GNDAA36
GNDAA39
GNDAA40
GNDAA43
GNDAA44
GNDAA5
GNDAA6
GNDAA9
GNDAB10
GNDAB19
GNDAB24
GNDAB29
GNDAB3
GNDAB34
GNDAB35
GNDAB4
GNDAB41
GNDAB42
GNDAC1
GNDAC10
GNDAC17
GNDAC2
GNDAC22
GNDAC27
GNDAC32
GNDAC35
GNDAC36
GNDAC39
GNDAC40
GNDAC43
GNDAC44
GNDAC5
GNDAC6
GNDAC9
GNDAD10
GNDAD20
GNDAD25
GNDAD3
GNDAD36
GNDAD4
GNDAD41
GNDAD42
GNDAD9
GNDAE1
GNDAE10
GNDAE18
GNDAE2
GNDAE23
GNDAE28
GNDAE33
GNDAE35
GNDAE36
GNDAE39
GNDAE40
GNDAE43
GNDAE44
GNDAE5
GNDAE6
GNDAE9
GNDAF10
GNDAF11
GNDAF16
GNDAF21
GNDAF26
GNDAF3
GNDAF31
GNDAF35
GNDAF4
GNDAF41
GNDAF42
GNDAG1
GNDAG10
GNDAG14
GNDAG19
GNDAG2
GNDAG24
GNDAG29
GNDAG34
GNDAG35
GNDAG36
GNDAG39
GNDAG40
GNDAG43
GNDAG44
GNDAG5
GNDAG6
GNDAG9
GNDAH12
GNDAH17
GNDAH22
GNDAH27
GNDAH3
GNDAH32
GNDAH36
GNDAH4
GNDAH41
GNDAH42
GNDAH9
GNDAJ1
GNDAJ10
GNDAJ15
GNDAJ2
GNDAJ20
GNDAJ25
GNDAJ30
GNDAJ35
GNDAJ36
GNDAJ39
GNDAJ40
GNDAJ43
GNDAJ44
GNDAJ5
GNDAJ6
GNDAJ9
GNDAK10
GNDAK13
GNDAK18
GNDAK23
GNDAK28
GNDAK3
GNDAK35
GNDAK4
GNDAK41
GNDAK42
GNDAL1
GNDAL11
GNDAL16
GNDAL2
ARRIA 10 - GND
10AX115F1932C
U28X
GNDH7
GNDH8
GNDH9
GNDJ1
GNDJ10
GNDJ15
GNDJ2
GNDJ20
GNDJ35
GNDJ36
GNDJ37
GNDJ38
GNDJ39
GNDJ40
GNDJ43
GNDJ44
GNDJ5
GNDJ6
GNDJ7
GNDJ8
GNDJ9
GNDK10
GNDK3
GNDK33
GNDK35
GNDK4
GNDK41
GNDK42
GNDL1
GNDL10
GNDL11
GNDL16
GNDL2
GNDL26
GNDL31
GNDL35
GNDL36
GNDL39
GNDL40
GNDL43
GNDL44
GNDL5
GNDL6
GNDL9
GNDM3
GNDM34
GNDM36
GNDM4
GNDM41
GNDM42
GNDM9
GNDN1
GNDN17
GNDN2
GNDN22
GNDN27
GNDN32
GNDN35
GNDN36
GNDN39
GNDN40
GNDN43
GNDN44
GNDN5
GNDN6
GNDN9
GNDP10
GNDP15
GNDP20
GNDP25
GNDP3
GNDP35
GNDP4
GNDP41
GNDP42
GNDR10
GNDR13
GNDR18
GNDR2
GNDR23
GNDR28
GNDR33
GNDR35
GNDR36
GNDR39
GNDR40
GNDR43
GNDR44
GNDR5
GNDR6
GNDR9
GNDT11
GNDT16
GNDT21
GNDT26
GNDT3
GNDT36
GNDT4
GNDT41
GNDT42
GNDT9
GNDU1
GNDU10
GNDU14
GNDU19
GNDU2
GNDU24
GNDU29
GNDU34
GNDU35
GNDU36
GNDU39
GNDU40
GNDU43
GNDU44
GNDU5
GNDU6
GNDU9
GNDV10
GNDV12
GNDV17
GNDV22
GNDV27
GNDV3
GNDV35
GNDV4
GNDV41
GNDV42
GNDW1
GNDW2
GNDW20
GNDW25
GNDW36
GNDW39
GNDW40
GNDW43
GNDW44
GNDW5
GNDW6
GNDW9
GNDY18
GNDY23
GNDY28
GNDY3
GNDY33
GNDY36
GNDY4
GNDY41
GNDY42
GNDY9
GNDR1
GNDAM28
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Decoupling
FPGA VCC
FPGA VCCERAM
FPGA VCCA_PLL, VCCH_GXB[L,R]
FPGA VCCPT, VCCBAT
FPGA VCCIO BANKS 2J, 2K, 2L
FPGA VCCIO BANKS 3B & 3C
FPGA VCCIO BANKS 3F & 3G
FPGA VCCIO BANKS 2A, 2I, 3A, 3D, 3E, 3H, VCCPGM
Do Not Copy. Decoupling requirements is design specific. Please use the Early Power Estimator andPDN Tool available on Altera.com to determine your specific decoupling requirements.
VREF_FMCA
A10_VCC
A10_VCCRT_GXB A10_VCCRT_GXB
A10_1.8V
A10_VCCPT
A10_VCCRAM
A10_VCCIO_MEMMEM_VREF
A10_VCCIO_FMCA
A10_VCCIO_FMCB
A10_VCCIO_1.8V
VREF_FMCB
A10_VCC
A10_VCCRT_GXB
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B48 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B48 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B48 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
C497
4.7uF
C491
4.7nF
SCREW4
C734
100uF6.3v
C379
22nF
C485
330uF
C424
4.7uF
C135
330uF
C612
0.47uF
C369
0.22uF
C536
0.1uF
C479
4.7uF
C591
0.22uF
C645
0.01uF
C361
22nF
C340
0.22uF
C263
330uF
C371
22nF
C356
330uF
C502
4.7nF
SCREW3
C661
100uF
C610
0.47uF
C513
0.22uF
C450
4.7uF
C580
4.7uF
C639
0.01uF
C377
22nF
C269
330uF
C423
0.47uF
C539
4.7uF
C301
330uF
C510
4.7nF
C590
4.7uF
C476
4.7uF
STANDOFF1
C633
0.01uF
C360
0.01uF
C25
330uF
C446
4.7uF
C363
22nF
C578
4.7uF
C965
100uF
C555
0.01uF
C650
0.1uF
C372
0.01uF
C559
4.7uF
STANDOFF2
C519
4.7uF
C544
22nF
C617
22nF
C581
47nF
C629
330uF
C451
4.7uFC453
4.7nF
C416
0.22uF
C514
4.7uFC561
0.01uF
C368
0.01uF
C982
100uF
C613
22nF
C541
47nF
C20
330uF
C475
4.7nF
C562
4.7uF
C392
4.7uF
SCREW5
C418
1uF
C524
22nF
C422
0.1uF
C606
1uF
C644
0.01uF
C525
22nF
C473
0.1uF
C381
0.01uF
C520
47nF
C303
330uF
C452
4.7uFC492
4.7nF
C380
0.47uF
C342
1uF
C420
0.47uF
C494
4.7uF
C503
22nF
C577
4.7uF
C378
0.01uF
C616
0.22uF
C339
47nF
C279
330uF
C522
4.7nF
C557
4.7uF
C637
4.7uF
C546
100uF
C552
4.7uFC538
0.1uF
C394
22nF
C607
4.7uF
C493
4.7uF
C638
0.01uF
C366
0.01uF
C964
100uF
C350
0.1uF
C593
0.1uF
C24
330uF
C554
4.7uFC535
4.7nF
C421
0.1uF
C396
0.01uF
C643
47nF
C564
4.7nF
C500
4.7uF
C582
0.1uF
C11
330uF
C533
4.7nFC474
4.7uF
C281
330uF
C454
4.7uFSCREW2
C393
0.1uF
C376
0.1uF
C449
0.1uF
C521
4.7uF
C605
0.1uF
C647
0.01uF
C375
22nF
C414
330uF
C614
0.47uF
C534
0.22uF
C478
4.7uF
C579
4.7uF
SCREW1
C642
0.01uF
C373
22nF
C9
330uF
C560
4.7uF
C302
330uF
C501
4.7nF
C583
4.7uF
C589
4.7uF
C636
0.01uF
C640
22nF
C12
330uF
C576
4.7uF
STANDOFF5
C367
22nF
C417
0.1uF
PCB1
C480
4.7uF
C630
47nF
C364
0.01uF
C737
100uF6.3v
C543
4.7uF
C382
22nF
C280
330uF
C515
4.7nF
C540
4.7uF
C556
4.7uF
STANDOFF4
C649
0.1uF
C646
0.01uF
C575
4.7uF
C615
22nF
C558
47nF
C329
330uF
C523
4.7uF
C415
4.7uF
C509
47nF
C481
0.1uF
C609
0.22uF
C641
0.01uF
C981
100uF
C496
4.7nFC736
100uF6.3v
C611
22nF
C499
47nF
C10
330uF
C448
4.7nF
C584
4.7uF
C349
4.7uF
C553
4.7uF
C631
0.47uF
C635
0.01uF
C594
22nF
C444
0.1uF
C374
0.01uF
C477
47nF
C52
330uF
C545
4.7uFC472
4.7nF
C634
4.7uF
STANDOFF3
C341
0.47uF
C495
4.7uFC471
1uF
C370
0.01uF
C445
0.47uF
C735
100uF6.3v
C352
0.1uF
C85
330uF
C511
4.7nF
C537
4.7uF
C517
4.7uF
C447
4.7uF
C516
0.47uF
C395
22nF
C632
0.01uF
C563
4.7nF
C518
4.7uF
C362
0.01uF
C351
0.1uF
C592
0.1uF
C1
330uF
C498
4.7uFC512
4.7nF
C278
330uF
C482
0.22uF
C608
0.01uF
C365
47nF
C419
0.1uF
C542
4.7uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Power-down Fast Discharge
EN_A10_VCCIO
EN_A10_VCCIO
EN_A10_VCCIOEN_A10_VCCIO
EN_A10_VCCIO EN_A10_VCCIO
EN_A10_GROUP2 EN_A10_GROUP2EN_A10_1.8V
EN_A10_VCC
A10_VCCIO_1.8V A10_VCCIO_FMCA
A10_VCCIO_FMCB
MEM_VDD
2.5V3.3V
3.3V
3.3V3.3V A10_VCCIO_MEM
3.3V 3.3V
A10_VCCRAM A10_VCCRT_GXB3.3V 3.3V3.3V A10_1.8V
A10_VCC3.3V
EN_A10_VCCIO 30,34,42,43,44,45EN_A10_1.8V 30,41EN_A10_GROUP2 30,38,39EN_A10_VCC 30,35,36
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B49 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B49 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Title
Size Document Number Rev
Date: Sheet of
E3.1
Arria 10 GX FPGA Development Kit
B49 49Wednesday, August 10, 2016
150-0321301-E3 (6XX-44366R)
Altera Corporation, 101 Innovation Dr., San Jose CA 95134Copyright (c) 2013, Altera Corporation. All Rights Reserved.
Q52FDMC8878
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