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© BME-MIT 2017Budapest University of Technology and EconomicsDepartment of Measurement and Information Systems
ARM Cortex Core Microcontrollers
4. System Control block
Scherer Balázs
© BME-MIT 2017 2.
Evaluation of internal architecture of
ARM7 core based micros
2003 - 2008
© BME-MIT 2017 3.
The first ARM7 core micro
2003: LPC210x
ARM7 core
Vector Interrupt Controller
AHB/APB bridge
AHB bus
APB bus
Periph 1
Periph 2
Periph 3
Periph 4
AHB bridge
On-chip memory
© BME-MIT 2017 4.
AHB vs APB
Both part of the ARM Advanced Microcontroller Bus Architecture (AMBA) standard
AHB Advanced High-performance Buso Pipelining
o Multiple master
o Burst transaction
o Full-duplex parallel comm.
APB Advanced Peripheral Buso No Pipelining
o Single master
o Small complexity
o Small power
o 32-bit bus
© BME-MIT 2017 5.
The last ARM7 core micro
2006: LPC23xx
ARM7 core
Vector Interrupt Controller
AHB/APB bridge
AHB1 bus
APB bus
Periph 1
Periph 2
Periph 3
Periph 4
AH
B b
ridge
On-chip memory
USBmemory
USBwith DMA
AH
B b
ridge
Fast I/O
DMAcontroller
Ethernetwith DMA
Ethernetmemory
AHB ot AHBbridge
© BME-MIT 2017 6.
Evaluation of internal architecture of
Cortex M3 core micros
© BME-MIT 2017 7.
First generation of Cortex M3
2006: Luminary LM3S102
ARM Cortex M3Proc
20MHz
APB bridge
APB bus
GPIO
Periph 2
Periph 3
Periph 4
8 Kbyte Flash
iCode
iData
System Bus
2 Kbyte SRAM
© BME-MIT 2017 8.
Second generation of Cortex M3
2007: STM32F103 (Max 72 MHz)
• APB1: max. 72MHz• APB2: max. 36MHz
© BME-MIT 2017 9.
Multi master bus system
Slave
MasterArbiter
Slave
Slave
Master
Master
Shared AHB Bus
Slave
Master
Slave
Slave
Master Master
AHB Bus Matrix
© BME-MIT 2017 10.
What happens in the matrix
Arbitration: usually round-robin
© BME-MIT 2017 11.
Third generation of Cortex M3
2009: STM32F107 (Max 72 MHz)
© BME-MIT 2017 12.
Third generation of Cortex M3
• 2009: LPC1768
© BME-MIT 2017 13.
Negyedik Cortex M3 generáció• 2010: Az STM32F2xx belső buszszerkezete
© BME-MIT 2017 14.
Internal architecture of the most
widespread Cortex M0 based micros
© BME-MIT 2017 15.
Back to the Neumann architecture
ARM7TDMI Cortex M3 Cortex M0
© BME-MIT 2017 16.
LPC800
AHB-Liteo Reduced bus
complexity
o 1 Master/layer
Switch Matrix
© BME-MIT 2017 17.
Internal architecture of the most
widespread Cortex M4 based micros
© BME-MIT 2017 18.
STMF4xxx
© BME-MIT 2017 19.
LPC4300 family Cortex-M4 based Digital Signal Controller Cortex-M0 subsystem for peripheral functions max. 1 MByte Flash
o Organised into two banks Flash
Max. 200 kbyte SRAM High speed USB Features
o 10/100 Ethernet MACo LCD panel controller (max. 1024H × 768V)o 2x10-bit ADC and 10-bit DAC at 400 kspso 8 channel DMA controllero Motor Control PWM, Quadrature Encodero 4x UARTs, 2x I2C, I2S, CAN 2.0B, 2x SSP/SPI
© BME-MIT 2017 20.
LPC4300 internal architecture
© BME-MIT 2017 21.
Memory system of LPC43xx
Dual Core
o Both the M4 and M0 core can accesses the Flash
o RAM can be used to share data
o The MPU of M4 can protect the regions used by the M0 core
© BME-MIT 2017 22.
Internal architecture of the most
widespread Cortex M7 based micros
© BME-MIT 2017 23.
STM32F7xx
© BME-MIT 2017 24.
System Control Block
© BME-MIT 2017 25.
System Control block
Selecting the clock source of the systemo External Quartz Crystal, Internal RC oscillator, Real-time quartz
PLL (Phase Locked Loop)o Determination of system clock rate
Determination of the peripheral clock rateso Specifying the relationship between the system clock rate and
peripheral bus clock rates
Controlling the Flash accesso Flash acceleration, Number of wait cycles
Controlling the power source of peripheralso In modern microcontrollers every peripheral can be switched on or
off.
Determination of pin alternate functions
© BME-MIT 2017 26.
Reset
© BME-MIT 2017 27.
The Reset event
Source of the reset signal
o Power-on
o Watchdog
o Brown – out
o External pin
o Software
The source of the reset is identifiable by reading a register
What happens after the reset event?
© BME-MIT 2017 28.
The NVIC vectors
247
…………………..
7
6
5
N.A.
4
3
N.A.
2
1
0
-1
-2
-3 (Highest)
Priority
256
……
16
15
14
13
12
11
7-10
6
5
4
3
2
1
No.
External Interrupt #0settableInterrupt #0
External Interrupt #240settableInterrupt#240
…………………..settable…………………..
System Tick TimersettableSYSTICK
Pendable request for System DevicesettablePendSV
N.A.Reserved
Break points, watch points, external debugsettableDebug Monitor
System Service callsettableSVCall
N.A.Reserved
Exceptions due to program errorssettableUsage Fault
Fault if AHB interface receives errorsettableBus Fault
MPU violation or access to illegal locationssettableMemManage Fault
Default fault if other hander not implementedfixedHard Fault
Non-Maskable InterruptfixedNMI
ResetfixedReset
DescriptionsType of Priority
Exception Type
247
…………………..
7
6
5
N.A.
4
3
N.A.
2
1
0
-1
-2
-3 (Highest)
Priority
256
……
16
15
14
13
12
11
7-10
6
5
4
3
2
1
No.
External Interrupt #0settableInterrupt #0
External Interrupt #240settableInterrupt#240
…………………..settable…………………..
System Tick TimersettableSYSTICK
Pendable request for System DevicesettablePendSV
N.A.Reserved
Break points, watch points, external debugsettableDebug Monitor
System Service callsettableSVCall
N.A.Reserved
Exceptions due to program errorssettableUsage Fault
Fault if AHB interface receives errorsettableBus Fault
MPU violation or access to illegal locationssettableMemManage Fault
Default fault if other hander not implementedfixedHard Fault
Non-Maskable InterruptfixedNMI
ResetfixedReset
DescriptionsType of Priority
Exception Type
Reset vector is at 0x00000004
o The 0x00000000 is the stack pointer to enable the early usage of C language
Mic
roco
ntr
olle
rsp
ecific
© BME-MIT 2017 29.
The startup flow
© BME-MIT 2017 30.
Embedded boot code
Since the first ARM7 core micro
o The Flash programing is a non trivial task
• Uploading the code to the RAM and from there programming the Flash
o There lack of support for JTAG based debugging at the early ages
Built in bootcode
o Supporting the Flash programing
o Where is it and how can it be started?
© BME-MIT 2017 31.
Where is the boot code
STM32F107
© BME-MIT 2017 32.
STM32Fxxx Boot configuration
Based on the state of two external pins during reset
© BME-MIT 2017 33.
Flash acceleration
© BME-MIT 2017 34.
Flash memory
The Flash requires less space than RAM, but slower
Read access time of Flash is about>o 30ns - 50ns (33 –25 MHz)
This is too slow to run the micro at 60, 72, 120, 180, 200, 300 MHz
Solutionso Run the code from RAM
• But, the RAM is costly and not power efficient
o Increase the bus width of the Flash memory• 64bit, 128 bit• Increase complexity
© BME-MIT 2017 35.
The solution used at STM32F10x at 2009
2 pieces of 64-bit prefetch buffer
Need to program the number of wait cycles
© BME-MIT 2017 36.
Solution used in the LPC1768 at 2010
8 pieces of 128-bit buffer
Can fetch constant data
© BME-MIT 2017 37.
Performance of the Falsh accelerator in the LPC1768
Comparing to a RAM based execution
o The executing speed is in a 16% region to the RAM based execution
o The power consumption is 25% less
Comparing to the old ARM7 version with 128-bit Flash access
o 45% increase in performance
© BME-MIT 2017 38.
Benchmark results
0
0.5
1
1.5
2
2.5
3
a2
time
aifft
r
aifirf
aiif
ft
ba
sefp
bitm
np
cach
eb
ca
nrd
r
idct
rn
iirflt
ma
trix
pn
trch
pu
wm
od
rsp
ee
d
tblo
ok
ttsp
rk
EEMBC Benchmark
Rela
tive p
erf
orm
an
ce
LPC2376
LPC17XX
M3 Comp
© BME-MIT 2017 39.
STM32F2xx/STM32F4xx the latest solution
© BME-MIT 2017 40.
STM32F2xx/STM32F4xx the latest solution
© BME-MIT 2017 41.
Clock systems
© BME-MIT 2017 42.
Problems of clock distribution
Many type of source clock sources
o Quartz Crystal
• Precise, stable, but costly
o RC oscillator
• Un-Precise, cheap
Many requirements from the peripheral set
o Simple base peripherals
o I/O pins
o Ethernet
o USB
© BME-MIT 2017 43.
Second generation of Cortex M3
2007: STM32F103 (Max 72 MHz)
• APB1: max. 72MHz• APB2: max. 36MHz
© BME-MIT 2017 44.
Clock tree of the STM32F1xx
TIMxCLK
TIM2,3,4
APB1 Prescaler
/1,2,4,8,16
AHB Prescaler/1,2…512
If (APB1 pres
=1) x1Else x2
PCLK1 up to 36MHz
TIM1CLK APB2
Prescaler/1,2,4,8,16
If (APB2 pres
=1) x1Else x2
PCLK2 up to 72MHz
ADC Prescaler/2,4,6,8
ADCCLK
HCLK up to 72MHz
TIMxCLK
TIM2,3,4
APB1 Prescaler
/1,2,4,8,16
AHB Prescaler/1,2…512
If (APB1 pres
=1) x1Else x2
PCLK1 up to 36MHz
TIM1CLK APB2
Prescaler/1,2,4,8,16
If (APB2 pres
=1) x1Else x2
PCLK2 up to 72MHz
ADC Prescaler/2,4,6,8
ADCCLK
HCLK up to 72MHz
USB Prescaler
/1,1.5
USBCLK 48MHz
USB Prescaler
/1,1.5
USBCLK 48MHz
CSSCSS
HSE Osc
OSC_OUT
OSC_IN
4 -16 MHz
up to 72 MHz
SYSCLKx2...x16 PLL
PLLCLK
HSI RC
/2
/2
8MHz
HSE Osc
OSC_OUT
OSC_IN
4 -16 MHz
up to 72 MHz
SYSCLKx2...x16 PLL
PLLCLK
HSI RC
/2
/2
HSE Osc
OSC_OUT
OSC_IN
4 -16 MHz
up to 72 MHz
SYSCLKx2...x16 PLL
PLLCLK
HSI RC
/2
/2
HSE OscHSE Osc
OSC_OUT
OSC_IN
4 -16 MHz
OSC_OUT
OSC_IN
4 -16 MHz
up to 72 MHz
SYSCLK
up to 72 MHz
SYSCLKx2...x16 PLL
PLLCLK
HSI RC
/2
x2...x16 PLL
PLLCLK
HSI RC
/2
HSI RC
/2
/2/2
8MHz
LSI RC
32.768KHz
/128
LSE OSc
OSC32_IN
OSC32_OUT
~40KHz IWDGCLK
RTCCLK
LSI RC
32.768KHz
/128
LSE OSc
OSC32_IN
OSC32_OUT
~40KHz IWDGCLK
RTCCLK
© BME-MIT 2017 45.
Clock tree of the STM32F4xx
© BME-MIT 2017 46.
Problems caused by the clock tree
A simple LED switching requires at least 1 clock setting, but for a complex micro 3-4 clock config parameters should be programed
© BME-MIT 2017 47.
Peripheral power also should be checked Very microcontroller specific
© BME-MIT 2017 48.
Alternate functions of pins
Very similar method used by every microcontroller
© BME-MIT 2017 49.
CMSIS
Cortex Microcontroller
Software Interface Standard
© BME-MIT 2017 50.
Software versus Hardware development costs
© BME-MIT 2017 51.
CMSIS architecture (v1.3)
© BME-MIT 2017 52.
CMSIS Core
Hardware Abstraction Layer (HAL): Standardized peripheral handling for al Cortex M core variant. Standard for register access and internal peripheral functions like SysTick, NVIC, MPU and FPU.
Exception handling: Standardized names and function interfaces
Header file organization: Naming conventions
System start: Standardized SystemInit() function to cover microcontroller specific clock startups
Support for special instructions
Global variable for system clock frequncy
© BME-MIT 2017 53.
CMSIS core files
© BME-MIT 2017 54.
The device.h
stm32f10x.h
device.h
core_cm3.h
system_stm32f10x.h
stdint.h
CMSIS
One and only include file for starting the system
© BME-MIT 2017 55.
The startup_device file
Startup is compiler dependent
This file contains the Startup Code
The vector table is defined with weak pragmas
DCD USART1_IRQHandler, /* USART1 interrupt vector*/
#pragma weakUSART1_IRQHandler = Default_Handler
© BME-MIT 2017 56.
The system_device.c
Minimum services to start the microcontroller
Function
void SystemInit (void)Function to set up the system clocks
void SystemCoreClockUpdate (void) Upgrading the system clock.
Variable description
uint32_t SystemCoreClock The current value of the system clock.
description
© BME-MIT 2017 57.
CMSIS coding guildlines
Based on MISRA 2004
Data types based on <stdint.h>
All functions of Core Peripheral Access Layer (CPAL) should be reentrant. There is no blocking code
All of the interrupt rutins should end with _IRQHandler
Function use CamelCase naming
Doxygen comments are used
© BME-MIT 2017 58.
CMSIS architecture improvements (v5)
© BME-MIT 2017 59.
CMSIS DSP library
Designed for Cortex M4 and M3, including assembly code utilizing the specialties of the instruction set
Basic math functions
o Vector multiplication, subtraction, adding
Fast complex math functions
o Cosinus, Sinus, Square root
o Complex number handling
Filter rutins
o FIR, IIR
© BME-MIT 2017 60.
CMSIS Driver API
Microcontroller vendor independent API
© BME-MIT 2017 61.
CMSIS RTOS
Microcontroller independent RTOS abstraction
© BME-MIT 2017 62.
CMSIS RTOS
Kernel handling functions
© BME-MIT 2017 63.
CMSIS RTOS
Thread management functions
© BME-MIT 2017 64.
CMSIS RTOS
General purpose timing functions
OS timer functionality
