ARM Architecture

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ARM

The ARM logo

Designer ARM Holdings

Bits 32-bit & 64-bit implementations

Introduced 1985

Version ARMv8[1]

Design RISC

Type Register-Register

Encoding Fixed

Branching Condition code

Endianness Bi (Little as default)

Extensions NEON, Thumb, Jazelle, VFP, A64

Registers

16/31[1]

ARM architectureFrom Wikipedia, the free encyclopedia

The ARM architecture describes a family of RISC-basedcomputer processors designed and licensed by Britishcompany ARM Holdings. It was first developed in the

1980s[2] and globally as of 2013 is the most widely used 32-bit instruction set architecture in terms of quantity

produced.[3][4] In 2011 alone, producers of chips based onARM architectures reported shipments of 7.9 billion ARM-based processors, representing 95% of smartphones, 90% of

hard disk drives[citation needed], 40% of digital televisionsand set-top boxes, 15% of microcontrollers and 20% of

mobile computers.[5]

As an IP core business, ARM Holdings itself does notmanufacture its own electronic chips, but licenses its designsto other semiconductor manufacturers. ARM-basedprocessors and systems on a chip include the QualcommSnapdragon, nVidia Tegra, and Texas Instruments OMAP,as well as ARM's Cortex series and Apple System on Chips(used in its iPhones). The name was originally an acronym forAdvanced RISC Machine, and in its early days Acorn RISC

Machine.[6]

Using a RISC based approach to computer design, ARMprocessors require significantly fewer transistors thanprocessors that would typically be found in a traditionalcomputer. The benefits of this approach are lower costs, lessheat, and less power usage, traits that are desirable for use inlight, portable, battery-powered devices such as smart

phones and tablet computers.[7] The reduced complexity andsimpler design allows companies to build a low-energysystem on a chip for an embedded system incorporating memory, interfaces, radios, etc. The earliest example wasthe Apple Newton tablet but this same approach is still used in the Apple A4 and A5 chips in the iPad.

ARM periodically releases updates to its core currently ARMv7 and ARMv8 which chip manufacturers canthen license and use for their own devices. Variants are available for each of these to include or exclude optionalcapabilities. Current versions use 32-bit instructions with 32-bit addressed 1 byte wide memory which is effectivelyreduced to just over 24 bit addressing due to 4 byte alignment, with some addressing reserved in bytewiseallocation for Memory Mapped I/O, but accommodates 16-bit instructions for economy and can also handle Javabytecodes which use 32-bit addresses. More recently, ARM architecture has included 64-bit versions in 2012,Microsoft produced its new Surface tablet with ARM technology and AMD announced that it would start

producing server chips based on the 64-bit ARM core in 2014.[8]



Contents

1 Features and applications

2 Licensees

3 History

3.1 Acorn RISC Machine: ARM2

3.2 Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale

3.3 Licensing

4 ARM cores

5 Example applications of ARM cores

6 Architecture

6.1 CPU modes

6.2 Instruction set6.2.1 Arithmetic instructions

6.2.2 Registers

6.2.3 Conditional execution

6.2.4 Other features

6.2.5 Pipelines and other implementation issues6.2.6 Coprocessors

6.3 Debugging6.4 DSP enhancement instructions

6.5 Jazelle6.6 Thumb

6.7 Thumb-26.8 Thumb Execution Environment (ThumbEE)

6.9 Floating-point (VFP)6.10 Advanced SIMD (NEON)

6.11 Security Extensions (TrustZone)6.12 No-execute page protection6.13 ARMv8 and 64-bit

7 ARM licensees7.1 Approximate licensing costs

8 Operating systems8.1 Historical operating systems

8.2 Embedded operating systems8.3 Mobile Device operating systems

8.4 Desktop operating systems9 See also

10 References11 Further reading12 External links

Features and applications



Microprocessor-based system on a chip

As of 2005, about 98% of the more than one billion mobile

phones sold each year used at least one ARM processor.[9]

As of 2009, ARM processors accounted for approximately

90% of all embedded 32-bit RISC processors[10] and wereused extensively in consumer electronics, including personaldigital assistants (PDAs), tablets, mobile phones, digitalmedia and music players, hand-held game consoles,

calculators[citation needed] and computer peripherals such

as hard drives[citation needed] and routers.

Licensees

The ARM architecture is licensable. Companies that arecurrent or former ARM licensees include Advanced Micro

Devices, Inc.,[11] Alcatel-Lucent, Apple Inc.,AppliedMicro, Atmel, Broadcom, Cirrus Logic, CSR plc,Digital Equipment Corporation, Ember, Energy Micro,Freescale, Fujitsu, Fuzhou Rockchip, Huawei, Intel(through DEC), LG, Marvell Technology Group,Microsemi, Microsoft, NEC, Nintendo, Nuvoton, Nvidia,NXP (formerly Philips Semiconductor), Oki, ONSemiconductor, Panasonic, Qualcomm, Renesas, BlackBerry(formerly Research In Motion), Samsung, Sharp,Silicon Labs, Sony, ST-Ericsson, STMicroelectronics, Symbios Logic, Texas Instruments, Toshiba, Yamaha,Xilinx, and ZiiLABS.

ARM offers several microprocessor core designs, including the ARM7, ARM9, ARM11, Cortex-A8, Cortex-A9,and Cortex-A15. Companies often license these designs from ARM to manufacture and integrate into their ownsystem on a chip (SoC) with other components like RAM, GPUs, or radio basebands (for mobile phones).

System-on-chip packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc'sQuatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAPproducts, Samsung's Hummingbird and Exynos products, Apple's Ax SoC line, and Freescale's i.MX.

Companies can also obtain an ARM architectural license for designing their own CPU cores using the ARMinstruction set. Distinct ARM architecture implementations by licensees include Apple's A6, AppliedMicro's X-Gene, Qualcomm's Snapdragon and Krait, DEC's StrongARM, Marvell (formerly Intel) XScale, and Nvidia'splanned Project Denver.

History

Originally conceived by Acorn Computers for use in its personal computers, the first ARM-based products werethe co-processor modules for the BBC Micro series of computers. After achieving success with the BBC Microcomputer, Acorn Computers Ltd considered how to move on from the relatively simple MOS Technology 6502processor to address business markets like the one that would soon be dominated by the IBM PC, launched in1981. The Acorn Business Computer (ABC) plan required a number of second processors to be made to workwith the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016

were considered to be unsuitable, and the 6502 was not powerful enough for a graphics based user interface.[12]



A Conexant ARM processor used

mainly in routers

The ARM1 second processor for the

BBC Micro

After testing all of the available processors and finding them lacking, Acorn decided that it needed a newarchitecture. After reading white papers on the Berkeley RISC project, Acorn seriously considered designing itsown processor. They reasoned if a class of graduate students could create a competitive 32-bit processor, thenAcorn would have no problem. A visit to the Western Design Center in Phoenix, where the 6502 was being

updated by what was effectively a single-person company, showed Acorn engineers Steve Furber[13] and SophieWilson they did not need massive resources and state-of-the-art R&D facilities.

Wilson developed the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Microwith a second 6502 processor. This convinced the Acorn engineers that they were on the right track. Wilsonapproached Acorn's CEO, Hermann Hauser, and requested more resources. Once approval was given, a smallteam was assembled to implement Wilson's model in hardware.

Acorn RISC Machine: ARM2

The official Acorn RISC Machine project started in October 1983.VLSI Technology, Inc was chosen as the "silicon partner," as they werea source of ROMs and custom chips for Acorn. The design was led byWilson and Furber, and was consciously implemented with a similar

efficiency ethos as the 6502.[14] A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502'smemory access architecture had allowed developers to produce fastmachines without using costly direct memory access hardware. VLSIproduced the first ARM silicon on 26 April 1985 it worked the first

time, and was known as ARM1 by April 1985.[2] The first productionsystems named ARM2 were available the following year.

The first practical application of the ARM was as a second processor forthe BBC Micro, where it saw use developing the simulation software tofinish development of the support chips (VIDC, IOC, MEMC), and tospeed up the CAD software used in ARM2 development. Wilsonsubsequently rewrote BBC Basic in ARM assembly language, and the in-depth knowledge obtained from designing the instruction set enabled thecode to be very dense, making ARM BBC Basic an extremely good testfor any ARM emulator. The original aim of a principally ARM-basedcomputer was achieved in 1987 with the release of the Acorn

Archimedes.[15]

In 1992, Acorn once more won the Queen's Award for Technology forthe ARM.

The ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers. Program code had to liewithin the first 64 Mbyte of memory, as the program counter was limited to 24 bits because the top 6 and bottom 2bits of the 32-bit register served as status flags. The ARM2 had a transistor count of just 30,000, compared toMotorola's six-year-older 68000 model with 68,000. Much of this simplicity comes from the lack of microcode(which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including any

cache. This simplicity enabled low power consumption, yet better performance than the Intel 80286.[16] Asuccessor, ARM3, was produced with a 4 KB cache, which further improved performance.



Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale

In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of theARM core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd.Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings plc, floated on the

London Stock Exchange and NASDAQ in 1998.[17]

The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used theARM6-based ARM 610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM 610 as themain central processing unit (CPU) in their Risc PC computers. DEC licensed the ARM6 architecture andproduced the StrongARM. At 233 MHz, this CPU drew only one watt (newer versions draw far less). This workwas later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their i960line with the StrongARM. Intel later developed its own high performance implementation named XScale which ithas since sold to Marvell.

Licensing

The ARM core has remained essentially the same size throughout these changes. ARM2 had 30,000 transistors,the ARM6 grew only to 35,000. ARM's primary business is selling IP cores, which licensees use to createmicrocontrollers and CPUs based on those cores. The original design manufacturer combines the ARM core withother parts to produce a complete CPU, typically one that can be built in existing semiconductor fabs at low costand still deliver substantial performance. The most successful implementation has been the ARM7TDMI withhundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system.

The ARM architectures used in smartphones, personal digital assistants and other mobile devices range fromARMv5, used in low-end devices, to ARMv6, to the Cortex A-Series (ARMv7) in current high-end devices.ARMv7 includes a hardware floating point unit, with improved speed compared to software-based floating point.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with

netbooks based on Intel Atom.[18] According to analyst firm IHS iSuppli, by 2015, ARM ICs are estimated to be

in 23% of all laptops.[19]

In 2011, HiSilicon Technologies Co. Ltd. licensed ARM technology for use in communications chip designs. These

included 3G/4G base stations, networking infrastructure and mobile computing applications.[20]

ARM cores

Main article: List of ARM microprocessor cores



Architecture Family

ARMv1 ARM1

ARMv2 ARM2, ARM3

ARMv3 ARM6, ARM7

ARMv4 StrongARM, ARM7TDMI, ARM9TDMI

ARMv5 ARM7EJ, ARM9E, ARM10E, XScale

ARMv6 ARM11

ARMv6-M ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1

ARMv7ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A15,

ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7

ARMv7-M ARM Cortex-M3, ARM Cortex-M4

ARMv8-A ARM Cortex-A53, ARM Cortex-A57 [21]

A list of vendors who implement ARM cores in their design is provided by ARM.[22]

Example applications of ARM cores

Main article: List of applications of ARM cores

ARM cores are used in a number of products, particularly PDAs and smartphones. Some computing examples arethe Microsoft Surface, Apple iPad and ASUS Eee Pad Transformer. Others include the Apple iPhone smartphone,iPod portable media player, Canon PowerShot A470 digital camera, Nintendo DS handheld game console andTomTom turn-by-turn navigation system.

In 2005, ARM took part in the development of Manchester University's computer, SpiNNaker, which used ARM

cores to simulate the human brain.[23]

ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard, and other Single-boardcomputers, because they are very small, inexpensive and consume very little power.

Architecture

From 1995, the ARM Architecture Reference Manual (http://infocenter.arm.com/help/index.jsp) has been theprimary source of documentation on the ARM processor architecture and instruction set, distinguishing interfacesthat all ARM processors are required to support (such as instruction semantics) from implementation details thatmay vary. The architecture has evolved over time, and starting with the Cortex series of cores, three "profiles" aredefined:

"Application" profile: Cortex-A series

"Real-time" profile: Cortex-R series

"Microcontroller" profile: Cortex-M series.



Profiles are allowed to subset the architecture. For example, the ARMv6-M profile (used by the Cortex M0 / M0+/ M1) is a subset of the ARMv7-M profile which supports fewer instructions.

CPU modes

The ARM architecture specifies the following eight (8) CPU modes. At any moment in time, the CPU can be inonly one mode, but it can switch modes due to external events (interrupts) or programmatically.

User mode

The only non-privileged mode.

System mode

The only privileged mode that is not entered by an exception. It can only be entered by executing an

instruction that explicitly writes to the mode bits of the CPSR.

Supervisor (svc) mode

A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed.

Abort modeA privileged mode that is entered whenever a prefetch abort or data abort exception occurs.

Undefined mode

A privileged mode that is entered whenever an undefined instruction exception occurs.

Interrupt mode

A privileged mode that is entered whenever the processor accepts an IRQ interrupt.

Fast Interrupt mode

A privileged mode that is entered whenever the processor accepts an FIQ interrupt.Hyp mode

A hypervisor mode introduced in armv-7a for cortex-A15 processor for providing hardware virtualization

support.

Instruction set

The original ARM implementation was hardwired without microcode, like the much simpler 8-bit 6502 processorused in prior Acorn microcomputers.

The ARM architecture includes the following RISC features:

Load/store architecture.No support for misaligned memory accesses (although now supported in ARMv6 cores, with some

exceptions related to load/store multiple word instructions).

Uniform 16 32-bit register file.

Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density.

Later, the Thumb instruction set increased code density.

Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, someadditional design features were used:

Conditional execution of most instructions, reducing branch overhead and compensating for the lack of abranch predictor.



Arithmetic instructions alter condition codes only when desired.32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and

address calculations.

Powerful indexed addressing modes.

A link register for fast leaf function calls.

Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.

Arithmetic instructions

The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented byARM cores based on the following ARM architectures:

ARMv7-M and ARMv7E-M architectures always includes divide instructions.[24]

ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in the

ARM instruction set.[25]

ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented,

or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions

sets, or implemented if the Virtualization Extensions are included.[25]

Registers

Registers R0-R7 are the same across all CPU modes; they are never banked.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can beentered because of an exception has its own R13 and R14. These registers generally contain the stack pointer andthe return address from function calls, respectively.



Registers across CPU modes

usr sys svc abt und irq fiq

R0

R1

R2

R3

R4

R5

R6

R7

R8 R8_fiq

R9 R9_fiq

R10 R10_fiq

R11 R11_fiq

R12 R12_fiq

R13 R13_svc R13_abt R13_und R13_irq R13_fiq

R14 R14_svc R14_abt R14_und R14_irq R14_fiq

R15

CPSR

SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

Aliases:

R13 is also referred to as SP, the Stack Pointer.

R14 is also referred to as LR, the Link Register.R15 is also referred to as PC, the Program Counter.

Conditional execution

The conditional execution feature (called predication) is implemented with a 4-bit condition code selector (thepredicate) on every instruction; one of the four-bit codes is reserved as an "escape code" to specify certainunconditional instructions, but nearly all common instructions are conditional. Most CPU architectures only havecondition codes on branch instructions.

This cuts down significantly on the encoding bits available for displacements in memory access instructions, butavoids branch instructions when generating code for small if statements. The standard example of this is the

subtraction-based Euclidean algorithm:

In the C programming language, the loop is:



while (i != j) { if (i > j) i -= j; else j -= i; }

In ARM assembly, the loop is:

loop: CMP Ri, Rj ; set condition "NE" if (i != j), ; "GT" if (i > j), ; or "LT" if (i < j) SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j; SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i; BNE loop ; if "NE" (not equal), then loop

which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of the SUB

instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top

of the loop, for example had SUBLE (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from non-branch instructions.

Other features

Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic,logical, and register-register move) instructions, so that, for example, the C statement

a += (j



The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier (hence theadded "M").

Coprocessors

The ARM architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which canbe addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is dividedlogically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typicalcontrol functions like managing the caches and MMU operation (on processors that have one).

In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physicalregisters into ARM memory space or into the coprocessor space or connecting to another device (a bus) which inturn attaches to the processor. Coprocessor accesses have lower latency so some peripherals (for example anXScale interrupt controller) are designed to be accessible in both ways (through memory and throughcoprocessors).

In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an imageprocessing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operationsto support a specific set of HDTV transcoding primitives.

Debugging

All modern ARM processors include hardware debugging facilities, allowing software debuggers to performoperations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built usingJTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. InARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an"EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a defacto debug standard, although it was not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints,watchpoints, and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE.Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access thedebug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7processors.

DSP enhancement instructions

To improve the ARM architecture for digital signal processing and multimedia applications, DSP instructions were

added to the set.[27] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.

The new instructions are common in digital signal processor architectures. They include variations on signedmultiplyaccumulate, saturated add and subtract, and count leading zeros.

Jazelle



Main article: Jazelle

Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java Bytecode to be executed directly in theARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode.Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-Score names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), althoughnewer cores only include a trivial implementation that provides no hardware acceleration.

Thumb

To improve compiled code-density, processors since the ARM7TDMI (released in 1994[28]) have featuredThumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in thisstate, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM

instruction set.[29] Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilitiescompared to the ARM instructions executed in the ARM instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and manyopcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodesgive improved code density overall, even though some operations require extra instructions. In situations where thememory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increasedperformance compared with 32-bit ARM code, as less program code may need to be loaded into the processorover the constrained memory bandwidth.

Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usuallymakes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bitARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, includingXScale, have included a Thumb instruction decoder.

Thumb-2

Thumb-2 technology was introduced in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thusproducing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumbwith performance similar to the ARM instruction set on 32-bit memory. In ARMv7 this goal can be said to have

been met.[citation needed]

Thumb-2 extends both the ARM and Thumb instruction set with bit-field manipulation, table branches, andconditional execution. A new "Unified Assembly Language" (UAL) supports generation of either Thumb-2 or ARMinstructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capableas ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition. Whencompiling into ARM code this is ignored, but when compiling into Thumb-2 it generates an actual instruction. Forexample:



; if (r0 == r1)CMP r0, r1ITE EQ ; ARM: no code ... Thumb: IT instruction; then r0 = r2;MOVEQ r0, r2 ; ARM: conditional; Thumb: condition via ITE 'T' (then); else r0 = r3;MOVNE r0, r3 ; ARM: conditional; Thumb: condition via ITE 'E' (else); recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

All ARMv7 chips support the Thumb-2 instruction set. Other chips in the Cortex and ARM11 series support both

"ARM instruction set state" and "Thumb-2 instruction set state".[30][31][32]

Thumb Execution Environment (ThumbEE)

ThumbEE, also termed Thumb-2EE, and marketed as Jazelle RCT(http://www.arm.com/products/processors/technologies/jazelle.php) (Runtime Compilation Target), was announcedin 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth processor mode, making small changesto the Thumb-2 extended Thumb instruction set. These changes make the instruction set particularly suited to codegenerated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target forlanguages such as Java, C#, Perl, and Python, and allows JIT compilers to output smaller compiled code without

impacting performance. On 23 November 2011, ARM deprecates any use of the ThumbEE instruction set.[33]

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, aninstruction to perform an array bounds check, access to registers r8-r15 (where the Jazelle/DBX Java VM state is

held), and special instructions that call a handler.[34] Handlers are small sections of frequently called code,commonly used to implement high level languages, such as allocating memory for a new object. These changescome from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE mode.

Floating-point (VFP)

VFP (Vector Floating Point) technology is an FPU coprocessor extension to the ARM architecture. It provideslow-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable fora wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecturewas intended to support execution of short "vector mode" instructions but these operated on each vector elementsequentially and thus did not offer the performance of true single instruction, multiple data (SIMD) vector

parallelism. This vector mode was therefore removed shortly after its introduction,[35] to be replaced with the muchmore powerful NEON Advanced SIMD unit.

Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, and

require roughly ten times more clock cycles per float operation.[36] Other floating-point and/or SIMD coprocessorsfound in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality asVFP but are not opcode-compatible with it.

Advanced SIMD (NEON)



The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and 128-bitsingle instruction multiple data (SIMD) instruction set that provides standardised acceleration for media and signal

processing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices.[37]

NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM adaptive multi-rate(AMR) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files

and independent execution hardware.[38] NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics andgaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardwareshares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9

support 128-bit vectors but will execute with 64 bits at a time,[36] whereas newer Cortex-A15 devices can execute128 bits at a time.

Security Extensions (TrustZone)

The Security Extensions, marketed as TrustZone Technology, is found in ARMv6KZ and later application profilearchitectures. It provides a low cost alternative to adding an additional dedicated security core to an SoC, byproviding two virtual processors backed by hardware based access control. This enables the application core toswitch between two states, referred to as worlds (to reduce confusion with other names for capability domains), inorder to prevent information from leaking from the more trusted world to the less trusted world. This world switchis generally orthogonal to all other capabilities of the processor, thus each world can operate independently of theother while using the same core. Memory and peripherals are then made aware of the operating world of the coreand may use this to provide access control to secrets and code on the device.

Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, andsmaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone optimisedversion of the Trusted Foundations Software developed by Trusted Logic Mobility (http://www.tl-mobility.com) ),

allowing much tighter digital rights management for controlling the use of media on ARM-based devices,[39] andpreventing any unapproved use of the device. Trusted Foundations Software was acquired by Gemalto. Giesecke& Devrient developed a rival implementation named Mobicore. In April 2012 ARM Gemalto and Giesecke &

Devrient combined their Trustzone portfolios into a joint venture[40] Trustonic (http://www.trustonic.com) . OpenVirtualization (http://www.openvirtualization.org) is an open source implementation of the trusted world architecturefor TrustZone.

In practice, since the specific implementation details of TrustZone are proprietary and have not been publiclydisclosed for review, it is unclear what level of assurance is provided for a given threat model.

No-execute page protection

As of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for

eXecute Never.[41]

ARMv8 and 64-bit

Released in late 2011, ARMv8 represents a fundamental change to the ARM architecture. It adds a 64-bitarchitecture, dubbed 'AArch64', and a new 'A64' instruction set. Within the context of ARMv8, the 32-bitarchitecture and instruction set are referred to as 'AArch32' and 'A32', respectively. The Thumb instruction sets arereferred to as 'T32' and have no 64-bit counterpart. ARMv8 allows 32-bit applications to be executed in a 64-bit



OS, and for a 32-bit OS to be under the control of a 64-bit hypervisor.[1] Applied Micro, AMD, Broadcom,Calxeda, HiSilicon, Samsung, ST Microelectronics and other companies have announced implementation

plans.[42][43][44][45] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[21]

To both AArch32 and AArch64, ARMv8 makes VFPv3/v4 and advanced SIMD (NEON) standard. It also addscryptography instructions supporting AES and SHA-1/SHA-256.

AArch64 features:

New instruction set, A6431 general-purpose 64-bit registers

Instructions are still 32 bits long and mostly the same as A32Most instructions can take 32-bit or 64-bit arguments

Addresses assumed to be 64-bitAdvanced SIMD (NEON) enhanced

Has 32 128-bit registers (up from 16), also accessible via VFPv4Supports double-precision floating pointFully IEEE 754 compliant

AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registersA new exception system

Fewer banked registers and modesMemory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be

easily extended to 64-bit

OS support:

Linux patches adding ARMv8 support have been posted for review by Catalin Marinas of ARM ltd. The

patches have been included in Linux kernel version 3.7.[46]

ARM licensees

ARM Ltd does not manufacture or sell CPU devices based on its own designs, but rather, licenses the processorarchitecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To alllicensees, ARM provides an integratable hardware description of the ARM core, as well as complete softwaredevelopment toolset (compiler, debugger, SDK), and the right to sell manufactured silicon containing the ARMCPU.

Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested inacquiring a ready-to-manufacture verified IP core. For these customers, ARM delivers a gate netlist description ofthe chosen ARM core, along with an abstracted simulation model and test programs to aid design integration andverification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators,choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customerhas the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exoticdesign goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption,instruction set extensions, etc.). While ARM does not grant the licensee the right to resell the ARM architecture



itself, licensees may freely sell manufactured product (chip devices, evaluation boards, complete systems, etc.).Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores,they generally hold the right to re-manufacture ARM cores for other customers.

ARM prices its IP based on perceived value; lower performing ARM cores typically have lower license costs thanhigher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox)core. Complicating price matters, a merchant foundry which holds an ARM license (such as Samsung and Fujitsu)can offer reduced licensing costs to its fab customers. In exchange for acquiring the ARM core through thefoundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront license fee.Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services,Fujitsu/Samsung charge 2 to 3 times more per manufactured wafer. For low to mid volume applications, a designservice foundry offers lower overall pricing (through subsidisation of the license fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM'sNRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

Many semiconductor or IC design firms hold ARM licenses: Analog Devices, AppliedMicro, Atmel, Broadcom,Cirrus Logic, Energy Micro, Faraday Technology, Freescale, Fujitsu, Intel (through its settlement with DigitalEquipment Corporation), IBM, Infineon Technologies (Infineon XMC4000 32bit mcu family), Marvell TechnologyGroup, Nintendo, Nvidia, NXP Semiconductors, OKI, Qualcomm, Samsung, Sharp, STMicroelectronics, andTexas Instruments are some of the many companies who have licensed the ARM in one form or another.

Approximate licensing costs

ARM's 2006 annual report and accounts state that royalties totalling 88.7 million ($164.1 million) were the result

of licensees shipping 2.45 billion units.[47] This is equivalent to 0.036 ($0.067) per unit shipped. This is averagedacross all cores, including expensive new cores and inexpensive older cores.

In the same year ARM's licensing revenues for processor cores were 65.2 million (US$119.5 million),[48] in a

year when 65 processor licenses were signed,[49] an average of 1 million ($1.84 million) per license. Again, this isaveraged across both new and old cores.

Given that ARM's 2006 income from processor cores was approximately 60% from royalties and 40% fromlicenses, ARM makes the equivalent of 0.06 ($0.11) per unit shipped including both royalties and licenses.However, as one-off licenses are typically bought for new technologies, unit sales (and hence royalties) aredominated by more established products. Hence, the figures above do not reflect the true costs of any single ARMproduct.

Operating systems

Historical operating systems

The very first ARM-based Acorn Archimedes personal computers ran an interim operating system called Arthur,which evolved into RISC OS, used on later ARM-based systems from Acorn and other vendors.

Embedded operating systems



Android, a popular[50]

operating system running on

the ARM architecture

The ARM architecture is supported by a large number of embedded and real-time operating systems, includingWindows CE, Symbian, ChibiOS/RT, FreeRTOS, eCos, Integrity, Nucleus PLUS, MicroC/OS-II, QNX,RTEMS, RTXC Quadros, ThreadX, VxWorks, DRYOS, MQX and OSE.

Mobile Device operating systems

The ARM architecture is the primary hardware environment for most mobile device operating systems such as iOS,Windows Phone, Blackberry OS and Android.

Desktop operating systems

The ARM architecture is supported by Windows RT and multiple Unix-likeoperating systems, including BSD and various Linux distributions such as ChromeOS.

See also

AMULET microprocessorARMulator

OVPsimAmber (processor core)

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48. ^ Based on total 110.6 million ($202.5 million) divided by "License revenuesby product"; "Business review/Financial review/IFRS" and "Key performanceindicators" respectively, p. 10 / p. 3 ARM annual report and accounts, 2006(http://media.corporate-ir.net/media_files/irol/19/197211/reports/ar06.pdf) .Retrieved 7 May 2007.

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Further reading

The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN978-0-12-385477-3. (Online Sample) (http://books.google.com/books?id=5OZblBzjsJ0C&printsec=frontcover&dq=isbn:9780123854773)

The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN978-1-85617-963-8. (Online Sample) (http://books.google.com/books?

id=mb5d_xeINZEC&printsec=frontcover&dq=isbn:9781856179638)ARM Accredited Engineer certification program

External links

Official website (http://www.arm.com) , ARM Ltd.

Quick Reference Cards

Instructions: Thumb (1

(http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf) ), ARM and Thumb-2 (2 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf) ), Vector Floating

Point (3 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf) )Opcodes: Thumb (1 (http://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf) , 2

(http://www.mechcore.net/files/docs/ThumbRefV2-beta.pdf) ), ARM (3 (http://re-eject.gbadev.org/files/armref.pdf) , 4 (http://www.mechcore.net/files/docs/armref.pdf) ), GNU AssemblerDirectives 5 (http://re-eject.gbadev.org/files/GasARMRef.pdf) .

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