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7/25/2019 ARM 7
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Embedded Systemswith
ARM 7 Controller (!C "#$% &
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Syllab's ntrod'ction to ARM
Embedded Systems
Di)erence between 'C * '! Di)erence between RSC * CSC
nstr'ction +'e'e
nstr'ction !ipeline
ARM Architect're ARM Core Data ,low
ARM processor -amily / 0rs
E1ceptions * nterr'pt 0andling Application o- ARM !rocessor
Assembly ang'age 2or3ing with +EM4
Sample Assembly !rograms
!C"#$% Microcontroller
,eat'res o- !C"#$% 5loc3 diagram o- !C"#$%
!in diagram o- !C"#$%
Architect'ral overview
6nchip 8ash program memory
6nchip static RAM 9 0rs
ntrod'ction to Coding Environment
':E 2;ARM
!rogramming Concepts
!in Connect 5loc3
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Session #
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Embedded Systems
Combination o- hardware and so-twarethat per-orms a speciBc tas3. Is a system built to perform its duty,
completely or partially independent ofhuman intervention.
Is specially designed to perform a fewtasks in the most ecient way.
Interacts with physical elements in ourenvironment, e.g. controlling and driving amotor, sensing temperature
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Embedded SystemsCharacteristics
SpeciBc !'rpose
ery strict memorylimitations
!rocessorlimitations
Speed limitations
Cost imitations Acc'racy * iming
constraints
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Micro !rocessors s Micro
Controllers
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'C * '!
Micro Controllers SpeciBc !'rpose
C!4 with some
B1ed RAM R6M *other peripheralsembedded in asingle chip
Cloc3 speed is low Cost is less
Micro !rocessors
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E1isting Embedded C!4
Architect'res
ARMFs ARM architect're (/"bit&
ARM9$ (9$=/"bit&
AtmelFs AR architect're
MicrochipFs !C architect're
e1as nstr'mentHsMS!$/I architect're
ntelFs %IJ# architect're
KilogFs K%I architect're
2estern DesignCenterFs 9J%#9 architect're
0itachiFs S'per0 architect're
A1isComm'nicationsF ERAL
CRS architect're !ower
Architect're (-ormerly !ower!C&
EnSilicaFs eSi
RSC architect're Mil3ymist architect're
nmosF ransp'ter architect'res
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CSC * RSC
Comple1 nstr'ctionSet Comp'ting More n'mber o-
nstr'ctions ariable width
nstr'ctions
Macro nstr'ctions
More C!4 Cycles nstr'ction +'e'e
Concept
SimpliBed Compiler
Red'ced nstr'ctionSet Comp'ting ess n'mber o-
nstr'ctions ,i1ed 2idth
nstr'ctions
Micro nstr'ctions
ess C!4 Cycles
nstr'ction !ipelineConcept
SimpliBed nstr'ctions
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nstr'ction +'e'e
Stores one or more instr'ctions
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nstr'ction +'e'e
Stores one or more instr'ctions
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nstr'ction !ipeline
!arallel e1ec'tion o- m'ltiple instr'ctions
Reads consec'tive instr'ction -rom memory while previo'sinstr'ction are e1ec'ted in vario's stages o- pipeline
!ipeline Strategy nstr'ction pipelining is similar to the 'se o- an assembly line in a
man'-act'ring plant. An assembly line ta3es advantage o- the
-act that a prod'ct goes thro'gh vario's staged o- prod'ction. 5y laying the prod'ction process o't in an assembly line
prod'cts at vario's stages can be wor3ed on sim'ltaneo'sly. hisprocess is also re-erred to as pipelining beca'se as in a pipelinenew inp'ts are accepted at one end be-ore previo'sly acceptedinp'ts appear as o'tp'ts at the other end.
o apply this concept to instr'ction e1ec'tion we m'st recogni?ethat in -act an instr'ction has a n'mber o- stages.
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nstr'ction !ipeline
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Session "
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ARM Architect're
ARM !rocessor Core is a 3eycomponent o- many s'ccess-'l /"bitembedded systems.
ARM # !rototype in #%J
6ver # billion ARM !rocessors beingshipped by the end o- "II#
ARM Core ;ot a single core b'twhole -amily o- design shares similardesign * common instr'ction set.
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ARM Core Data ,low Model
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Registers
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C!SRC'rrent !rogram Stat's Register
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Seven 6perating Modes
4SER 4nprivileged mode 'nder which most tas3 r'n
,+ 0igh !riority interr'pt is raised
R+ ow priority interr'pt is raised
S'pervisor Most !rivileged
Abort nvalid memory access
4nde- 0andles 4nde- nstr'ctions
System Most !riviledged
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!rocessor Modes
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E1ceptions * nterr'pts
E1ception handling SpeciBc details o- how the ARM
!rocessor handles e1ceptions
nterr'pts ARM deBnes interr'pt as special type o-
E1ception
nterr'pt ReN'ests nterr'pts are at 0eart o- Embedded
Systems
nterr'pt handlersEmbedded Daemonswww.vjece.blogspot.in
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E1ception handling
A so-tware ro'tine that e1ec'tes when ane1ception occ'rs
Data Abort e1ception will have a Data Abort
0andler 0andler Brst determines the ca'se o-
e1ception and then services the e1ception
Servicing ta3es place either within the handler
or by branching to a speciBc service ro'tine Reset E1ception is a special e1ception
beca'se it initiali?es the embedded system
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ARM !rocessor E1ceptionModes
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ector able
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E1ception !riority evels
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/ level ;ested nterr'pt
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!roced're o- 0andlingnterr'pt
An R+ or ,+ e1ception ca'ses the processor hardware togo thro'gh a standard proced're (provided the interr'ptsare not mas3ed&>
#. he processor changes to a speciBc interr'pt reN'est modewhich re8ects the interr'pt
being raised.". he previo's modeHs cpsr is saved into the spsr o- the newinterr'pt reN'est mode./. he pc is saved in the lr o- the new interr'pt reN'est mode.$. nterr'pt=s are disabledOeither the R+ or both R+ and ,+e1ceptions are disabled
in the cpsr. his immediately stops another interr'pt reN'est o- thesame type beingraised.J. he processor branches to a speciBc entry in the vector table.
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nterr'pt 0andling scheme
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nterr'pt 0andling scheme
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ARM Applications
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ARM 7 applications
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applications
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ARM## applications
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ARM Corte1M applications
Dell E$/IIatit'de aptop
instant boot'p-or 'sers andaccess to selectapplications
with m'ltidaybattery li-etimes
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ARM Corte1A applications
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ARM Corte1R
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Session /
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Assembly ang'age
nstr'ctions in te1t -orm
,low o- Assembly lang'age program .s .o .o't P in'1 Q
C !rogram ,low .c (!reprocessor& .i (Compiler& .s
(Assembler & .o (in3er &.o't
Advantage is we can observe allinstr'ctions in machine level andhelps in 'nderstanding.
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+EM4 nstallation J Mins
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+EM4
+EM4 is a FAST! processor em'lator 'sing dynamictranslation to achieve good em'lation speed.
+EM4 has two operating modes> ,'ll system em'lation. n this mode +EM4 em'lates a -'ll
system (-or e1ample a !C& incl'ding one or several
processors and vario's peripherals. t can be 'sed tola'nch di)erent 6perating Systems witho't rebooting the!C or to deb'g system code.
4ser mode em'lation. n this mode +EM4 can la'nchprocesses compiled -or one C!4 on another C!4. t can be
'sed to la'nch the 2ine 2indows A! em'lator (http>==www.winehN.org& or to ease crosscompilation andcrossdeb'gging.
+EM4 can r'n witho't an host 3ernel driver and yetgives acceptable per-ormance.
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+EM4 imitations
C'rrent +EM4 limitations>
imited 1%99$ s'pport.
!C syscalls are missing.
he 1%9 segment limits and accessrights are not tested at everymemory access (yet&. 0ope-'lly very-ew 6Ses seem to rely on that -ornormal 'se.
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Assembly ntrod'ction
Commonly 4sed nstr'ctions Moving
M6 M;
Arithmetic ADD S45 M4
5ranch 5 5L 5
ogical A;D 6RR E6R
Compare CM!
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Sample !rograms
Demo 'sing +EM4 4sing in'1 erminal
Some basic in'1 commands
Editor 2or3ing
Sample !rograms Addition s'btraction m'ltiplication
6dd or Even Arithmetic !rogression
4sing h'mb nstr'ctions
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Session $
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!C "#$% /" = #9 ARM7DMs C!4
Embedded 0igh Speed ,lash Memory
iny si?e * low !ower Cons'mption
+,!9$ pac3age
#"% bit wide nter-ace= Accelerator enables 0igh Speed 9I M0?
6peration 5lend o- Serial Comm'nication nter-ace
4S5 ".I ,'ll Speed Device
M'ltiple 4ARS
S! SS!
C
/" bit imers
#I bit ADC DAC
!2M Channels
$J ,ast
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!C"#$% development board
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!C"#$% development board
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Applications in
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Development boardschematic
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4nderstanding 4ser Man'al o- !C"#$%
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Session J!rogramming in ARM
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':E nstallation * ntrod'ction to!rogramming