1

iCBAS

iiiiABCCBACBACBA

iioACBCABC

ABG BAD

)( BAPorBAP

ioPCGPGC ),(

iCPPGS ),(

The Binary Adder:

2

Static Adder Circuit

iio ACBCABC

ioi CBACABCS

3

Complementary static CMOS implementation of full adder.

4

Mirror adder – circuit schematics

5

Dynamic full adder using the np CMOS logic style.

6

Layout of dynamic full adder using the np-CMOS logic style

7

Manchester carry-chain adder (5-bit section). The annotated numbers indicate the relative transistor sizes. A unit-size transistor measures

(6/1.2)

8

Equivalent network to determine propagation delay of carry chain

9Pipelined adder in NORA-CMOS

10

(a) Carry propagation

(b) Adding a bypass

Carry-bypass structure – basic concept.

11

sumcarrybypasscarrysetupp tMttMNMttt

1

12

(N=16) carry-bypass adder – composition. The worst-case delay path is shaded in gray

13

Propagation delay of ripple-carry versus carry-bypass adder.

14

Four-bit carry-select module – topology.

summuxcarrysetupadd ttMNMttt

15

16-bit, linear carry-select adder. The critical path is shaded in gray.

16

(a) Linear configuration

Worst-case signal arrival times in carry-select adders. The signal arrival times are marked in bold.

17

(b) Square root configuration

Worst-case signal arrival times in carry-select adders. The signal arrival times are marked in bold.

18

)1(....)3()2(1 PMMMMMN

21

22)1( 2

MPPPPMP

2

2PN

NP 2

summuxcarrysetupadd ttNMttt 2

19

Propagation delay of square-root carry-select adder versus linear ripple and select adders. The unit delay model is used to model the cell delays.

20

Schematic diagram of 4-bit lookahead adder

21

Configurations of associative operators.

22

pgg , pgp ,

0,000,00, PGGPCGC io

001,11011, ,PGPGPGGCo

0,01,1,, ... PGPGPGC kkkkko

...

23

0,00, PGCo

0,01,11, PGPGCo

0,01,12,23,33, PGPGPGPGCo

3,,3,74,747, ooo PCPCC

24

An 8-bit Brent-Kung structure. The forward binary tree is colored gray.

25

Binary multiplication – an example.

26

A 4 4 bit-array multiplier for unsigned numbers – composition.

27

andsumcarrymult ttNtNMt 121

Ripple-carry based 4 4 multiplier (simplified diagram). Two of the possible critical paths are highlighted.

28

Transmission-gate based full-adder cell with sum and carry delays of similar value.

29

A 4 4 carry-save multiplier. The critical path is highlighted in gray.

30

Rectangular floorplan of carry-save multiplier.

31

Barrel-shifter with a programmable shift-width from 0 to 3 bit to the right.

32

Logarithmic shifter with maximal shift width of 7 bits to the right