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Ar ithmetic, Logic, and ALU

Introduction

The ability to perform arithmetic and logical computations

Critical task for computer

ALU is common building block in most CPU type functionsDevice is able to perform variety of arithmetic and logical operations

On two N bit numbers

Generate N bit outputControl inputs specify operation to be performed

Most ALUs today can perform following operations

Simple operations

Basic addition, subtraction, multiplication, divisionIn very simple devices operations limited to

Addition and subtraction

Bit wise logical operationsAND, OR, NOR, XOR

Bit shift operations

Shifting or rotating wordLeft or right

With or without sign extension

Comparison

Complex operations

As complexity of supported operations increasesCost, size, and power all increase

Complexity can branch in different directions

Speed

Perform elementary arithmetic or logical operationsOne or several clock cycles

Barrel shifter is good example

Can shift data word specified number of bitsIn single clock cycle

Functionality

Implement operations such as floating point mathIn hardware

During course of our studiesWill examine basic implementation of

Four fundamental arithmetic functions

Add

SubtractMultiply

Divide

Several essential logical operations

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Complement

ShiftingExamine alternate implementation methods to improve performance

Speed

Cost

Lets look at each of these

Well begin with basic binary arithmeticWell see that this is no different from what weve been doing

In base 10

Binary Arithmetic Operations

We will begin with binary arithmetic

Using unsigned numbersFor now will work only with integers

Floating point operationsMerely extension of basic ideas

Unsigned Numbers

Unsigned numbers

Considered to be all positive

We began learning decimal arithmeticBy studying operations on single digit

Use same technique for binary

Addition and Subtraction

Addition and subtraction relatively straight forward operations

Executed much as one would expect

Addition

Basic binary addition proceeds as follows

0 0 1 1 augend+0 +1 +0 +1 addend

---- ---- ---- ----

0 1 1 1 1 carry sum

Carries propagate to the left as we have in familiar decimal additionOften name further qualified as carry out

Indicated carry out from one column to nextFurther qualification

Carry outfrom ith

column becomes

Carry into i+1th

columnWe see this in next example

We can extend to multiple bits very easily

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Example

111 11

1001 0111 1011 01011010 1101 0001 1010

------ ------ ------ ------10011 10100 1100 1111

ObserveCarry propagation

Carry out from one column as carry in to next

OverflowIn several cases

We get a carry out from the most significant bit

This is called overflowThe result is too large

To fit in word or register designated to hold it

Here we are working with 4 bit words

We have a 5 bit resultCan potentially be serious problem

If overflow not registered

Result can be interpreted as

Adding two large numbersProducing small result

The Full Adder

We can build a hardware circuitTo implement such an adder

In rather straight forward way

Begin with single bit adder

Calledfull adder

A full adder hasThree inputs

Augend bit

Addend bitCarry in bit

Two outputs

Sum bit

Carry out bit

If we do not have carry in bit

Called half adder

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The full adder block diagram follows

To implement adder in hardware X

Y

Ci

Co

Sum

Full

AdderBegin with truth table

Must consider

Two inputs and carry inSum output and carry out

X Y Ci S Co0 0 0 0 0

0 0 1 1 0

0 1 0 1 00 1 1 0 1

1 0 0 1 0

1 0 1 0 11 1 0 0 1

1 1 1 1 1

Can now write 2 equationsS = !X!YCi + !XY!Ci + X!Y!Ci + XYCi

Co = !XYCi + X!YCi + XY!Ci + XYCi

These reduce to

S = X Y Ci

Co = Ci (X Y)+ XY

Two equations give what we call full adder

InputsX, Y, Ci

Output

S, Co

Ripple Carry Adder

Consider now that we are working with 4 bit words

1011

0110------------

10001

The result of adding these two numbers

Generates carry out of MSBResult is too large to fit into 4 bits

Have produced overflowMust be aware of this

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To compute 4 bit sum in hardware

Can use 4 full adders from aboveWe take the carry out from stage i

Treat as carry in to stage i+1

Thus for 4 bit adder we have

X

Y

Ci

Co

Sum

Full

Adder

X

Y

Ci

Co

Sum

Full

Adder

X

Y

Ci

Co

Sum

Full

Adder

X

Y

Ci

Co

Sum

Full

Adder

If we examine the process of producing the 4 bit sumWe observe that we cannot compute sum in column i+1 until

Carry from column i is available

If we define the carry propagation delay as carrySee that for each additional column

Availability of final sum delayed by carry

For 32 bit word

Total delay 32 * carry

Which can become significant

Advantage

Design is low cost

Simple to implementDisadvantage

SlowLong carry delay pathAsynchronous

Carry Save Adder

Carry save adder is simple and low costLike ripple carry adder basic algorithm

Replicates pencil and paper method

ComponentsSingle full adder

Several shift registers

Control logicBlock diagram given in next diagram

In design

DataLoaded into X and Y registers in parallel

Read from Sum register in parallel

X, Y, and Sum registers n bits long

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Control algorithm

ResetLoad X

Load Y

repeat n times

clock X, Y, Sum registers and D flip-flopend repeat

Read Sum register and Co

Variations

X and Y registers can be

Serially loadedConfigured as circular registers

Sum register read serially

AdvantageDesign is low cost

Simple to implementSynchronous

Carry does not have long ripple path delayDisadvantage

Slow

Carry Look Ahead

To get around carry delay problem

Use technique called carry look ahead

Idea amounts to computing carry at same time as sum

Lets examine the carry out equation from above

Co = Ci (X Y) + XY

Examining equation

Co will be a true under the following conditions

When addend and augend bits are both 1Such a condition generatesa carry

When either bit is 1 and there is a carry inCondition in which either bit is 1 cannot generate a carry

However can combine with incoming carryTopropagatethat carry to next stage

Term XY

Called generateterm G

Term (X Y)

Calledpropagateterm P

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Can rewrite equation as

Co = Ci P+ G

For stage 0 we have

Co0= Ci0(X0Y0) + X0Y0

For stage 1 we have

Co1= Ci1(X1Y1) + X1Y1

= Ci1P1+ G1

Co1= Co0(X1Y1) + X1Y1= Co0P1+ G1

Co1= (Ci0(X0Y0) + X0Y0) (X1Y1) + X1Y1

= (Ci0P0+ G0) P1+ G1

We can continue in the same way for each stage

We can write the equation in much more compact formThus we have general term

Coi= CiiPi+ Gi

orCn= Gn+ Gn-1Pn+ Gn-2Pn-1Pn+..+CinP0P1Pn

As is evident

Building full carry look ahead even for small adderBecomes large very quickly

Doing so not reasonable for large system

Such as 64 bit adder

Rather that full look aheadBuild as hybrid

Implemented as multilevel systemBuild full look ahead across smaller blocks of adders

Ripple carries between such blocks

Design for 64 bit look ahead carry adder

ModulesFour bit adder module

Comprises four full adders

Look ahead carry across four bits

Module illustrated in accompanying diagram

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Four bit look ahead carry generator

Look ahead carry across four bitsModule illustrated in accompanying diagram

Can now implement system as illustrated in following diagram

Table Look Up

Method to perform arithmetic operations very quickly

Simply look up answerOperands provide address into table

Answers precomputed and stored in table

At location indicated by operands

Consider simple case of two bit operands

Concatenated operands form 4 bit numberFour bit number gives 16 combinations

Table entries store 4 bit wordCarry

Two bit sum

Adder Symbol

In best object centered sense

Specific implementation of adder is context dependent

Based upon requirements

From user perspectiveWe draw adder as follows

Number of bits in each input operand and in result output

Given by context

Subtraction

Subtraction operation

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Parallels addition

Basic binary subtraction proceeds as follows

0 0 1 1 minuend

-0 -1 -0 -1 subtrahend

---- ---- ---- ----0 1 1 1 0 borrow difference

Borrows propagate to the left as we have in familiar decimal subtraction

As discussed with additionBorrow has several interpretations

Borrow outfrom ith

column becomes

Borrow into i+1th

column

As we did with the adder

Can extend to multiple bitsExample

111 1 1 1

1001 0111 1011 01011010 1101 0001 1010

------ ------ ------ ------

1111 1010 1010 1011

ObserveBorrow propagation

UnderflowIn several cases

We get a borrow out from the most significant bit

This is called underflowThe result is too small

To fit in word designated to hold it

Here we are working with 4 bit wordsWe have a 5 bit result

Can potentially be serious problem

If underflow not registeredResult can be interpreted as

Subtracting two numbers

Producing result larger than original

Full Subtractor

We can build a hardware circuit

To implement such an adderIn rather straight forward way

Begin with single bit subtractor

Calledfull subtractor

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A full subtractor has

Three inputsMinuend bit

Subtrahend bit

Borrow in bit

Two outputsDifference bit

Borrow out bit

If we do not have borrow in bitX

Y

Bi

Bo

DifferenceFull

SubtractorCalled half subtractor

The full subtractor block diagram accompanies

To implement subtractor in hardware

Must considerTwo inputs and borrow in

Difference output and borrow out

X Y Bi D Bo

0 0 0 0 00 0 1 1 1

0 1 0 1 1

0 1 1 0 11 0 0 1 0

1 0 1 0 01 1 0 0 0

1 1 1 1 1

Can now write 2 equations

D = !X!YBi + !XY!Bi + !XYBi + XYBi

Bo = !X!YBi + !XY!Bi + !XYBi + XYBi

These reduce to

D = X YBiBo = Bi (!X+Y)+ !XY

Two equations give what we call full subtractorInputs

X, Y, Bi

OutputD,Bo

Consider now that we are working with 4 bit words

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0110

1011------------

11011

The result of adding these two numbersGenerates borrow out of MSB

Result is too small to fit into 4 bits

Have produced underflow

Ripple Borrow Subtractor

To compute 4 bit difference in hardware

Can use 4 full subtractors from aboveWe take the borrow out from stage i

Treat as borrow in to stage i+1

Thus for 4 bit subtractor we have

If we examine the process of producing the 4 bit difference

We observe that we cannot compute difference in column i+1 until

Borrow from column i is available

If we define the borrow propagation delay as borrowSee that for each additional column

Availability of final difference delayed by borrowFor 32 bit word

Total delay 32 * borrowWhich can become significant

AdvantageDesign is low cost

Simple to implement

Disadvantage

SlowLong borrow delay path

Asynchronous

Borrow Save Subtactor

Borrow save subtractor is low cost and simple modification of adder

Like ripple borrow subtractor

Basic algorithm replicates pencil and paper method

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Components

Single full subtractorSeveral shift registers

Control logic

Block diagram given in next diagram

In designData

Loaded into X and Y registers in parallelRead from Difference register in parallel

X, Y, and Difference registers n bits long

Control algorithm

Reset

Load X

Load Yrepeat n times

clock X, Y, Difference registers and D flip-flop

end repeatRead Difference register and Bo

VariationsX and Y registers can be

Serially loaded

Configured as circular registersSum register read serially

Advantage

Design is low cost

Simple to implementSynchronous

Carry does not have long ripple path delay

DisadvantageSlow

In doing soWe encounter same borrow prop delay as with 4 bit adder

Can implement look ahead borrow in same way as we did with adder

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Look Ahead Borrow Subtractor

Look ahead borrow subtractor

Mirrors look ahead carry designRarely implemented

Table Look UpTable look up design

Similarly parallels work done for adder design

Opr0

Opr1 Sub

DifferenSubtractor Symbol

Generally subtraction implemented using 2s complementLike adder specific implementation is context dependent

Based upon requirements

From user perspectiveWe draw subtractor as follows

Number of bits in each input operand and in result output

Given by context

Multiplication

Basic binary multiplication proceeds as follows

0 0 1 1 multiplicand

x0 x1 x0 x1 multiplier---- ---- ---- ----

0 0 0 1 product

Observe that binary multiplication operation

Implements AND operation

There are variety of ways to implement multiplication in ALU

Well look at a couple

Shift and Add

Simplest method duplicates pencil and paper approach

Consider following block diagram for 16 bit multiplier

16 Bit Multiplicand

16 Bit Multiplier

32 Bit Product

Operation proceeds as followsAlgorithm

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load multiplier and multiplicand registersclear product registerrepeat n times

if multiplier LSB = 1product registerproduct register + multiplicand

end if

shift product register right 1 bitshift multiplier register right 1 bit

end repeat

Example

Multiply 1101 by 1011

1 1 0 11 0 1 1

0 0 0 0 0 0 0 0 reset product register1 1 0 1 multiply

0 1 1 0 1 0 0 0 0 add

0 1 1 0 1 0 0 0 shift1 1 0 1 multiply

1 0 0 1 1 1 0 0 0 add1 0 0 1 1 1 0 0 shift0 1 0 0 1 1 1 0 shift1 1 0 1 multiply

1 0 0 0 1 1 1 1 0 add1 0 0 0 1 1 1 1 shift

Advantage

Shift and add algorithm simpleEasy to implement

Disadvantage

Slow

Wallace Tree

Utilizes fact basic arithmeticCombinational logic problem

Multiplication repeated add operation

Bit multiplication binary AND operation

Wallace treeBuilds multilevel combinational logic array

Level 0Builds partial product array

Implemented as array of AND operations

Shifting inherent in array interconnectionsLevel 1..N

Implemented as N levels of arrays of full addersFull adders viewed as

Three input two output adders

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Input

3 binary bits carry in used as one of bitsOutput

Sum and carry out

Successive levels reduce partial product array

Until two integer numbers remainLevel N+1

Two integer numbers produced from partial product array

Added in parallel to give final product

Example

Build Wallace tree 4 x 4 multiplier

Both multiplier and multiplicand have 4 bits

In diagramBit values not relevant

Indicate by

Partial product arrayBuilt as array of 2 input AND gates

Each gate ANDs

One bit from multiplicandOne bit from multiplier

AND gate outputs

Connected to full or half adder inputsIn first full adder array

Followed by succession of levels of full adder arrays

Partial product array will have N rowsN is number of bits in multiplier or multiplicand

Full adder arrays

First full adder arrayImplemented on partial product array

Within each full adder array

Each full or half adder in column i producesSum bit into column i

Carry bit into column i+1

In next full adder array

Each successive full adder array levelReduces array size until two rows remain

Final product produced by adding final two rows

Table Lookup

Multiplication can benefit significantly

From table lookup approach

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As with addition and subtraction

Operands provide address intoTable of precomputed results

For multiplication intensive applications

Fast Fourier Transforms for example

Speed improvement can be significant

Multiplier can be implemented as

Single large tableFor 32 bit operands can be rather large

Alternately

Can divide multiplier into4 bytes or 8 nibbles

Look up 4 or 8 partial products

Perform high-speed addition operationsTo combine individual pieces

Division

Lets looks at several alternative methods for implementing divisionBoth are variations on the pencil and paper methods

Restoring

To examine the first method

Lets work with the following block diagram

Register initially holding dividend

Double length

Ultimately will holdRemainder

Quotient

Identified as RQ register

Operation proceeds as follows

Algorithmdivisor register divisor // right alignedRQ register dividend // right aligned

repeat n times

shift RQ left 1 bit positionRR divisorif R negative

q00RR + divisor // restore

elseq0 1

end ifend repeat

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if R negativeRR + divisor

end if

dividend upper contains remainderdividend lower contains quotient

Example

0000 1000 dividend upper, lower

0001 0000 shift left

0011 divisor

------1110 0000 negative - restore

0011

------0001 0000 q0= 0, shift left

0010 0000 subtract

0011------

1111 0000 negative - restore

0011------

0010 0000 q0= 0, shift left

0100 0000 subtract

0011

------ positive

0001 0001 q0= 1, shift left

0010 0010

0010 0010 remainder 2, quotient 2

Non Restoring

Second method

Uses same block diagram

Register initially holding dividend

Double length

Ultimately will holdRemainder

Quotient

Identified as RQ register

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Operation proceeds as follows

Algorithmdivisor register divisor // right alignedRQ register dividend // right aligned

repeat n times

shift RQ left 1 bit position

if R positiveRR divisor

else if R negativeRR + divisor

end if

if R positiveq0 1

else if R negativeq00

end if

end repeat

if R negativeRR + divisor

end if

dividend upper contains remainderdividend lower contains quotient

Example

0000 1000 dividend upper, lower

0001 0000 q0= 0, shift left0011 divisor

------

1110 0000 negative - add next time

1100 0000 q0= 0, shift left

1100 0000 add

0011

------1111 0000 negative - add next time

1110 0000 q0= 0, shift left

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1110 0000 add

0011------

0001 0000 positive - subtract next time

0001 0001 q0= 1, shift left

0010 0010 subtract

0011

------1111 0010 negative restore remainder

q0= 0

1111 0010 restore remainder

0011

------0010 0010

0010 0010 remainder 2, quotient 2

Signed Numbers

Up to this point

Been working with operations on unsigned fixed point numbersSigned numbers

Permit both positive and negative numbers

Variety of different methods for representing such numbersWe will examine 3

Sign and Magnitude

1s complement2s complement

Sign and Magnitude

As name suggests

Number comprised of

Sign partUsually the MSB

0 - positive

1 - negative

Magnitude part max = 2n-1

min = 0

max = 2n-1

- 1

+/- 0

min = -2n-1

+ 1

Remaining bitsObserve with such scheme

One bit devoted to signReduces

Expressive power by one----why

Maximum and minimum values2

n-1+1 to 2

n-1- 1

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1s Complement

Formally 1s complement of number computed as

2n-N - 1

n is the number of bits in the numberEasiest way is to simply invert all the bits

1s complement reducesExpressive power by one----why

Maximum and minimum values

- 2n-1

+ 1 to 2n-1

- 1Example

1011

24-1011 - 0001

10000

- 01011

-------00101

- 00001-------

00100

Inverting

1011 0100

2s Complement

Formally 2s complement of number computed as

2n

-Nn is the number of bits in the number

Easiest way is to simply invert all the bits and add 1

Does not affectExpressive power ----why

Maximum and minimum values

- 2n-1

to 2n-1

- 1

Example

10112

4-1011

10000

- 01011-------

00101

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Inverting

1011 0100

Adding 10100 + 1 = 0101

Observe2s complement of a number is the original number

Proof

Select an arbitrary number NLet the 2s complement of N be given by N1

Thus N1 = 2n-N

Compute the 2s complement of N1

2

n

-N1 = 2

n

- (2

n

-N) = N

Addition and Subtraction Using Signed Numbers

We perform addition and subtraction using signed numbers

By performing addition of the numbers

Either as positive numbersExpressed in complementary form

Observe

N1 - N2 can be converted to N1 + (-N2)-N2 expressed in either

1s or 2s complement form

Lets develop a generalized notion of such arithmeticFirst stepAll negative numbers expressed in complemented form

Dont need to worry about sign bit

Must consider 2 cases

Numbers

Same signOpposite signs

Only need to worry about addition at this point---why

Same SignAgain two cases

Both positiveBoth negative

Both Positive

Simply add numbers

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Sum = N1 + N2

Example

+13 00001101

+ 9 00001001

----- ------------+22 00010110

ObservePossibility of overflow exists must be handled

Both Negative

Simply add complemented numbers

Sum = N1c+ N2c

= (2n-N1) + (2

n-N2)

= 2n- (N1 + N2) + 2

n

ObserveThe result is in 2s complement formThe trailing 2

nis ignored

Possibility of underflow exists must be handled

Example

-13 11110011- 9 + 11110111----- ------------

-22 111101010

^ ignore

2s complement of 11101010 00010110

Opposite Signs

Note

We cannot have overflow or underflow

Again two cases1. N1 0 N2 < 0

2. N2 0 N1 < 0

Observe

Case 1.

If | N1 | |N2|Result must be positive

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Sum = N1 + N2c

= N1 + (2n-N2)

= (N1 - N2) + 2n

Ignore the last carry out

If | N2 | > | N1|

Result must be negative

Sum = N1 + N2c

= N1 + (2n-N2)

= 2n+ (N1 - N2)

= 2n- (N2 - N1)

Example

13 00001101- 9 + 11110111

----- ------------

4 100000100^ ignore

Example

9 00001001

- 13 + 11110011

----- ------------- 4 11111100

Case 2.If | N2 | | N1|

Result must be positive

Sum = N1c+ N2

= 2n-N1 + N2

= (N2 N1) + 2n

Ignore the last carry out

If | N1 | > | N2 |

Result must be negative

Sum = N1c+ N2

= 2n- N1 + N2

= 2n- (N1 N2)

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Example

- 9 1111011113 + 00001101

----- ------------

4 100000100^ ignore

Example

- 13 11110011

9 + 00001001

----- ------------- 4 11111100

Sign Extension

When working with signed numbers

Express positive numbers in natural formMSB is sign bit value 0

Indicating positive

Express negative numbers in 2s complement formMSB is sign bit value 1

Indicating negative

Will find occasions when must work with numeric values

With number of bits less than full word size

Require such operations in two common casesShort jumps in branching or looping operations

Must jump forwards or backwards by few instruction addressesTypically implemented by

Adding (algebraically) value to PCWorking with immediate mode constants as part of instruction

Arithmetic with such shortened values proves interestingWhen must put shortened value into full word

Where do missing most significant bits come from

Consider 2 cases of adding 8 bit quantity to 16 bit word

1001 0011 1010 0110 + 0110 1110

1001 0011 1010 0110 + 1110 1110

When second operand placed into register

What goes into upper 8 bitsIn first case

Can simply fill with 0s

Following operation resulting sum will be correct

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In second case

Since MSB is 1 number is negative 2s complementFilling with 0s will not give correct answer

Now want upper 8 bits to be 1s

To preserve 2s complement

We see then to ensure correct resultsPositive number must be filled with 0s

Negative (2s complement) number must be filled with 1s

In reality such operations called sign extensionExtending sign bit to fill MSB positions

Logical Operations

In addition to arithmetic operations

ALU must be able to perform various logical type operations

Operations includeLogic

AND, OR, XOR, complementShifting

Left, rightCircular (rotate), arithmetic, logical

Comparison

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Logical right shift by 1 bit

Arithmeticshift

Also known as signed shiftSimilar to logical shift

One simple difference

All bits in registerShifted left or right

Right shifts

MSB continually entered into register on leftCalled sign extension

For signed operands

Left shift0s entered into register on right

Arithmetic shifts illustrated in next diagram

Arithmetic right shift by 1 bitSame as logical shift left

Logical right shift by 1 bit

CircularshiftCircular shifts appear in cryptographic

applications

Used to permute bit sequencesSimilar to logical and arithmetic shift

One simple difference

All bits in register

Shifted left or rightRight shifts

LSB continually entered into register on left

Left shiftMSB entered into register on right

Circular shifts illustrated in next diagramCircular right shift by 1 bit

Circular left shift by 1 bit

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Comparison

Device will accept two N bit binary numbers

Depending upon design

Will produce

Single output

Indicating that two input numbers are equalHigh level diagram given in accompanying figure

Two outputs

N1 is larger than N2N2 is larger than N1

If both are true

Numbers are equal

Three outputs

N1 is larger than N2

N2 is larger than N1

N1 is equal to N2

More complex designs

N1

N2

EqualO

GreaterO

LessO

EqualI

GreaterI

LessI

Include inputs signalingLess than

Greater than

EqualUsing such inputs

Can cascade series of comparators

To compare two M digit numbersHigh level diagram given in accompanying figure

Summary

Have introduced studied and developed

Number of fundamental algorithms for

Performing basic arithmetic and logical computations

Such computations are building block commonly found

In most ALU

Documents

Arithmetic 0