RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

EFFECTS OF MICROWAVESRobust Computer Architectures

Prof. Bruce Jacob

Electrical & Computer EngineeringUniversity of Maryland, College Park

UNIVERSITY OF MARYLAND

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RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

System Modeling

WHEN systems fail, HOW do they fail?

We use this informationto develop & test reliable architectures

SIMULATOR

BehavioralResultsRE-THINK

HDL Modelof Chip

Results ofPhysical

Experiments& DeviceModeling

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Tasks (Talk Outline)

ACCOMPLISHED

•

Verilog models of two bootable microprocessors (simple/advanced)

•

Initial work on robust architectures(reliability studies, draft floorplan)

IN PROGRESS

•

Verilog model of microprocessor with hardware checkpoint/repair

FUTURE WORK

•

Fabricate and test physical designs

•

Enhanced Verilog and SPICE software

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Processor Model: simple

Single-Issue, In-Order, Five-Stage Pipeline

REGISTER FILE

SRC1SRC2

TGT

Program Counter

TLB &I-CACHE

OP rA PC

Sign-Ext-7SRC1

TGT

SRC2

PCOP rT OPERAND2 OPERAND1s2s1

rT STORE DATAOP

+1

TLB &D-CACHE

ADDRDATA IN

RF WRITE DATArT

DATA OUT

FETCHSTAGE

DECODESTAGE

EXECUTESTAGE

MEMORYSTAGE

WRITEBACKSTAGE

RF WRITE DATArT

Left-Shift-6

SRC2 SRC1

ALU OUTPUT

OPERAND0

PC

+1

ADD

PC

EXC

EXC

EXC

EXC

rCrB

s2s1

ALU &SHIFT

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Processor Model: simple

Single-Issue, In-Order, Five-Stage Pipeline

16-bit processor coreHandles interrupts precisely

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Processor Model: advanced

High-Performance Out-of-Order Core

Instruction N+1 Instruction N

FETCH BUFFERS

RESULT BUSES

OPERAND 1OPID

INSTR QUEUE

ISSUE BUS

ENQUEUEBUS

DATAMEMORY

OPIDOPERAND 2OPERAND 1OPID OPERAND 2 ADDRESS DATA

COMMIT

COMMITBUS

— —

REGISTERFILE

ALU0BUS

ALU1BUS

MEMORYBUS

EXECUTEPHASE

ISSUEPHASE

ENQUEUEPHASE

FETCHPHASE

OPID ADDRESS DATA

OPID ADDRESS DATA

IQ0 IQ1 Instruction N+2 IQ7IQ2 . . .

INSTRUCTIONMEMORY

BUS

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Processor Model: advanced

PowerPC ISA with AltiVec SIMD Unit

Design & layout of core in progress (AltiVec multiplier above)

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Robust Architectures

INITIAL STUDY: Assume the Worst Case

Checkpoint/Repair ...

CHECKPOINT:

Periodically save KNOWN-GOOD STATE

In case of FAULT, REPAIR to last saved state

TIME

State i-2 State i-1 State i

FAULTDETECT

Resume Executionfrom STATE i

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Robust Architectures

INITIAL STUDY: Assume the Worst Case

Implementation can be single- or multi-chip

. . .. . .

REPAIR

CHECKPOINT

Sensor/Detector

Busses protected viaECC encoding

Small shielded areaLarge transistors

72 x (32+ECC) bits

GPRs/FPRsCtrl Regs

PC

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Robust Architectures

0 1 2 4 8 16 32 640.00

0.25

0.50

0.75

1.0

Portion of die unaffected

Successrate

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Robust Architectures

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Robust Architectures

Initial Floorplan (simple CPU + safestore)

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Globally Asynchronous

ASSUMPTION: Clock Net is Weak Point

Processing elements generate local clocksSynchronize at inter-node communication

MEMORY MEMORY

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RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Future Work

Synthesize, Fabricate, Test Canonical Forms

•

Clock trees

•

Busses (w/ and w/o ECC)

•

Memories (w/ and w/o ECC)

•

Arithmetic/Logic Units

Incorporate Drift-Diffusion into CAD tools(more accurate SPICE/Verilog modeling)

RELIABLECOMPUTER

ARCHITECTURES

MURI Review

June 8, 2002

Bruce Jacob

University of

Maryland

Participants

Profs. Bruce Jacob & Neil Goldsman, UMCP

A host of grad students:

•

Azadeh Davoodi, Cagdas Dirik, Amol Gole, Samuel Rodriguez, Ohm Tuaycharoen (Architecture)

•

Akin Akturk, Zeynep Dilli, Tejas Chitnis (Microelectronics)

UNIVERSITY OF MARYLAND