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Engling Yeo University of California,
Berkeley 1
Architectures and Implementations of
Low-Density Parity Check
Decoding Algorithms
Engling Yeo, Borivoje Nikolić, and Venkat Anantharam
Department of Electrical Engineering and Computer SciencesUniversity of California, Berkeley, CA 94720, USA
Engling Yeo University of California,
Berkeley 2
0 1 2 3 4 5 6
10-4
10-3
10-2
10-1
100
SNRB
ER
SNR vs. BER for rate 1/2 codes
IterativeCode
Conv. Code ML decoding
Uncoded
CapacityBound
Background: Iterative Codes
C. Berrou and A. Glavieux, "Near Optimum Error Correcting Coding And Decoding: Turbo-Codes," IEEE Trans. Comms., Vol.44, No.10, Oct 1996.
S. Chung; G.D. Forney, T.J. Richardson, and R. Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, vol.5, (no.2), IEEE, Feb. 2001. pp.58-60.
Year Rate ½ Code SNR Required for BER < 10-5
1948 SHANNON 0dB
1967 (255,123) BCH 5.4dB
1977 Convolutional Code 4.5dB
1993 Iterative Turbo Code 0.7dB
2001 Iterative LDPC Code 0.0045dB4
dB
Engling Yeo University of California,
Berkeley 3
Outline
LDPC Codes Soft Decoding of LDPC Codes Parallel vs. Serial Architectures Platforms Methods for Code Construction
Engling Yeo University of California,
Berkeley 4
Low Density Parity Check Codes (LDPC)
• LDPC representation by bi-partite graph.
• Decoding by message computation and relay along edges
• Iteratively improved estimates of log-likelihood ratios
• Example code:
- R. G. Gallager, IRE Trans. Info. Theory, Vol. 8(1962) p. 21
4096 information bits 4608 variable nodes , 512 check
nodes512 parity bits
CHECK NODES
VARIABLE NODES
)0(
)1(ln
n
n
p
p
Engling Yeo University of California,
Berkeley 5
Outline
LDPC Codes Soft Decoding of LDPC Codes Parallel vs. Serial Architectures Platforms Methods for Code Construction
Engling Yeo University of California,
Berkeley 6
Qnm
Message from Variable n to Check m
R1n
R2n
R 3n
1 2 3m
n
CHECK NODES
VARIABLE NODE
mnnm
nmn
nnm RR
p
pQ
)('')0(
)1(ln
)0(
)1(ln
n
n
p
pDecoder input:
Engling Yeo University of California,
Berkeley 7
n1 2 3
Message from Check m to Variable n
0);()2
1tanh(log)( 1
xxxx
Q 1m
Q 2m
Q3m
mR
nm
CHECK NODE
VARIABLE NODE
)sgn(sgn ')(')('
'1
mnmn
nmnmmNn
mnmn QQQQR
• Signed magnitude representation
• MSB represents parity information
Engling Yeo University of California,
Berkeley 8
Hardware for Computation of Rmn
b : Wordlength of messages
Engling Yeo University of California,
Berkeley 9
Outline
LDPC Codes Soft Decoding of LDPC Codes Parallel vs. Serial Architectures Platforms Methods for Code Construction
Engling Yeo University of California,
Berkeley 10
Parallel Architecture of LDPC decoders
Throughput Efficiency
Power Efficiency Complex
Interconnect
A. Blanksby and C. J. Howland, “A 220mW 1-Gbit/s 1024-Bit Rate-1/2 Low Density Parity Check Code Decoder,” Proc IEEE CICC, Las Vegas, NV, USA, pp. 293-6, May 2001.
PEVC,1
SoftInput1
SoftOutput1
...
PECV,1
PEVC,2 PEVC,3 PEVC,4
PECV,2 PECV,M...
PEVC,N
SoftInput2
SoftOutput2
SoftInput3
SoftOutput3
SoftInput4
SoftOutput4
SoftOutputN-1
SoftInputN
SoftOutputN
SoftInputN-1
PEVC,N-1
PECVCheck-to-Variable
Processing Element
PEVCVariable-to-Check
Processing Element
Engling Yeo University of California,
Berkeley 11
Serial Architecture of LDPC decoders
High logic density Memory requirement grows linearly with number of
edges G. Al-Rawi, J. Cioffi, and M. Horowitz, “Optimizing the mapping of low-density parity check codes on parallel decoding architectures,” Proc. IEEE ITCC, Las Vegas, NV, USA, pp.578-86, Apr 2001.
Processing Element for BothClasses of MessageComputation
PE
Memory
SoftInputs
CrossbarSwitch
SoftOutputs.
.
.
.
.
.
Memory
Memory
PE
PE
PE
Engling Yeo University of California,
Berkeley 12
Outline
LDPC Codes Soft Decoding of LDPC Codes Parallel vs. Serial Architectures Platforms Methods for Code Construction
Engling Yeo University of California,
Berkeley 13
Decoding with Software Approach
General purpose microprocessors and Digital Signal Processors (DSP)
Limited number of Processing Elements (ALUs) Serial Architecture Few hundreds of kbps throughput Design, simulate, and perform comparative analysis of LDPC
codes Low throughput applications with fast time to market
element
Engling Yeo University of California,
Berkeley 14
Decoding with Hardware Approach
Parallel architecture Power and throughput efficiency
FPGA Parallel adders and table lookups Need to fit PEs and routing onto single
FPGA die Existing implementations with serial
architecture limited to 56Mbps throughput
[M. M. Mansour and N. R. Shanbhag, “Memory-efficient turbo decoder architectures for LDPC codes,” Proc. IEEE SIPS 2002, San Diego, CA, Oct. 2002.]
[T. Zhang and Keshab Parhi, “A 56Mbps (3,6)-Regular FPGA LDPC Decoder,” Proc. IEEE SIPS 2002, San Diego, CA, Oct. 2002.]
Engling Yeo University of California,
Berkeley 15
Decoding with Hardware Approach
Custom ASIC Parallel implementation demonstrated with
1Gbps throughput[A.J. Blanksby and C.J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol.37, (no.3), (Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, San Diego, CA, USA, 6-9 May 2001.) IEEE, March 2002. p.404-12. ]
Routing congestion Logic density is 50% Design not scalable to codes with larger
block sizes
Engling Yeo University of California,
Berkeley 16
Solving Routing Congestion in Hardware
Serial architecture with groups of parallel optimized processing elements
Full utilization of pipelined hardware with alternating blocks E.g. 128x parallelism in commercial IP (FlarionTM) Further memory reduction through staggered decoding
schedule[E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "High throughput low-density parity-check architectures," Proc. IEEE Globecom2001, San Antonio, TX, pp.3019-24, Nov 2001. ]
Bank ofMemories
Variable-to-Check PEs
CrossbarSwitch
SoftInputs
Bank ofMemories
Check-to-Variable PEs
SoftOutputs
Engling Yeo University of California,
Berkeley 17
Platform vs. Throughput Summary
103 104 105 106 107 108 109
Engling Yeo University of California,
Berkeley 18
Outline
LDPC Codes Soft Decoding of LDPC Codes Parallel vs. Serial Architectures Platforms Methods for Code Construction
Engling Yeo University of California,
Berkeley 19
Density Evolution
Density Evolution Very good codes (< 0.0045dB from theoretical
bound)
Large variable edge degree (~ 100)
Large block size (107)
Cayley and Ramanujan Graphs Unstructured interconnects
Algebraic Constructions Cyclic or quasi-cyclic properties
Use of shift registers
Parallel implementation has to address sparse code / interconnect issue.
Engling Yeo University of California,
Berkeley 20
Summary
Difficulties with routing or memory requirement
Parallel architectures are optimal for power/ throughput efficiency
Different platforms (microprocessor/FPGA/ASIC) offers possibilities for various applications
Methods for code construction need to consider implementability
Engling Yeo University of California,
Berkeley 21
END
Engling Yeo University of California,
Berkeley 22
Engling Yeo University of California,
Berkeley 23
Low Density Parity Check Codes (LDPC)
• LDPC representation by bi-partite graph.
• Non-zero entries in each
• Row m represent the set of bits that are connected to check m, (m) = {n: Hm,n = 1}
• Column n represent the set of checks that are connected to bit n. (n) = {m: Hm,n = 1} is
Engling Yeo University of California,
Berkeley 24
Sparse Graph
Limited spatial locality between input edges
Rearrangement of nodes has limited effect in improving spatial locality
Engling Yeo University of California,
Berkeley 25
...
PEVC,1PECV,1
PEVC,2
PEVC,3
PEVC,4
Memory
PECV,2
PECV,3
PECV,4
Memory...
Memory
...
LDPC Decoding Algorithms
Pipeline stall delays
Throughput hardly increased
Limited spatial locality
• Sparse graph
Hardware Pipelining of serial architecture
STA
LL!!
Traditional DSP Algorithms
• e.g. FFT, Digital Filters
Throughput increases
High spatial locality
...
ButterflyUnit
Memory
Memory...
Memory
...
ButterflyUnit
ButterflyUnit
ButterflyUnit
...
ButterflyUnit
ButterflyUnit
ButterflyUnit
ButterflyUnit