Architecture, IC Design & Embedded Software · •Platforms and extensive patent portfolio •Key Enabling Technologies as innovation driver •World-class knowledge and methods •Confidentiality

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DACLE Division 2013 © CEA. All rights reserved | 2 & V1,0

CEA: from Research to Industry

» 16 000 employees

» 10 research centers

» 4 regional extensions

» Budget of 4.3 billion €

» 650 patents/year

» 4000 publications/year

» 50 Joint Research Laboratory

» 150 startup creations in 30 years

Direction

Tech

no

log

y

Sci

en

ce

Defense

Security

Military

Applications

Division

Nuclear

Energy

Nuclear

Energy

Division

Key Enabling

Technologies

Fundamental research

Materials Sciences Division

Life Sciences Division

Gramat Cesta

Le Ripault Valduc

DAM- IdF

Paris

Saclay Fontenay-aux-Roses

Grenoble

Marcoule Cadarache

Bordeaux

Nantes

Toulouse

Gardanne


DACLE Division 2013 © CEA. All rights reserved | 3 & V1,0 3

Market Knowloedge

Pump Priming

25%

(5-10 ans)

Technology Transfer

75%

(1-3 ans)

CEA Tech: bringing competitiveness to our customers

3



CEA Tech: unique technology platforms over Europe

4


DACLE Division 2013 © CEA. All rights reserved | 5 & V1,0 5 Example: nanoelectronics

CEA Tech: KETs for a broad range of industries

5



From an application to an embedded system

Algo/Archi matching Architecture design Silicon integration

Embedded System

Platform Design

Platform Test

Platform

Mo

del

s

Emu

lati

on

IP

The Valley of Death

C++ IC

Advanced technologies & HW/SW expertise Reusable building blocks

Turned toward market’s system needs

Evaluate usage scenario at system level Offer an adapted technology Progress on Technology Readiness Level (TRL)

Our approach



Integrated Components

Technologies & Tests

Embedded Systems

Applications

Integrated Systems Platforms

Emulation, Simulation Hard/Soft Integration

NanoInnov

Minatec

Components & IC Design

System in Package Miniaturization



Embedded System Platform

Equipment & Human Resources Emulation Tools

Eve-Synopsis Zebu : 5M ports capacity

Mentor Veloce2 : 200M gates multicore emulator

Simulation Tools (SESAM, ArchC)

40 permanent researchers

Methodologies System exploration

Architecture exploration and design

Electronic System prototyping

Embedded application exploration

Hardware/Software coherence

Middleware development

Embedded System fault tolerance, reliability & security

Veloce2 Emulator



COTS ANALYSIS



Programming single vs multi-core architectures

Single-core programming “Democratic” programming Fairly good abstraction Fairly good performance

Multi-core programming Expert programming Dedicated language No performance portability

(yet)

C C++ fortran Java

compilation

ARM powerPC Intel

OpenCL CUDA

Compilations

...

Nvidia AMD

MPI

Archi //

#1

Archi //

#2

…

HMPP OpenMP



Benchmarking of Parallel Architectures

Working on COTS parallel architecture benchmarking

To improve benchmarking objectivity To improve productivity when performing parallel ports on embedded systems

On-going and future research ARM-based systems benchmarking and dimensioning methodology and rules Benchmarks suites for I/Os intensive applications

Sp

ee

du

p

Parallelisation degree

Empirical

Knowledge

Database

Apps

Semi-auto statistical

methodology

Kernel/hotpoints Extraction

Best choices: - Architectures - Parallelization methods

1,E+5

1,E+6

1,E+7

1 4 8 16 36

1e3

Cyc

les

/ fr

ame

s

arm

i7

tilera

P2012

Degré de parallélisation Hig

he

r is

be

tte

r

Tem

ps

d’e

xécu

tio

n

Effi

caci

téé

ne

rgét

iqu

e

0

0,2

0,4

0,6

1 4 8 16 36

Fram

es/J

ou

le arm

i7

tilera

P2012

Lo

we

r is

be

tte

r

(estim.)

COTS platform



Example conclusions

Parallel programming and parallel architectures Push programming complexity way beyond

sequential programming Re-introduces a lot of human intervention in

design flows Harms the average-developer as much as the

expert-one

New methodology introduced, combining empirical experimentations with analytic analysis to allow fast architecture benchmarking and parallelization model analysis

Results demonstrate small deviation (<10%) between prediction and measures Impact of programming style (50% performance) Impact if code optimization (8 factor between naïve and

optimized implementations)

0

20

40

60

80

100

120

1 4 8 16 36

mJ

Energy spent for pedestrian detection

arm

i7

tilera

P2012



MODELING



SESAM

Processor modeling and integration

• Functional or CA ISS

• ArchC 2.0, GenIssLib, OVP…

• Mips32, STXP70, Sparcv8…

• NXP BSP CoolFlux… MPSoC

Modeling

High-level modeling

• SystemC C/C++

• AT TLM

Cosimulation

• VHDL / Verilog

Architecture & SW

Exploration

• Parameter files

• +250 parameters

• +300 statistics

• Reliability, power…

MPSoC

Simulation

• Asymetric multiprocessors

•Up to 1-10 MIPS (8 PE)

• +90% of accuracy

• NFS server

• Automatic spreadsheet



SW & HW prototypes comparison

Maximum error deviation between SW & HW prototypes

+/- 7%

Acceleration of simulation speed

x250

0

50

100

150

200

250

300

1

10

100

1000

Functional RTL Post-synthesis RTL on EVE

SESAM

Too

l acc

ele

rati

on

Re

al e

xecu

tio

n t

ime

(h

ou

rs)



EXPLORATION VIRTUAL PROTOTYPING



Highlights

Example : a 3D-Vision driver assistance system

Architecture sizing, design and diffusion taking into account Performance, Thermal, Power and HW/SW configuration.

An end-to-end HW/SW development

Rapid Architecture sizing in SESAM Environment :

Components on the Shelf (COTS) evaluation, based on performances, cost… and applications

High level system modeling & simulation

Thermal/Power effects are analyzed with DOCEA and ATRENTA frameworks

Hardware dependent Software is configured and customized for application with MAGILLEM Tools

FPGA DSP ARM

FM_LCE_LISAN-LC-DOCEA-DAC-demo.ogv



Optimization process

High performance and flexible computing board for applications of real time and actual embedded geolocalization applications

Design of a Multi-CPU, Multi-FPGAs board

X86 Host CPU SW

34/ 1512ms

POI extractor Descriptor Match Pose

Local Bundle Adjustment

or 3D recons.

RT-SW & HW

Dedicated HW acceleration: >10

SIMD, MT and Multi-frame Parallelism

55ms 25ms 48ms 5ms

<15ms

2ms 15 ms

<167ms

Pure SW execution

Parallel Board

execution Embedded CPU

HW accelerators



OS PharOS PsyC,

Chaine de Compilation

Modèles d’architecture (ex Boléro, Leopard)

Norme et Standards (DO168, AUTOSAR)

Validation et Intégration des OS temps réel

Dimensionnement d’architectures

Simulation

Emulation Evaluation de performances

Environnement de prototypage virtuel

DiagnoBoard DiagnoChip GMR A

uto

mo

bile

Aé

ron

auti

qu

e

Ferr

ovi

aire

Conception des systèmes embarqués et de circuits intégrés

Puissance de calcul X2 à même surface

Localisation 8X plus précise et 30x plus rapide que la puce

Livewire

Développement OS sur Architecture virtualisée

Applicati

on

APPLICATIONS



Fundamental research

A Business Model …

… Bridging the gap to transfer IP & know-how…

Applied Research

Pilot line

Mass production

4P

… To the industry



End-to-end Embedded System Design Partner

+ +

Full control Design flow

+ Front-End Back-end

Architectures Logic Synthesis Functional modeling Electrical modeling

Circuit Simulations Placement/routing

Verification Post-Layout

Overcome skills partitioning, a condition for innovation

A single partner along product maturation

Emulation Characterization & test

Functional Validation

Modeling

HW/SW Co-design

Bench labs

Industrial test on pre-series



A CUSTOMIZED offer

A COMPETITIVE and INNOVATIVE offer

A UNIQUE offer

A PROTECTED offer

A MULTI-INDUSTRY offer

• Personal service at every stage of your innovation project

• Customized collaboration (contract, industrial transfer, local support)

CEA-Tech Offer for our customers ’ competitiveness

• Platforms and extensive patent portfolio

• Key Enabling Technologies as innovation driver

• World-class knowledge and methods

• Confidentiality and data protection

• For all industries: from traditional to high-tech

22

Centre de Grenoble 17 rue des Martyrs

38054 Grenoble Cedex

Centre de Saclay Nano-Innov PC 172

91191 Gif sur Yvette Cedex

All inquiries [email protected]

Documents

Architecture, IC Design & Embedded Software · •Platforms and extensive patent portfolio •Key Enabling Technologies as innovation driver •World-class knowledge and methods •Confidentiality