Architectural and Physical Design Optimization for Efficient Intra-Tile Communication Liza Rodriguez Aurelio Morales EEL 6935 - Embedded Systems Dept

Architectural and Physical Design Optimization for Efficient Intra-Tile Communication

Liza RodriguezAurelio Morales

EEL 6935 - Embedded SystemsDept. of Electrical and Computer

EngineeringUniversity of Florida

By: A. Papanikolaou, F. Starzer, M. Miranda, K. de Bosschere, F. Catthoor

EEL 6935 Architectural and Physical Design Optimizations for Efficient Intra-Tile Communications 2 of 32

OutlineOutline

• IntroductionIntroduction• Related WorkRelated Work• Intra-Tile Segmented BusesIntra-Tile Segmented Buses• System Architecture Case StudySystem Architecture Case Study• ResultsResults• ConclusionsConclusions


OutlineOutline



• Inter-Tile Architectures• Take care of communication between tiles• Significant latency can be tolerated.

• Intra-Tile Architectures• Provide means for transferring data between

components of the same tile (Mems, PEs).• Communication Bandwidth is large (Gbps).• Low latency (1 or 2 cycles).• Energy per transfer should be very low.

Communication Architectures in SoCCommunication Architectures in SoC

IntroductionIntroduction



Inter-Tile and Intra-Tile Communication in a SoC


System On-Chip Communication ArchitecturesSystem On-Chip Communication Architectures

Buses are the simplest and most widely used SoC interconnection networks.

Bus:a collection of signals (wires) to which one or more IP components

are connected.

Only one IP component can transfer data on the shared bus at any given time.

Micro-controller

DigitalSignalProcessor

Input/OutputDevice

Memory

Bus

BusesBuses


BusBus TerminologyTerminology

© 2008 Sudeep Pasricha & Nikil Dutt

Master (or Initiator) IP component that

initiates a read or write data transfer

Slave (or Target) IP component that

does not initiate transfers and only responds to incoming transfer requests

Arbiter Controls access to the

shared bus Uses arbitration

scheme to select master to grant access to bus

Decoder Determines the target

for any transfer initiated by a master

Bridge Connects two busses Acts as slave on one

side and master on the other


Bus signal linesBus signal lines

A bus typically consists of three types of signal lines◦ Address

Carry address of destination for which transfer is initiated Can be shared or separate for read, write data

◦ Data Carry information between source and destination components Can be shared or separate for read, write data

◦ Control Requests and acknowledgements Specify more information about type of data transfer

Byte enable, burst enable

address lines

data lines

control lines


Types of Bus TopologiesTypes of Bus Topologies

• Shared bus



• Hierarchical shared bus


Improves system throughput

Multiple ongoing transfers on different buses



• Split bus


Reduces impact of capacitance across two segments

Reduces contention and energy



• Full crossbar/matrix bus (point to point)


Other TopologiesOther Topologies


Bus Physical StructureBus Physical Structure

• tri-state buffer based bidirectional signals

• Commonly used in off-chip/backplane buses▫ + take up fewer wires, smaller area footprint▫ - higher power consumption, higher delay, hard to debug



• MUX based signals


Separate read, write channels

Bus Physical StructureBus Physical Structure



MotivationMotivation

• Communication is one of most critical aspect affecting system performance in current SoC.

• Communication architecture consumes up to 50% of total on-chip power.

• Ever increasing number of wires, repeaters, bus components (arbiters, bridges, decoders etc.) increases system cost.

• Communication architecture design, customization, exploration, verification and implementation takes big part of the design cycle.



ProposalProposal

• Design of a scalable and energy-efficient programmable communication architecture for SoCs.

• Application domain specific SoC, with a software-controlled implementation of segmented buses for intra-tile communication for energy savings and delay/latency gains.


AgendaAgenda



• Past and current research have been focused on communication between SoC tiles.

• Use of standards:• AMBA Bus (ARM) [3]

• CoreConnect (IBM)[4]

• STBus (ST Microelectronics)[5]

• WISHBONE (Opencores.org)[6]

• Academic Contributions:• NoC[7][8]

• Self-Timed segmented buses[9]

• Previous work on segmented buses focused on architecture optimization, ignoring physical aspects.

Related WorkRelated Work


AMBA (AMBA (AAdvanced dvanced MMicrocontroller icrocontroller BBus us AArchitecture)rchitecture)


• PLB (PLB (PProcessor rocessor LLocal ocal BBus)us)• Pipelined• Burst modes• Split transactions• Multiple masters

• OPB (OPB (OOn-chip n-chip PPeripheral eripheral BBus)us)• Low bandwidth• Burst mode• Multiple Masters

• DCR (DCR (DDevice evice CControl ontrol RRegister)egister)• Low throughput• 1 r/w = 2 cycles• Ring type data bus

IBM CoreConnectIBM CoreConnect


AgendaAgenda



Architecture of Segmented Buses Architecture of Segmented Buses Communication NetworkCommunication Network

• Communication between PEs and local memories involves large BW.

• Latency should be minimal to reduce stall cycles.

• To meet requirements of low energy, low latency, and high BW: Use of software-controlled segmented buses.

• Buses are divided into segments. Use of tri-state switches. Energy Optimal Segmented Bus (ESB) Architecture


Data PlaneData Plane• Infrastructure that provides the means for the transfer of data from

source to destination. Buses and switches.• Issues: number of parallel buses, and where to insert the switches.• Assumption: application is fully characterizable at compile-time.

Switches can be unicast or multicast

Control PlaneControl Plane• Infrastructure that provides

the correct routing of data.• Communication Control block

& Control Decoding Logic are part of Control Plane.

• Communication conflicts are resolved at compile and synthesis time.


OutlineOutline



• Single-Tile in a SoC.• Three hardwired datapaths

(demodulator with FFT processor, deinterleaver, Viterbi decoder) and 9 working memories.

• Communication architecture is clustered into 3 set of segmented buses.

• Each switch is controlled by the network controller.

Digital Audio Broadcast (DAB) ReceiverDigital Audio Broadcast (DAB) Receiver

Block diagram of a DAB receiver[11]


Architectural OptimizationsArchitectural Optimizations

• Switches were clustered into groups.

Communication Architecture OptimizationCommunication Architecture Optimization

System PartitioningSystem Partitioning• Partition the system into non-communicating clusters.• No memory have access to more than one datapath port.• Data and address buses that connect memories to datapaths

are partitioned into three smaller buses.

Physical Design OptimizationPhysical Design Optimization

• Floorplan is generated according to block’s comm. activities.• Highly active memories are placed close to its PE.


OutlineOutline



ResultsResults

Area breakdown of DAB using the Segmented Bus Architecture

Break down of Storage Energy and Data Transfer for the DAB @ 130nm. Measurement unit is Joules.

Critical path in segmented bus communication architecture was 1.8 ns.Critical memory access time was 2.5 ns.


OutlineOutline



• Communication is becoming a significant part of energy consumption in SoC designs.

• Use of software-controlled implementation of segmented buses provided the required latency and bandwidth for intra-tile communication.

• Significant energy savings compared to using single shared bus.

ConclusionsConclusions


ReferencesReferences[1] A. Papanikolaou et al ”Architectural and Physical Design Optimizations for Efficient Intra-tile [1] A. Papanikolaou et al ”Architectural and Physical Design Optimizations for Efficient Intra-tile

Communication”, Proceedings of the 2005 International Symposium on System-on-Chip, 17-17 Nov. Communication”, Proceedings of the 2005 International Symposium on System-on-Chip, 17-17 Nov. 2005, pp 112 – 115, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01595657 2005, pp 112 – 115, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01595657

[2] S. Pasricha, N. Dutt, “On-Chip Communication Architectures: System on Chip Interconnect”, Morgan [2] S. Pasricha, N. Dutt, “On-Chip Communication Architectures: System on Chip Interconnect”, Morgan Kaufmann, 2008. Kaufmann, 2008.

[3] ARM, AMBA Bus specification,available at: http://www.arm.com/products/system-ip/amba/index.php [3] ARM, AMBA Bus specification,available at: http://www.arm.com/products/system-ip/amba/index.php [4] IBM, CoreConnect Bus Architecture, available at: [4] IBM, CoreConnect Bus Architecture, available at:

https://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture https://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture [5] ST Microelectronics, STBus specifications, available at:[5] ST Microelectronics, STBus specifications, available at:

http://www.st.com/stonline/products/literature/um/14178.pdf http://www.st.com/stonline/products/literature/um/14178.pdf [6] WISHBONE specifications http://www.opencores.org/downloads/wbspec_b3.pdf [6] WISHBONE specifications http://www.opencores.org/downloads/wbspec_b3.pdf [7] W. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks", Design Automation [7] W. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks", Design Automation

Conf, June 2001, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=935594 Conf, June 2001, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=935594 [8] [8] L.Benini, G. De Micheli, "Networks on chips: a new SoC paradigm", IEEE Computer, Jan. 2002.L.Benini, G. De Micheli, "Networks on chips: a new SoC paradigm", IEEE Computer, Jan. 2002.[9] J. Plosila, T. Seceleanu, P. Liljeberg, "Implementation of a self-timed segmented bus", IEEE Design & [9] J. Plosila, T. Seceleanu, P. Liljeberg, "Implementation of a self-timed segmented bus", IEEE Design &

Test of Computers, Nov. 2003, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1246163 Test of Computers, Nov. 2003, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1246163 [10] J. Guo et al, “Topology exploration for energy efficient intra-tile communication”, Design Automation [10] J. Guo et al, “Topology exploration for energy efficient intra-tile communication”, Design Automation

Conference, 2007, pp 178 – 183, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4196028 Conference, 2007, pp 178 – 183, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4196028 [11] K. Taura et al “A digital Audio Broadcasting (DAB) Receiver” IEEE Transactions on Consumer [11] K. Taura et al “A digital Audio Broadcasting (DAB) Receiver” IEEE Transactions on Consumer

Electronics, 1996, pp Electronics, 1996, pp 322 – 327322 – 327,, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00517204 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00517204


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Architectural and Physical Design Optimization for Efficient Intra-Tile Communication Liza Rodriguez Aurelio Morales EEL 6935 - Embedded Systems Dept