APPROVED FOR PUBLIC RELEASE. CASE 06-1104.dome.mit.edu/bitstream/handle/1721.3/38969/MC665_r04_E-438.pdf · Engineering Mote E-A3& Page 1 of 18 ... exceeds its modulus, ... maintain

6345 Engineering Mote E-A3& Page 1 of 18

Ligital Computer Laboratory Massachusetts Institute of Technology

Cambridge, Massachusetts

SUBJECT: BINARY COUNTING KITH :,UGNET1C CCEES

To: N. H. TayJor

From: L. A. Buck

Late: December 6, 1951

Abstract: Magnetic materials suitable for multi-dimensional memories have recently become candidates for circuit elements in other parts of a d ig i ta l computer. Their possible uses in binary counters and as pulse-operated gates are being considered.

A. INTF01UCT30N

In a binary adder any one of the stages, except pcssibjv the f i r s t and the l a s t , must be prepared to interpret a combination of ONE's and ZEFO's on three inputs and supply a ONE or ZERO to each of two outputs. Two of the inputs are the d ig i t s to be ceded and the third i s the carry from the preceding stege; the outputs rre the sum digi t end the oerry to the following stege. The relationship between the input combinetion of ONE's anc ZERO1a anc the output combination of ONE's and ZERO1a i s the well known blnery addition table. I f e stage receives a carry from the preceding stage anc at the same time transmits t carry to the following stage, i t i s sold to "propagate" the cerry, anc the carry i s thought of as pessing through the stege. I f a stage has no carry as an input but does have e cerry es an output, i t i s seid to "originate" e carry, and conversely, i f a stcge has a carry input but no cerry output, i t i s then said to "block" the carry. These definitions wi l l be used in the f o l l o wing discussion.

B. COUNTERS

Counting i s e speolel case of addition in which one of the addenda i s slweys unity. In counting however, unlike in ecdition, only the leas t significant strge can orlglnete e crrry. All other stages either propagate or block a oerry. The oarry can be- thought of es originating in the l e e s t significant stage eno propagrtlng up through the stages unt i l i t i s blocked; having been blocked i t cannot start agein.

APPROVED FOR PUBLIC RELEASE. CASE 06-1104.

6245 Engineering Note E-438

The carry can propagate through any number of stages in the counter from none to the maximum number. The corry propogates through no stages on alternate counts v?hen unity is acded to an even Dumber eno merely changes the least significant digit from ZRF.O to ONE, and the carry propagates through the maximum number of stages when the counter exceeds its modulus, or "overflows". The latter case in many ways subjects a given counter cesign to its most difficult operating concitions. The carry, as it propegrtes up the entire iength of the counter, must maintain its amplitude and waveshape to an extent that will allow it to accomplish its eddition function at each stage. In this case, also, the greatest amount of time is required for the cerry to come to a stop so that the counter can be read. Since no knowlecge of the count is assumed et the time of reading, the maximum carry propagation time must be allowed efter each enc every count.

The problem of meking the carry propagate rapioly has been temporarily deemphasized here in view of the more fundamental problem of maintaining the amplituce and waveshape of the carry as it propagates. At present, it seems desirable that for ell except very short counters the carry be amplified in some manner as it goes from stage to stege, and since it is hoped that the obvious expedient of putting c vecuura-tube amplifier between stages csn somehow be avoided, a smell-scale investigation of possible techniques of getting the carry up through the steges was uncertaken. The progress to date will be briefly reported.

Counters are often divided into two categories: those in which the carry is regenerated by each stage ss it flips over from ONE to ZERO, and those in which the carry propagates through gates which are controlled by the various strges. logically the two ere identical, especially when the regeneration by each stage of a counter of the first type is thought of as a gating action. The distinction, however, exists, and the counters in the first category are called "progressive-carry" counters while those in the second category are called "geted-carry" counters.

1. Progressive-carry Counters

In progressive-carry counters the carry, as it enters a stage, causes the stage to trigger, that is, to change to ONI if it contains ZERO or to ZERO if it contains ONE. In the letter cese, in which the stage changes from ONE to ZERO, the carry is re-shaped end delivered to the following stage. This process continues up through the stages until the carry comes to a stage which already contains ZERO. This stage is changed from ZERO to ONE and the carry stops. The power gain of each stage is utilized in the re-shaping process so that the carry propagates without attenuation.

To date, magnetic-core counters in the progressive-carry category are restricted to those which use a high-frequency magnetic amplifier type of flip-flop. One stege of a counter representative of this class is shown in Figure 1. Developed by Computer Research Corporation, it was


6345 Engineering Note L-438

precedec by e s imiler development by Ingineernng research Associates. Robert Pfaff, 3 S.M. thes i s student with the group, i s a t present inves t igating the possible use of a counter of th i s type in an application associated with the M.l.T. Servo Laboratory Ki l l ing Machine Project .

2 . Gated-carry Counters

Gated-carry counters (Fig. 2) are those in which each stage of the counter operates e gate which controls the car ry . Figure 2a i l l u s t r a t e one stage of a geted-carry counter in which, a f te r a short delay, the f l i p -flop i s tr iggered by the carry entering the s tage . I f the stage contains ONE, the carry has time before the f l ip - f lop t r igge r s to pass through a gate which i s held open by the ONE-side of the f l i p - f l op . I f the s tage , on the other hand, contains ZERO, the f l ip - f lop i s t r iggered, but by the time the gate on the 6NE-side opens, the carry pu l se , which i s shorter then the delay, disappears and i s not propagated to the following s tage . Figure 2b i l l u s t r a t e s one stage of a similar gated-carry counter in which the f l ip - f lop need not be capable of t r igger ing . Two gates instead of one, however, are required.

A scheme has been worked out (Fig. 3) to use pulse-operated magnetic cores i n t h i s l a t t e r configuration. This i s actual ly a four-core stepping r e g i s t e r arranged so t ha t the output feeds brck in to the input . The logical operrt ion wi l l be described here, but the c i r cu i t design considerations wi l l be covered in the section on pulse-operated magnetic gates . Magnetic cores numbered 1 and 3 are the f l i p - f l op and cores 2 and 4 are the gates of the gated-carry counter. Among the four cores of a s tage, there i s but a single ONE and three ZERO's. The single QBE wi l l always l i e , when the counter i s a t r e s t , in e i the r core number 1 or core number 3 , the two cores of the f l i p - f l o p . I f the ONE l i e s in core number 1, the f l i p - f lop contains ZERO and i f i t l i e s in core number 3 , the f l i p -flop contains ONE. The carry input pulse i s made in to two power pulses which are displaced in time one from the other by the delay. The f i r s t of these , power pulse I , drives the information from the odd-numbered cores in to the even-numbered cores ( f l ip- f lop in to ga t e s ) , while the second, power pulse I I , drives the information from the even-numbered cores in to the odd-numbered cores (gates in to f l i p - f l o p ) . The single ONE, then, wi l l c i r cu la t e around the loop of four cores once for every two carry input pu l s e s . Each time i t rounds the bene at core number 3> a carry i s sent to the following s tage . A carry can also be taken from core number U which w i l l be delayed from tho carry from core 3 so tha t the delay can be eliminated in a l l but the f i r s t s tage , only amplification being needed in succeeding s t ages . The vacuum tube amplifiers shown coulc probably be eliminated for a very short counter, as already mentioneo. A four-core stepping r e g i s t e r of t h i s design (minus carry output leads) was constructed by the group. Using f e r r i t e cores , i t was able to count a t a r a t e exceeding 100 KC.



C. PUI SE-OPEFATEL MAGNETIC GATE-JUI-'UFIIES.

At this point v?e deport from counters temporarily to invest igate the possible use of pulse-opercted magnetic cores to replace the vecuum-tubes as cerry amplifiers and gates.

1, A Simple Coincidence Gate

Cne scheme which suggests itself is to apply a power pulse end a pulae to be amplified simultaneously through windings N£ and Ni, of Fig. 4a, in such a way that the power pulse alone i.i not enough to switch the core but the combination of the two pulses will switch the core. As the core switches, the instantaneous power delivered by the power pulse is the product of the instantaneous voltage and the instantaneous current in winding N2. Symbolically, P2= •2i2"*2^2 » • simiJerly» Piî1-!*111*1 2^

and the output power vêîÛjij M Since, auring switching, the dj|

is common to all windings, the power going into each of the two criven windings 16 proportional to the ampere-turns of that rinding, and since the power going into these driven windings must go sonowhere, it goes into the load, supplying the output power. The requiioment governing the ampere turns in the two driven windings is that their rum slightly exceed the knee of the hysteresis loop. The ratio of rower-pulse ampere-turns, ^2i2» *° ^ e pulse-to-be-ampllfied ampere-turns, N3.i1, night be made arbitrarily large and therefore it would appear that tht power gain is limited only by the degree to which the amplitude of the power pulse can be controlled.

When the hysteresis loss of the core is consideiod, however, the inability of the scheme to provide power gain is clearly s-en. The hysteresis loss in the core, flidB, is the area of the hysteresis loop. As this gate operates, moving from one residual point on the hysteresis loop to the other, one haif of the hysteresis loop area must be cisnipeted in the core. The power-pul8e ampere-turns, N2*2» can b e tnouEht oJ (Fig. 4b) as supplying a fraction of the hysteresis loss which is erbilrerily close to, but never greater than, unity. If the power puloe were 1o supply more than just the hystereais loss, the core v/oulc switch on this pulse alone, thereby destroying the geting aotion of the core. The pulse to be amplified, then, supplies the rest of the hysteresis loss plus the power delivered to the load. Clearly, as in the case of a convents :>nal transformer, there can be no power gain.

2. The Harvard Gete-Ampllfier

A pulse-operated magnetic gate which does have a potor gain (Fig. 4c) has been developed by the Harvard Computation Laboratory. In this scheme, the power pulse and the pulse to be amplified are not applied simultaneously, and they ere eech large enough to switch the are. The pulse to be amplified is first applied, switching the core fron ZEJ.O on


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6345 Engineering Note h-A38

the top of the hysteresis loop, the core's rest stete, to ONE on the bottom. Vi'hen the pulse to be amplified is removed, the core is lei o at OKF on the bottom of the loop, where it will remain until the power pulse is applied. The power pulse, appliea so as to produce flux in the opposite direction, switches the core back to ZEEC, anc the gate is once agein in its rest position. The presence of the rectifier in the loed circuit effectively removes the load when the pulse to be amplified switches the core but reconnects the load as the power pulse switches the core in the oprosite direction. This allows the power pulse to supjly power to the load as well as one-half of the B-H loop area, whiJe the pulse to be emplifiea merely supplies the other half of the B-H loop area. If the pulse to be amplified is defined as the input to this core anc the pulse delivered to the load is defined as the output, it can then be said that the core gives a power gain. Gating action is achieved by virtue of the fact that if a power pulse comes along without having been preceooo by a pulse to bo amplified, the core, which is alrefdy on the top of its hysteresis loop, wiJl move from ZERO to "a" anc back causing a negligible chenge in inoucticn and therefore no pulse in the load. If it is assumed that at the time of a power pulse one does not know in which state the core lies, then there will or will not be a pulse in the loac depending upon whether or not a pulse to be amplifieo came along. The joilse to be amplified, then, csn be thought of as a gating pulse.

This gate, beside provicing amplification, has the most cesirable feature that neither the pulse to be amplified nor the power pulse need be measured pulses. They are only required to exceed a minimum value, above which they can have any value whatever.

An interesting feature of this gate is that only one pulse can pass for each gating pulse, a feature which might be usee to acvantage in an application such as a push-button pulse synchronizer in which en asynchronous pulse is used as the gating pulse and the first clock pulse to come along after the gating pulse is used as the power purse. All subsequent clock pulses would merely drive the core from ZLFO to "a" and back, the gate being "off". In this application, the gating pulse would have to be larger in ampere-turns than the power pulse so that it coulo overwhelm the power pulse in the event they coinciced with one another in time.

•• This i s the gate used in the magnetic stepping register anc

in the gatec-carry counter already described. .It has the obvious disadvantage that a time oelay i s required between input anc output. If, in the gated-carry counter already described, this gate were used to replace the tubes used to amplify the carry between stages, a succession of these delays woulo be required in order that a carry propagate the entire length of the counter.


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3. A Current-Biased Gate Amplifier

Still another magnetic-core gate has been ceveloped which is turned off by a current through one of its windings (Fig. 5)» in a way analagous to that in which a vacuum-tube is biased off by a negative voltage. A large m.m.f. due to the control current, ±2, will hold the core in a region where there is a negligible induction change for a given change in power-pulse m.m.f. In this region, the power pulses are effectively disconnected from the load since coupling is by chenges in induction. Furthermore, there will be little voltage across the control winding, N^, and the power winding, Ng, so that a negligible amount of power will be supplied by these circuits when the gate is "off". Removal of the control current, i l t allows the core to move to its residual Induction point on the bottom of the hysteresis loop and the gate is then said to be "on". If, when the gate is "on", a positive pulse followeo by a negative pulse occurs in the power winding, N2, the core will go around its hysteresis loop and the resulting induction change will oeliver a positive and negative pulse to the load. The oontrol circuit, oeliverinf zero current, will absorb no power. Subsequent pairs of positive and negative pulses in the power winding, N2, rill deliver pulses to the load. These pairs can, in fact, be sine waves, if it is desired merely to couple power to the load, as would be the case if the load were a panel lamp in an indicator circuit. A variation is to have a single positive pulse which will act as in the gate previously described coupling a single pulse to the load and then no more until the gate is turned "off" end then "on" again.

This gate has been extended to a scheme in which a core can be biased off by any number of control windings, each of which acting alone Is enough to hold the gate "off". K. Olsen has applied this to a multi-position switch in which the control windings on a number of cores are connected as a matrix so that all of the cores except one are biased off. This gating scheme is the basis for a "carry-matrix" type of gated-carry counter yet to be described.

I. A CARET-MATRIX COUNTER

Taking advantage of the fact that the carry progresses through the stages of a counter, triggering each of them, until it comes to a stage containing ZERO which it triggers and then stops, we can use the gate just described to control the carry. Consider a matrix of magnetic cores (Fig. 6) In which there is one core whose responsibility it is to propagate the carry to each stage. These cores are connected as gates in such a way that a ZERO in any stage of the counter will bias off all of the gates leading to higher stages. This scheme Involves the use of fîp-flops which can be tripgered. An extension of this (Fig. 7) uses two cores instead of one to propagate the carry to each stage. The


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t ttage itself biases one of the two cores off. The output of one of the cores sets the flip-flop to ONE while the output of the other sets the flip-flop to ZERO. The whole thing is so arranged thet if the flip-flop is ZERO it gets set to ONE or if it is ONE it gets set to ZERO, and therefore need not be capable of triggering.

This concludes the discussion of counters. It was felt that the informal appendix at this point is a useful way to introduce some of the design problems and techniques.

S1GNEL Duale; Buck

APPIOVED j4j D

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Appendix 1 , Pages 8-10 drawings SA-50622-3-4) Appendix I I , Page 11 drawing SA -50625) Lrawinge Attached:

F i g . 1 - Drawing No. SA-50617, Page 12 F i g . 2 - Drawing No. SA-50618, Page 13 F i g . 3 - Drawing No. SA-50619, Page 14 F i g . 4 - Drawing No. SA-50620, Page 15 F i g . 5 - Drawing No. SA-50621, Page 16 F i g . 6 - Drawing No. SA-50532 Page 17 F i g . 7 - Drawing No. SA-50561, Page 18

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APPROVED FOR PUBLIC RELEASE. CASE 06-1104.dome.mit.edu/bitstream/handle/1721.3/38969/MC665_r04_E-438.pdf · Engineering Mote E-A3& Page 1 of 18 ... exceeds its modulus, ... maintain