Applying Effective Dynamic Frequency Scaling Method in Contactless Smart Card

1828 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 10, OCTOBER 2012

Applying Effective Dynamic Frequency ScalingMethod in Contactless Smart Card

Mingyu Wang and Hao Min

Abstract—A creative dynamic frequency scaling method in con-tactless smart card is presented for the first time. A low powermagnetic field detection circuit, a simple load detection circuit, thequick load comparator and the simple clock switch scheme in themethod are also presented. The test result shows that the longestcommunication distance is improved from 6 to 8 cm compared tothe same contactless smart card (CSC) chip using the fixed fre-quency divided by 4 and the transaction time is saved by 18% inaverage, compared to the same CSC chip using the fixed frequencydivided by 8.

Index Terms—Communication distance, contactless smart card,dynamic frequency scaling (DFS), load detection circuit, lowpower, transaction time.

I. INTRODUCTION

D YNAMIC voltage and frequency scaling (DVFS) tech-nique has proven to be a highly effective method of

achieving low power consumption for the system on chip(SOC) while meeting the performance requirements due to thefact that extending the service lifetime of these systems byreducing their power dissipation requirements is a key require-ment [1]. A number of modern microprocessors such as Intel’sXScale [2] and Transmeta’s Cruso [3] are equipped with theDVFS functionality. The key idea behinds DVFS techniquesis to dynamically scale the supply voltage level of the SOCso as to provide “just-enough” circuit speed to process thesystem workload while meeting the total compute time and/orthroughput constraints, and thereby, reducing the energy dissi-pation demand for low power consumption in active systemshas risen sharply. However DVFS technology is used only inthe active devices especially for the battery-powered devices,this is because extending the service lifetime of these devicesby reducing their power requirements is a key customer/userrequirement.The circuit power can be divided into dynamic power and

static power, here we only discuss dynamic power, and it is de-fined as [4]

(1)

(2)

Manuscript received April 26, 2011; revised July 25, 2011; accepted August01, 2011. Date of publication September 12, 2011; date of current version July19, 2012.The authors are with the State Key Laboratory of ASIC and Systems, School

of Microelectronics, Fudan University, Shanghai 201203, China (e-mail: [email protected]; [email protected]).Digital Object Identifier 10.1109/TVLSI.2011.2164560

where is the circuit total load capacitance, is the cir-cuit working voltage, is the proportion of the work of thecircuit, is the operating clock frequency, is the CMOSswitch on time, is the circuit short current, is thetotal dynamic energy consumed by the circuit in a period of .For the given mission, is a constant value, thus in orderto truly reduce the energy consumption for the active device,DVFS method needs not only to lower the frequency but also tolower the voltage at the same time.However, DVFS techniques to reduce and to optimize the

power consumption in the active embedded systems [5], [6] arenumerous even in multi-core active devices [7], [8]. To the bestof knowledge, the dynamic frequency scaling method is neverused in the passive devices such as contactless smart card. Thispaper explains the difference between active (battery driven)and passive (RF coupled) devices powered methods and its im-pact on the DFS method realization. It also introduces the detailmodules’ design for the DFS method and chip test result com-parison with and without DFS function.

II. ENERGY TRANSMISSION

In the passive devices such as contactless smart card or pas-sive radio frequency identification (RFID), the low power re-quirement is different to the active devices. Its energy comesfrom coupled magnetic flux generated from reader’s antennacoil, the magnetic flux is expressed by (3) [9], [10]

(3)

where is the coupled magnetic flux from reader, is thecurrent of the reader’s antenna coil, is the number of coilturns, is the radius of coil loop, is the distance from thecenter of the coil. is a constant value: . Equation(3) indicates that the magnetic field produced by a loop antennadecays with , according to the Electromagnetic inductiontheory, the coupled voltage of the tag’s antenna coil is expressedby (4) [10]

(4)

where is frequency of the arrival signal, is number of turnsof tag’s antenna coil, is area of the loop in square meters, isthe magnetic field strength of the arrival signal, is the angle ofarrival of the signal, is the quality factor of the tag’s circuit.From (4), we know that the coupled voltage by the card antennais inversely proportional to the distance from reader to the tag.Based on the energy transmission mechanism of the contact-

less smart card, we can conclude the following.

1063-8210/$26.00 © 2011 IEEE

WANG AND MIN: APPLYING EFFECTIVE DYNAMIC FREQUENCY SCALING METHOD IN CONTACTLESS SMART CARD 1829

1) As long as the contactless smart card is located in the ef-fective magnetic field generated by the reader, it can con-tinuously recover the energy to provide necessary power towork.

2) The communication distance of the contactless smart cardis inversely proportional to its consumed peak power. Thelower the peak power, the longer the communication dis-tance.

There are many different low power design methods used inthe contactless smart card such as adiabatic circuit and asyn-chronous circuit. Though these low power methods are effec-tive compared to the normal synchronous circuit design used inthe contactless smart card, they suffers from a lack of dynamicadaptation to the real coupled energy situation which meansonce the energy is enough to support the contactless smart cardto run in better performance or higher frequency, these methodscannot take full advantage of the coupled energy which can befully used.Meanwhile the realizations for these methods are very com-

plex because they can’t use normal CMOS library provided bythe foundry directly. Adiabatic circuits [11], [12] use the adia-batic-quasi-static (AQS) CMOS logic circuit and the special ACpower for the AQS CMOS logic. Foundry library does not pro-vide the adiabatic logic cells normally. Asynchronous circuitsuse quasi-delay-insensitive (QDI) logic [13] or special hand-shake circuit [14] instead of standard CMOS logic cells to re-alize the asynchronous pipeline. The designer should create thespecial adiabatic or asynchronous CMOS cell library for simu-lation, synthesis and place&route, the design flow and processbecome very complex.DFSmethod can avoid these defects. It is used for the contact-

less smart card to run in the maximum frequency or operationspeed which can be afforded by the present momentary coupledpower from the reader machine in any communication distance.DFS method also directly uses the normal design library pro-vided by the foundry, its design flow and process is normal andmuch simpler than the adiabatic and asynchronous circuit de-signing process for the contactless smart card chip.

III. DFS VERSUS DVFS

Since the contactless smart card can fully use the coupled en-ergy from the reader, it does not need to save the coupled energyat any time as long as the peak momentary circuit consumedpower does not exceed the coupled momentary energy from thereader. The key difference of low power design between activedevice and passive device is that the former needs to lower theaverage power in a given time period and the latter needs tolower the momentary power, this is also the theory base of thisDFS method used in contactless smart card.Table I shows the feature comparison between DFS method

presented by this paper and DVFS method used in active de-vices. Though DFS method thinking is created from DVFS andit also needs to detect the present module power load, it doesn’tneed the future power load prediction algorithm as DVFS.DVFS method in [15] combines the long term metric valueprediction and duration prediction methods; [16] improves therobustness of low power scheduling algorithms on DVFS byassuming that the worst case execution number of cycles might

TABLE ICOMPARISON BETWEEN DFS METHOD AND DVFS METHOD

be imprecisely known; [17] uses a prediction equation basedon the correlation of the memory access rate. For the reason ofthat DFS method does not need to actively change the voltageand does not need to realize the load prediction algorithm asDVFS method before adjusting the clock frequency, its clockswitch speed is much quicker than DVFS method.This paper fully integrates the DFS circuit into the contactless

smart card chip whose communication interface compiles to theISO/IEC 14443 TYPEA protocol, the carrier frequency of theoperating field is 13.56 MHz 7 kHz [18].

IV. CIRCUIT DESIGN

DFS method is mainly composed by modules of magneticfield detector, load detector and load comparator as shown inFig. 1. Magnetic field detector is used to check the amount ofthe coupled energy from reader to indicate the energy supplyingstatus. Load detector checks the current modules load to indicatepresent energy consumed status. The two statuses are comparedby the load comparator to decide the appropriate operation fre-quency for the contactless smart card chip.

A. Magnetic Field Detector

Magnetic field detector in Fig. 2 is used to convert the coupledenergy to DC voltage, it’s composed with rectifier and threevoltage comparators. As in Fig. 2(a), the rectifier is a full-waverectifier, where M1 and M2 compose diode access circuit, M3and M4 act as switch access circuit, their drain-source voltageis small when they are switched on alternatively, as in (5)

(5)

where is the coupled voltage by tag’s antenna coil, isthe threshold of theMOSFET. Because the simulation result and


Fig. 1. DFS block diagram (where is the frequency divider, 13.56 MHz).

Fig. 2. Magnetic field detector circuit. (a) Rectifier circuit. (b) Voltage comparator circuit.

real test result shows that the range of VCCL which supportsto establish communication is from about 1.8 to 3.6 V and theV_REF comes from band gap voltage reference can provide thereference voltage from about 0.5 to 1.3 V, so we divide VCCLby 3 as the voltage being compared, as in (6)

(6)

The voltage comparator compares the reference voltage(V_REF) and divided sample voltage (VCCL_P) as in Fig. 2(b).It outputs one bit comparison result (voltage_flag). It uses dif-ferential-input and single-output structure, if the sample voltageis larger than the reference voltage, it outputs high level signaland vice versa, where M5 and M6 is a pair of differentialtransistors, M15 and M18 are the load transistors, M16 andM17 realize positive feedback to make the circuit have a certainhysteresis. The bias current is mirrored to M11, M12, and M14through M13 in proportion, its output connects to one buffer torestore the logic levels and increase the output drive capability.In the voltage comparator circuit, V_REF comes from band

gap reference circuit. Its theory is based on the character ofthat Si’s band gap voltage is stable and independent of temper-ature to achieve low temperature drift, high precision referencevoltage. As in Fig. 3(a), the band gap reference circuit, whereM20 and M21 provide the current, M20, M21, and M22 havethe same gate length, meanwhile the sizes of M20 and M21 aresame. Uses of the op amp’s “virtual short” feature, the circuit isin the status of deep negative feedback to clamp Vip and Vin tobe equal.There are many different kinds of smart card readers in the

real market, from (3) and (4), we can conclude that the range of

the coupled energy is different with different readers, thus thevalue range of VCCL in the rectifier is also different with dif-ferent readers. In order to reflect the real situation, the referencevoltages (V_REF1, V_REF2, V_REF3) can be adjusted by threetrim bits, as in Fig. 3(b). Whenis zero, the related switch is opened, its parallel resistance isshorted and V_REF1 is also changed accordingly. Roi ( 1,2, 3, 4) is used to divide the reference voltage. Table II shows therelationship between the trim values and the reference voltagesand Fig. 4 shows the simulation result by using SMICS 0.18 mlibrary in the Fast/Fast(FF) process corner, the entire band gapcircuit consumes 23.6 A current.

B. Load Detector

The load detector continuously monitors every module’sbusy signal, and then it adds each active module’s load weightwhose busy signal is active high to get the present power load(PL) value in Fig. 5 to indicate the chip load status. Table IIIshows the module load weight from power simulation resultusing the same library and process corner as previous circuitsimulation. There are two types of the modules, one is the clockdriven module which means that the module’s power is changedwith its operation clock frequency, the other is non-clock drivenmodule which means that the module’s power is not changedby its operation clock frequency. The module load weight isproportional to the power simulation result, since PMU, RF,and OSC always work on and their loads are not changed to thefrequency adjustment, their loads are set to be zero during loaddetection process for the calculation convenience.


Fig. 3. Band gap voltage reference circuit. (a) Reference circuit. (b) Trim circuit.

Fig. 4. Simulation result for the reference voltages with different trim values.

TABLE IIREFERENCE VOLTAGES WITH DIFFERENT TRIM VALUES

Power simulation result reflects the roughly proportional rela-tionship among different modules driven by clocks. PVT corneranalysis such as TT, SS, FF, and so on shows almost the samepower load proportional relationship. The power simulation re-sult is used for three purposes: 1) to calculate the maximumthreshold; 2) to set the initial load threshold, the final test loadthreshold is based on this and can be adjusted; 3) to give everymodule’s power load weight.The maximum load is happened in f/2 (13.56 MHz/2) fre-

quency when all of MCU, ROM, RAM, CLK_CTL, and RNGare work, set this load equal to 40, all other cases are smallerthan this load threshold as Table IV shown.

C. Load Comparator

The load comparator compares the results come from voltagecomparator and load detector. The six-bit present load thresholdregisters can be set in the chip according to the real coupledenergy for different readers. During the chip test process, wechoose the reference voltage ' and set the presentload threshold values as Table IV shown to realize the best DFS


Fig. 5. Load comparator determination flow (where PL is the present or currentmodules load, PL_TH is the present load threshold, N is the new frequencydivider ( , 2, 4), n is the present frequency divider ( , 2, 4)).

TABLE IIIMODULE LOAD WEIGHT

method performance. The determination process is shown in

TABLE IVLOAD THRESHOLDS WITH DIFFERENT COUPLED VOLTAGES IN THE CHIP TEST

Fig. 6. Clock mux structure.

Fig. 5, the PL value comes from load detector is updated every4.7 s (8 cycles of f/8) and the present load threshold value isdecided by the three-bit voltage flag. The purpose is to makethe chip run in the most appropriate frequency according to themomentary coupled power.For an example, if present ' (its related

load threshold is 24 as Table IV shown), present frequency isf/8 and PL value is 35, divide PL by present frequency divider

is 8.75, it is smaller than 24, thus there is no need tochange the present frequency . Another example is ifpresent ' , present frequency is f/4, presentpower load is 10 and multiply it by present frequency divider

is 20 which is smaller than its load threshold, thus thecomparator will choose the new frequency of f/2for the chip. The DFS method should guarantee the present

power load divided by the frequency divider is not more thanthe present load threshold at any time.

D. Clock Switch Scheme

Because DFS method continually carry out the clock fre-quency switching, in order to guarantee the quick frequencyswitching without glitch is the necessary condition to be suc-cessful for the DFS method. As in Fig. 6, there are four clocksin the clock mux module, clk0 is 13.56 MHz, clk1 is two fre-quency-division of clk0, clk2 is four frequency-division of clk0and clk3 is eight frequency-division of clk0. All of the fourclocks are the synchronization clocks, the two-bit register select[1: 0] is used to select the clock output through mux. In orderto avoid the glitch, the mux must use the negative edge of theclock to switch the clocks.


Fig. 7. Clock switch waveform. (a) Case 1: switching clk2 to clk3 needs oneclk3 cycle. (b) Case 2: switching clk2 to clk3 needs one clk2 cycle and one clk3cycle.

Fig. 8. Microphotograph of the contactless smart card chip.

There are two clock switch cases, one is that there is onlyone bit of select register has been changed

, in this condition, the slowest of the clock switching ishapped at the case of that the select register is changed from 10to 11, it needs almost one clk3 cycle in Fig. 7(a). The other caseis that there are two bits have been changed at the same time

, the slowest of theclock switching is happed at the case of that the select register

Fig. 9. Measured contactless smart card transaction time.

Fig. 10. Test result for the transaction time and distance.

is changed from 00 to 11, it needs about one cycle of clk2 andone cycle of clk3 to switch the clock in Fig. 7(b).Meanwhile the sum of each module present power load and

the procedure for the comparison of power load in the DFSmethod are realized by combination logic. Thus we can con-clude that the speed of clock switch in the DFS method is veryfast based on previous analysis, it is less than 8 cycles of clk0for six bits sum and comparison plus 2 cycles of clk3 to switchthe clocks, total time is less than 2 s and can be almost negli-gible. Therefore, compared to DVFS approach, DFS can morequickly and efficiently switch the clock directly without takingtime to realize the load prediction algorithms used in DVFS (seeTable I).

V. RESULTS

The microphotograph of the contactless smart card chip isshown in Fig. 8. It includes the bonding test PADs and the non-bonding test PADs located in the scribe lane (the bottom of thechip), the chip size is 2.2 mm 2.4 mm.As in Fig. 9, the measured contactless smart card transaction

time in the distance of 8 cm from card to reader, the transactionoperation includes one-time of DES encryption/decryption, 16bytes EEPROM erase/write/read and 8 bytes random data gen-eration. Fig. 10 shows the DFS performance test result for thesame chip. The maximum communication distance of the chipwith DFS method is 8 cm, compares to 2 cm and 6 cm for the


fixed frequency of f/2, f/4 respectively. The average transactiontime using DFS method is 103 ms corresponds to the commu-nication distance from 0 to 8 cm, the average transaction timeusing fixed frequency of f/4, f/8 is 110 and 126 ms, respectively.

VI. CONCLUSION

The test result shows that the simple DFSmethod is effective.It makes the contactless smart card reach to the longer commu-nication distance and the less transaction time than the samechip without DFS method since these two parameters are themost important features for the contactless smart card.

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Mingyu Wang received the B.S. degree fromHuazhong University of Science and Technology(HUST), Wuhan, China, in 1999, and the M.S.degree in electronic engineering from ShanghaiJiaotong University (SJTU), China, in 2001. He iscurrently pursuing the Ph.D. degree in microelec-tronics from Fudan University, Shanghai, China.His research interests include mixed signal circuit

design, low power integrated circuit design.

Hao Min received the Ph.D. degree from the De-partment of Material Science, Fudan University,Shanghai, China, in 1991.He served as an Associate Professor with the

ASIC and Systems State Key Laboratory, FudanUniversity. From 1995 to 1998, he worked as aVisiting Associate Professor with the Departmentof Electrical Engineering, Stanford University,Stanford, CA, where he focused on low power mixedsignal VLSI design especially on the design andcharacterizing of CMOS image sensors. From 1998

to 2005, he served as a Professor and Director of ASIC and Systems StateKey Laboratory, Fudan University, where he worked on the smart card andRFID chip technology. His research areas include VLSI architecture, RF andmixed signal IC design, digital signal processing, image processing, etc. Hehas published over 50 papers in journals and conferences. He is the inventor ofmore than 20 patents (pending).

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Applying Effective Dynamic Frequency Scaling Method in Contactless Smart Card