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External Use
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SILICON SYSTEMS GROUP External Use SILICON SYSTEMS GROUP
Applied Vantage® Vulcan™ RTP The Better Side of Anneal
Sundar Ramamurthy, Ph.D.
Appointed Vice President
General Manager, Front End Products
Silicon Systems Group
June 29, 2011
External Use
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SILICON SYSTEMS GROUP 2
Mobility and Connectivity Driving Growth
in Lower Power, High Performance Chips
External Use
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SILICON SYSTEMS GROUP
Centinel™ PVD / ALD
Reflexion GT™ for Cu
Raider® GT
DFinder™ Inspection
Astra™ DSA
Siconi™ for Epi
Avenir™ RF PVD Gate
Eterna™ FCVD
Avenir™ RF PVD Ni
Conforma™ Doping
Reflexion GT™ for W
Innovations Enable Inflections
3
Raider S™ ECD
InVia™ CVD
Avila™ CVD
Silvia™ Etch
Mesa™ Etch
UVision® 4 Brightfield
Tetra™ X
Aera3™
Centris™ Etch
Vantage Vulcan™ RTP
External Use
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SILICON SYSTEMS GROUP
What is Rapid Thermal Processing?
4
900
1000
1100
Temp (°C)
Time (s)
800
1-2
secs
700
Spike
>200°C/sec
ramp
Jet Engine
Temperatures
1200
1300
600
500
400
Room
Temp
Thermal process which heats silicon wafers to ultra-high
temperatures on a timescale of a few seconds.
Used for anneals and oxidation.
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP
Multiple RTP Steps in Advanced Transistors
Source/Drain Anneals
Silicide Anneals
Inter-Layer Dielectric Anneal
High-k Densification Anneal
Fin Implant Anneal
2
3 4
Channel Length
3 2
4
6
5
1
7
Advanced Planar Transistor
Fin
Drain
High-k SiON
Source
5
4 3
6
7
FinFET Transistor
1
2 1
6
5
5
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP
Introducing Applied Vantage Vulcan RTP
6
Revolutionary backside
heating design
Extends Applied’s
technology leadership
in ~$500M market
Source: Gartner Dataquest April ‘11
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP
Challenge #1: Bigger Die Increase the
Within-Die Uniformity Challenge
7
~150 mm2 die 130nm
technology node
graphics chip
~500 mm2 die 40nm
technology node
graphics chip
Source: NVIDIA
Less Margin For Error
External Use
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SILICON SYSTEMS GROUP
Challenge #2: Temperature
Micro-Climates Add Within-Die Variation
8
Dense City
32°C Open Field
25°C
Customers Currently Change
Design Rules to Combat This Effect
External Use
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SILICON SYSTEMS GROUP
Desktop
Mobile
Leak
ag
e C
urr
en
t (m
A)
9
Process Variability Can Result in
Too Many Desktop Chips
Source: 2009 IEEE Keynote, J. Chen, NVIDIA
Graphics
chips are
binned for
different end
markets
Chip Speed (MHz)
1000
100 300 330 360 390 420 450 480
High-End
External Use
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SILICON SYSTEMS GROUP 10
Within-Die Spike Anneal Thermal Variability
With Frontside Heating
FRONTSIDE HEATING
Emitted Energy
Absorbed Energy
Dense City Open Field
~9°C Within-Die
Difference
Magnified Die Substrate
External Use
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SILICON SYSTEMS GROUP 11
3X Decrease in Within-Die Thermal Variability
With Vulcan System’s Backside Heating
Uniform
Absorbed
and Emitted
Energy
BACKSIDE HEATING
Dense City Open Field
<3°C Within-Die
Difference
Magnified Die Substrate
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP
Extreme Test For Within-Die Uniformity
■ Silicon (absorbing)
Poly on Oxide (reflecting)
CHECKERBOARD
WAFER
FRONTSIDE
HEATING
0
50
100
-150 -100 -50 0 50 100 150
Equiv
ale
nt Tem
p C
hange
°C
0
50
100
-150 -100 -50 0 50 100 150
Wafer Diameter (mm)
Equiv
ale
nt Tem
p C
hange °
C
BACKSIDE
HEATING
LINE
TRACE
12
External Use
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SILICON SYSTEMS GROUP
Best-in-Class Dynamic Temperature Control
Proven honeycomb
design with 18 zones
0.1% control
of peak temperature
100 cycles-per-second
multi-zone control
WAFER
POSITION
13
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP 14
Honeycomb
Lamp Array
Pyrometers
Best-in-Class Dynamic Temperature Control
Wafer Levitation
and Rotation
Proven honeycomb
design with 18 zones
0.1% control
of peak temperature
100 cycles-per-second
multi-zone control
External Use
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SILICON SYSTEMS GROUP 15
Thermal Processing Roadmap
Technology Node (nm)
Thermal
Budget
of Anneal
180 130 90 65 45 32 22
VANTAGE RADIANCE
PLUS RTP
SOAK
ANNEAL
5 to 60
sec
<1.5 sec
VANTAGE
VULCAN RTP
~1 sec
Temperature
Control
Range
550°C
1300°C
Enabling 28nm Node and Beyond With Sharper Spikes
and Full-Range Temperature Control
1150°C
200°C
1200°C
75°C
External Use
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SILICON SYSTEMS GROUP 16
Junction Diffusion Depth Must Be Reduced
Without Compromising Activation
Atomic-Level Precision
Required for Ultra-Shallow Junctions
EXTENSION
OVERLAP
JUNCTION
DEPTH
External Use
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SILICON SYSTEMS GROUP
900
1000
1100
Tem
p (
°C)
17
Faster Devices Through
Sharper Temperature Ramp Profiles
Junction
Activation
More
Less
Junction
Depth
Shallower Deeper
Sharper
Temperature
Spikes
Faster
Devices
Vantage Vulcan Nearly
Halves the Spike
Residence Time
Time (s)
800
<1
sec
External Use
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SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP SILICON SYSTEMS GROUP 18
Honeycomb
Lamp Array
Enabling Low-Temperature Regime Control
Closed-loop control from
<75°C
Unique sensors for
accurate, low-temperature
measurement
New capability for
advanced low-temperature
applications
Sensors
Wafer
External Use
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SILICON SYSTEMS GROUP
Industry’s Greenest RTP Solution
CARBON
FOOTPRINT REDUCTION*
Advanced system design improves
usage of grid energy
4 CARS OFF THE ROAD =
* Per system; equivalent to 16 metric tons of CO2/year
19
External Use
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SILICON SYSTEMS GROUP
Applied’s RTP is the Technology and
Marketplace Leader
20 20
RTP is a Growing ~$500M Market Opportunity
Vantage Radiance Plus Vantage Vulcan
Tool of record at
virtually every
top chip maker
In place at
top chip makers
for spike anneal
External Use
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SILICON SYSTEMS GROUP
Applied Vantage Vulcan RTP Continuing RTP Leadership for the Next Decade
21
Best-in-class temperature
uniformity for higher yield
Sharper temperature spikes
for faster chips
Low-temperature control for
new applications
Efficient energy usage for
lower carbon footprint
External Use
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SILICON SYSTEMS GROUP
Applied Vantage Vulcan RTP The Better Side of Anneal
22
External Use
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SILICON SYSTEMS GROUP
