Application of Charge Coupled Devices for Parallel Computing

7/30/2019 Application of Charge Coupled Devices for Parallel Computing

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Application of Charge

Coupled/Injection Devices for Parallel

ComputationsWith the development of new technologies in graphics processing, weather forecasting,

digitalization of resources, space missions data acquisition systems, artificial intelligence and

machine learning, the volume of data has increased considerably. However, there is an

unprecedented gap in the ability of todays computers to process this massive volume of information

Thus there is a need to find fundamentally new algorithms, designed for emerging integrated

systems which are scalable and also deliver better performance. This is where the role of massively

parallel computing units emerge.

Using charge-domain technology, large scale matrix-vector operations can be performed. It employs

arrays of Charge Coupled Device/ Charge Injection Device cells holding an analog matrix of charge,

which can process digital vectors in parallel by means of binary and non-destructive charge transfer

operations.

Schematic diagram of CCD/CID array

Each cell in the array connects to an input column

Line and an output row line by means of a column

gate and a row gate.


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To perform matrix multiplication, for binary input vectors, the column gates serve as binary-analog

multipliers by transferring the matrix charge towards the row gates only if the input bit of the

column indicates a binary one. The charge transferred is summed capacitively on each output row

line, yielding an analog output vector which is the product of binary input vector with analog charge

matrix. The charge sensing at the output is of non-destructive nature, and thus it can be stored in its

original state simply by pushing it back under the column gates.

Advantages of using charge domain technology over other parallel environments(digital CMOS etc)

are:

High Density: The compactness of these cells allows integration of around 100000 on 1 square cm

providing around 100 gigaOPS of computational power.

Low Power Consumption: The entire power consumption is localized at the interface of the array.

The charge stored is conserved because of the non-destructive nature of the cells.

Scalability: CCD/CID array allows to combine together many processors in parallel to form more

effective processing units of higher order.

Impact of CCD/CID cells on the parallel computational complexity

The complexity obtained through this CCD/CID architecture is very different from conventional

parallel computational complexity.

Consider the problem of summing up n scalars using n processors.

By conventional parallel processor architecture:

This can be performed in O(log n) additions by O(n) processors.

By CCD/CID cells:

The summation of N numbers is just the summation ofn charges, which can be performed

simultaneously. This is the pivotal change, which can give new results regarding the computational

parallel complexity using CCD/CID architecures.

Thus the summation ofN scalars can be performed in O(1) addition operations with O(N)processors(CCD/CID cells)

Matrix Vector Multiplication

Similarly, a matrix vector multiplication takes O(logn) additions and O(1) multiplications with

conventional parallel processors architecture.

On the other hand, using CCD/CID architecture, matrix vector multiplication can be performed in

O(1) additions and O(1) multiplications.

It may be noted that the complexity of these operations is independent of the problem size, but it

assumes that the chip size is large enough for the problem provided.


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This drastic change in the computational complexity in matrix vector multiplications can be

attributed to the change in design. However, it must be noted that to output the results, k clock

cycles are needed where k is the required number of bits. The CCD/CID chips are most efficient for

the matrix vector multiplication wherein the matrix is known a priori.

Conclusion

Thus, it can be seen that this CCD/CID hardware technology can give interesting and fundamentally

different results on the complexity of parallel computation. It requires a new framework for the

design and analysis of the parallel algorithms. Since, using the CCD/CID chips many operations can

be performed in O(1), it implies that the computational time is independent of the size of the

problem. This architecture can be used for a variety of application. For eg. To calculate the discrete

Fourier transform and to solve many partial differential equations. Such an architecture can be

employed to aerospace applications, oceanology applications and to compute large-scale matrix

vector multiplication in weather forecasting.

References:

[1] Parallel analog computation with charge coupled devices

Neugebauer, Charles F. (1993)Parallel analog computation with charge coupled

devices.Dissertation (Ph.D.), California Institute of Technology

http://thesis.library.caltech.edu/3303/

[2]Massively Parallel Neurocomputing for Aerospace Applications

-Fijany, A.,Barhen, J.,Toomarian, N.

http://trs-new.jpl.nasa.gov/dspace/handle/2014/35981

- Mukul Gupta

- 260/CO/09

- COE-1
http://thesis.library.caltech.edu/3303/http://thesis.library.caltech.edu/3303/http://trs-new.jpl.nasa.gov/dspace/handle/2014/35981http://trs-new.jpl.nasa.gov/dspace/handle/2014/35981http://trs-new.jpl.nasa.gov/dspace/handle/2014/35981http://thesis.library.caltech.edu/3303/

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Application of Charge Coupled Devices for Parallel Computing