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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 200123M • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 9, 2017 1
APPLICATION NOTE
Suggested PCB Land Pattern Designs for Leaded and Leadless Packages, and Surface-Mount Guidelines for Leadless Packages Introduction This application note provides sample PCB land pattern dimensions for a variety of leaded and leadless packages. These drawings conform with the Surface-Mount Design and Land Pattern Standard (IPC-SM-782) as published by the Institute for Interconnecting and Packaging Electronic Circuits (IPC).
Table 1 lists the land pattern drawings in this document together with their respective figure numbers. These drawings are for reference purposes only. Skyworks recommends contacting the company doing the component mounting and soldering for more information related to actual land patterns (additional dimensions, etc.).
Surface-Mount Guidelines for Leadless Packages Skyworks plastic encapsulated leadless style packages are offered on a number of products to reduce size and weight and to improve application performance. These packages are referred to by such names as Quad Flat No-Lead (QFN), Leadless Plastic Chip Carrier (LPCC), Dual Flat No-Lead (DFN), et. al. All of them conform to JEDEC outline MO-220.
As indicated in Figure 1, leadless packages use perimeter lands on the bottom of the package to provide contact with the PCB. These packages also have an exposed paddle on the bottom to provide a stable ground for optimum electrical performance of switches and attenuators, and an efficient heat path for thermal performance of amplifier products.
Table 1. PCB Land Pattern Drawings Included in This Application Note
Package Type Figure Package Type Figure
LGA 4 SOD-323 20
LGA-8, LGA-315 (4.9 x 3.2 mm) 5 SOIC (8-Lead) 21
LPCC-307 (16-Lead, 4 x 4 mm, Surface-Mount) 6 SOIC (8-Lead, Narrow Body) 22
MSOP-8 7 SOIC (14-Lead, Narrow Body) 23
MSOP-10 8 SOIC (16-Lead, Narrow Body) 24
QFN (12-Lead, 3 x 3 mm) 9 SOIC (16-Lead, Wide Body) 25
QFN (6-Lead) 10 SOIC (28-Lead, Wide Body) 26
QFN (20-Lead, 4 x 4 mm) 11 SOT-5, SOT-6 27
QFN (20-Lead, 4 x 4 mm, 2.1 mm Paddle) 12 SOT-23 (3-Lead) 28
QFN-306 (16-Lead, 4 x 4 mm) 13 SOT-143 29
QFN-310, QFN-364 (32-Lead, 5 x 5 mm, Surface-Mount) 14 SOT-666 30
QFN-349 (8-Lead, 2 x 2 mm) 15 SSOP (8-Lead, 5.3 mm) 31
QFN-350 (16-Lead, 3 x 3 mm) 16 SSOP (16-Lead) 32
SC-70 17 SSOP (20-Lead) 33
SC-70 (6-Lead), SC-88 18 TSSOP (16-Lead, Exposed Pad) 34
SC-79 19 SOD-882 (Small Outline Diode) 35
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 2 August 9, 2017 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200123M
Gold Wire
Lead
Mold Compound
Down Bond
Exposed Die Paddle
DIE
S2265
Figure 1. Package Cross Section
PCB Design Guidelines For a lead/terminal solder pad design, it is recommended to use a Non-Solder Mask Defined (NSMD) approach. However, a small amount of solder mask should remain between the pads to avoid solder bridging between terminals. The PCB land width should match package pad width. The PCB land length should be 0.1 mm greater than the package pad length, with the extra area on the outside of the package (see Figure 7 for example).
The ground pad on the PCB should match the size of the exposed paddle of the package and should be Solder Mask Defined (SMD). The solder mask opening should overlap the edges of the PCB ground pad by 0.065 mm on all four sides. The recommended design gap between the PCB ground pad and land pad is 0.15 mm minimum to avoid solder bridging and shorting. When space is available, a gap of 0.25 mm or more is preferred.
Plated through via holes in the PCB ground pad should be 0.33 mm in diameter and plugged. If via holes cannot be plugged, it is recommended to cap the vias on the backside of the board using solder mask material. This should allow the vias to be filled with solder during reflow.
Solder Mask Design Two types of stencil designs are used for surface-mounted packages:
1. SMD: Solder mask openings are smaller than metal pads.
2. NSMD: Solder mask openings larger than metal pads.
NSMD is recommended for the perimeter I/O land pad, which allows the solder to wrap around the sides of the metal pads on the board for a reliable solder joint.
Because the spacing between the ground pad and the land pads can be small, SMD is recommended for the ground pad to prevent solder bridging.
A stainless steel stencil, 0.125 to 0.150 mm (0.005 to 0.006 in) thick, is recommended for solder paste applications. For better paste release, the aperture walls should be trapezoidal and the corners rounded.
For the terminal land pads, the stencil opening should be 0.05 mm larger than the PCB land pad (0.025 mm in each direction).
For the ground pad area, it is recommended to screen the solder paste in an array of small openings rather than one large opening. The total (cumulative) area of all the openings should be approximately equal to 50 percent of the total ground pad area. This ensures good solder coverage with fewer voids (refer to Figure 2).
Solder Paste and Reflow Profile Since leadless packages have a low stand-off height and small terminal pitch, a no-clean, type 3 solder paste and a convection/IR reflow are recommended.
Sn63 (63 percent Sn and 37 percent Pb) solder is preferred because it is a eutectic compound with a melting point of 183 °C. The reflow temperature in this case would be above 183 °C for 30 to 60 seconds, with a peak temperature of 205 to 210 °C.
A Pb-free alloy may also be used. In the case of Sn/Ag or Sn/Ag/Cu, the melting points would be 221 °C and 217 °C, respectively. In this case, the profile would be above 221/217 °C for 30 to 90 seconds with a peak temperature of 235 to 245 °C. The maximum temperature should not exceed 245 °C.
A typical reflow profile is presented in Figure 3, which could be used as a starting point. The actual profile used depends on the thermal mass of the entire populated board and the solder compound used.
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 200123M • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 9, 2017 3
Multiple Small Stencil Openings(Total Area Approximately 50% of
Total PCB Ground Pad)
PCB GroundPad Boundary Terminal Land
Stencil Opening
S2290
Figure 2. Recommended Stencil Design
Tem
pera
ture
(°C)
250
200
150
100
50
00 60 120 180 240 300
Time (Sec)
Preheat Flux Activation/Thermal Equalization
Reflow CoolDown
2 to 4 Minutes Max.3
MinutesMin.
<2.5°CSec.
30 to 60Sec.
<0.5° to 0.6°C/Sec.
<1.3° to 1.6°C/Sec.
S2291
Figure 3. Typical Solder Reflow Profile
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 4 August 9, 2017 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200123M
S2279Note: Stencil aperture size should be80% to 100% of the pad size on the board
0.43 Typ.
0.36 Typ.
0.30 Typ.
0.40 Typ. Exposed SolderArea 4X
Figure 4. Land Grid Array (LGA)
PackageOutline
2X 1.6752X 0.925
6X 1.000
6X 0.750
4X 1.370
8X 0.800
16X R0.10
Exposed Solder Areas(Hatched Areas)
S2275
Figure 5. LGA-8, LGA-315 (4.9 x 3.2 mm)
Outsideof Package
Footprint of PCB Land =Lead Length +0.1 mm
Lead Width
Lead Length of LPCC
0.013(0.33 mm)
Typ. GND Via
0.063
(1.60 mm)Typ.
0.165(4.20 mm)
0.126(3.20 mm)
0.008(0.20 mm)
0.010(0.25 mm)
0.026 (0.65 mm) 0.020 (0.50 mm)
0.110(2.79 mm)
Sq.
S2267
Figure 6. LPCC-307 (16-Lead, 4 x 4 mm, Surface-Mount)
0.4mm
1.7 mm
2.4 mm
4.1 mm
5.8 mm
0.65mm
S2280
Figure 7. Micro Small Outline Package (MSOP-8)
0.25mm
1.8 mm
3.4 mm
4.4 mm
5.4 mm
0.50mm
S2289
Figure 8. MSOP-10
12X 0.95(To Metal Pads)
Pitch 0.50 1.32 (Sq.)SolderArea
4X Ø0.33Ground Via
See Detail A
Solder Area
0.23
Detail A 12XScale = 48X
0.75
All measurements in millimeters S1748
Figure 9. QFN (12-Lead, 3 x 3 mm)
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 200123M • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 9, 2017 5
6X ExposedSoldering Area
6X 1.325
5X 0.615
6X 0.350
1.220
2X 1.8250.950 Pitch
2X 0.230
0.840
0.230
0.610
All dimensions are in millimeters S2115
Pin 1
Figure 10. QFN (6-Lead)
20 X 1.45
Sq. 2.15(Solder Area)
Pitch 0.50
S2268All dimensions are in millimeters
Figure 11. QFN (20-Lead, 4 x 4 mm)
0.75
See Detail A
ExposedSoldering
Area
Detail A 20XScale = 48X
0.23
S2276
20 X 1.45
All dimensions are in millimeters
Sq. 2.15(Solder Area)
Pitch 0.50
Figure 12. QFN (20-Lead, 4 x 4 mm, 2.1 mm Paddle)
0.75
Exposed Soldering Area0.30
Detail A
16X 1.45(To Metal Pads)
Typ. 0.325
Pitch 0.65
4X Plated Thru Vias
See Detail A
Metal GND Pad (Sq.) 2.15
S2274
Figure 13. QFN-306 (16-Lead, 4 x 4 mm)
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 6 August 9, 2017 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200123M
0.013(0.33 mm)
Typ. GND Via.
0.063(1.60 mm) Typ.
0.020(0.50 mm)
0.020(0.50 mm)
0.122(3.10 mm)
Sq.
0.020 (0.50 mm)
0.020(0.50 mm)
0.013(0.33 mm)
S2269
Figure 14. QFN-310, QFN-364 (32-Lead, 5 x 5 mm, Surface-Mount)
8X 0.66
1.020.51
8X 0.600.28
0.56
9X Exposed Solder Area
8X 0.21
0.25
0.50 Pitch
S2292
Figure 15. QFN-349 (8-Lead, 2 x 2 mm)
0.60
ExposedSoldering
Area
Detail A 16XScale = 48X
0.25
See Detail A 1.70
Metal GND Pad
4X PlatedThru Via
0.25
16X 1.1
0.225 x 45°
1.70
12X 0.50 Pitch
S2278
Figure 16. QFN-350 (16-Lead, 3 x 3 mm)
0.087(2.20 mm)
0.055(1.40 mm)
0.051 (1.30 mm)0.026
(0.65 mm)
0.020 (0.50 mm)
S2293
Figure 17. SC-70
0.65 mm Ref.
0.65 mm Ref.
0.40 mm Ref.
0.75 mmRef.
1.65 mm Ref.
S2295
Figure 18. SC-70 (6-Lead), SC-88
0.014 (0.35 mm) Nom.
0.014(0.35 mm) Nom.
0.053(1.35 mm) Nom.
S2294
Figure 19. SC-79
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 200123M • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 9, 2017 7
0.095 (2.40 mm)
0.035(0.90 mm)
0.030(0.80 mm)
S2296
Figure 20. Small Outline Diode (SOD-323)
5.200 mm
1.270 mm
0.600 mm2.200 mm
S2284
Figure 21. Small Outline Integrated Circuit (SOIC) (8-Lead)
5.200 mm
1.270 mm
0.600 mm2.200 mm
S2266
Figure 22. SOIC (8-Lead, Narrow Body)
2.200mm
0.600 mm1.270 mm
5.200 mm
S2285
Figure 23. SOIC (14-Lead, Narrow Body)
2.200mm
5.200mm
1.270 mm0.600 mm
S2286
Figure 24. SOIC (16-Lead, Narrow Body)
9.2 mm
1.27 mm 0.6 mm
2.2 mm
S2287
Figure 25. SOIC (16-Lead, Wide Body)
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 8 August 9, 2017 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200123M
9.2 mm
1.27 mm 0.6 mm
2.2 mm
S2288
Figure 26. SOIC (28-Lead, Wide Body)
0.70 mm Ref.
3.4 mmRef.
0.95 mm Ref. 0.95 mm Ref.
1.0 mm Ref.2.4 mm
Ref.
S2297
Figure 27. Small Outline Transistor (SOT-5, SOT-6)
0.087(2.20 mm)
0.075(1.90 mm)
0.037(0.95 mm)
0.039(1.00 mm)
0.055(1.40 mm)
S2298
Figure 28. SOT-23 (3-Lead)
0.075 (1.90 mm)
0.039(1.00 mm)
0.031 (0.80 mm)
0.057 (1.44 mm)
0.039 (1.00 mm) Min.0.047 (1.20 mm) Max.
0.067(1.70 mm)
0.087 (2.20 mm)
S2299
Figure 29. SOT-143
0.60
0.28
6X 0.20
6X 0.27
45.00°12X
0.50 Pitch
12X R0.07
6X 0.40
6X ExposedSolderArea
S2277
Figure 30. SOT-666
5.0 mm
7.2 mm
9.4 mm
2.2 mm0.40mm
0.65mm
S2281
Figure 31. Small Shrink Outline Package (SSOP) (8-Lead, 5.3 mm)
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 200123M • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 9, 2017 9
16X 2.20
0.635 Pitch
16X 1.00
16X 0.25
0.3175
ExposedSoldering
Area
S2270
Figure 32. SSOP (16-Lead)
20X 1.20
20X 0.40
20X 2.90
0.325
ExposedSoldering
Area
Pitch 0.65
S2271
Figure 33. SSOP (20-Lead)
16X 2.40
0.65 Pitch
ExposedSoldering
Area
0.325
16X 0.32
16X 1.05
S2282
Figure 34. Think Shrink Small Outline Package (TSSOP) (16-Lead, Exposed Pad)
0.475
0.350
0.475
PCB Solder Mask Opening
1.200
0.750
0.650
Device Outline
PCB Pad Metallization 2X
Figure 35. Small Outline Diode (SOD-882)
200123-036
Figure 36. -219 Package (Version A)
200123-037
Figure 37. -219 Package (Version B)
APPLICATION NOTE • LEADED/LEADLESS LAND PATTERN DESIGNS AND DESIGN GUIDELINES FOR LEADLESS PACKAGES
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 10 August 9, 2017 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200123M
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