Appendix 6 Copy

8/12/2019 Appendix 6 Copy

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FPGA IMPLEMENTATION OF /4 -QPSK MODEM FOR EXAMINATION BLOCKS ALLOCATION SYSTEM.

Dept of.ECE, PDA Engineering Collge Gulbarga . 2013-14 73

APPENDIX

1. CREATING AN FPGA DESIGNBegin this tutorial by creating a new Quartus II project. A project is a set of files that

maintain information about your FPGA design. The Quartus II Settings File (.qsf) and

Quartus II Project File (.qpf) files are the primary files in a Quartus II project. To compile a

design or make pin assignments, you must first create a project.

THE STEPS USED TO CREATE A PROJECT ARE1. In the Quartus II software, select File > New Project Wizard. The Introduction page

opens, as shown in Figure 1

Figure 1 New Project Wizard introduction

2. Click Next.3. Enter the following information about your project: (Note: File names, project names,

and directories in the Quartus II software cannot contain spaces.)


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a. What is the working directory for this project? Enter a directory in which you will storeyour Quartus II project files for this design. For example,

E:\My_design\my_first_fpga.

b. What is the name of this project? Type my_first_fpga.c. What is the name of the top-level design entity for this project? Type my_first_fpga.

See Figure 2.

Figure 2 Project information

d. Click Next.e. In the next dialog box, you will assign a specific FPGA device to the design. Select the

EP4CE22F17C6 device, as it is the FPGA on the DE0-Nano, as shown in Figure 3

f. Click Finish.4. When prompted, select Yes to create the my_first_fpga project directory. You just

created your Quartus II FPGA project. Your project is now open in Quartus II, as shown

in Figure 4


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Figure 3 Specify the Device Example

Figure 4 My_First_FPGA Project


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2 EXPANSION PIN HEADERS OF ALTERA CYCLONE IVFPGA

The DE0-Nano board provides TWO 40-PIN expansion headers. Each header

connects directly to 36 pins of the Cyclone IV E FPGA, and also provides DC +5V (VCC5),DC +3.3V (VCC33), and two GND pins.

Figure 5.Pin1 locations of the GPIO expansion headers

Figure 6 Pin arrangement of the GPIO expansion headers


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3. BIT ERROR RATEIn digital transmission, the number of bit errors is the number of received bits of

a data stream over a communication channel that have been altered due

to noise, interference, distortion or bit synchronization errors.

The bit error rateor bit error ratio(BER) is the number of bit errors divided by

the total number of transferred bits during a studied time interval. BER is a unitless

performance measure, often expressed as a percentage.

The bit error probabilitypeis the expectation value of the BER. The BER can be

considered as an approximate estimate of the bit error probability. This estimate is accurate

for a long time interval and a high number of bit errors.

Bit-error rate curves for BPSK, QPSK, 8-PSK and 16-PSK, AWGN channel is show in the

figure 7

Figure 7Bit-error rate curves for BPSK, QPSK, 8-PSK and 16-PSK, AWGN channel

Figure 8 BER comparisons between BPSK and differentially encoded BPSK with gray-coding


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BER comparison between BPSK and differentially encoded BPSK with gray-coding

operating in white noise is show in the above figure 8.2

4. CHANNEL CAPACITYLike all M-ary modulation schemes with M = 2

b

symbols, when given exclusiveaccess to a fixed bandwidth, the channel capacity of any phase shift keying modulation

scheme rises to a maximum of bbits per symbol as the signal-to-noise ratio increases.

Figure 9 Bits per Symbol as the signal-to-noise ratio increases

Above figure 9 Gives the clear idea on the fixed bandwidth, channel capacity vs. SNR

for some common modulation schemes

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