api.ning.comapi.ning.com/files/rEucCERnfozC9z6qsZqc2JrR7o0iLvlo1... · Web viewCS302 Final Exam (Fall 2009) Time 2 Hours Total questions 41 Objective questions 31 Subjective question

CS302 Final Exam (Fall 2009)

Time 2 Hours

Total questions 41

Objective questions 31Subjective question 10

Question (Marks 1)The group of bits 10111 is serially shifted (right-most bit first) into an 5-bit parallel output shift register with an initial state 01110. What will be the contents of register after three clock pulses the register contains?

Question (Marks 1)How clock skew is eliminated?

Question (Marks 2)Give the circuit diagram of the Gated SR Latch.

Question (Marks 2)How erase operation works in context to Flash memory?

Question (Marks 3)How the frequency of an unknown signal is calculated?

Question (Marks 3)

Given the statement in PLD programming;

Y PIN 23 ISTYPE ‘COM’;

Explain what does this statement mean?

Question: 38 (Marks 5)Flash analogue to digital converter

Question: 39 (Marks 5)How 12(1100) is detected by the third NAND Gate?Why clock signal is added to all the three gates?

Question: 40 (Marks 10)The One-Shot is triggered by applying a short pulse at the input of the NOR gateat time interval t1. The One-Shot is in its stable state with output at logic zero at timeinterval < t1. The logic high triggering pulse at the input of the NOR gate sets its output tologic low.Give step wise working of One-Shot Mono-stable multi-vibrator after triggering pulse is applied.

Question: 41 (Marks 10)Give pin names of 4-bit Synchronous Counter 74HC163

Question No: 1 ( Marks: 1 ) - Please choose one

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

► FALSE ► TRUE


The output of an XNOR gate is 1 when ____________

I) All the inputs are zeroII) Any of the inputs is zeroIII) Any of the inputs is oneIV) All the inputs are one ► I Only ► IV Only ► I and IV only ► II and III only Question No: 3 ( Marks: 1 ) - Please choose one

NAND gate is formed by connecting _________

► AND Gate and then NOT Gate ► NOT Gate and then AND Gate ► AND Gate and then OR Gate ► OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one

Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

► Zero ► One ► Undefined ► No output as input is invalid Question No: 5 ( Marks: 1 ) - Please choose one

The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________

► Radiation-Erase programming method (REPM) ► In-System Programming (ISP) ► In-chip Programming (ICP) ► Electronically-Erase programming method(EEPM) Question No: 6 ( Marks: 1 ) - Please choose one

The ABEL symbol for “OR” operation is

► ! ► & ► # ► $ Question No: 7 ( Marks: 1 ) - Please choose one

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop ► 0 ► 1 ► Invalid ► Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________ ► Doesn’t have an invalid state ► Sets to clear when both J = 0 and K = 0 ► It does not show transition on change in pulse ► It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one

For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________ ► 0 ► 1 ► Q(t) ► Invalid Question No: 10 ( Marks: 1 ) - Please choose one

In asynchronous digital systems all the circuits change their state with respect to a common clock ► True ► False Question No: 11 ( Marks: 1 ) - Please choose one

A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock ► High-to-low transition of clock ► Enable input (EN) is set ► Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one

___________ is one of the examples of asynchronous inputs.

► J-K input ► S-R input ► D input ► Clear Input (CLR) Question No: 13 ( Marks: 1 ) - Please choose one

The _____________ input overrides the ________ input ► Asynchronous, synchronous ► Synchronous, asynchronous ► Preset input (PRE), Clear input (CLR) ► Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one

Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.

► AND ► NAND ► NOR ► XNOR Question No: 15 ( Marks: 1 ) - Please choose one

In ________ outputs depend only on the combination of current state and inputs.

► Mealy machine ► Moore Machine ► State Reduction table ► State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one

________ is used to simplify the circuit that determines the next state. ► State diagram ► Next state table

► State reduction ► State assignment Question No: 17 ( Marks: 1 ) - Please choose one

A multiplexer with a register circuit converts _________

► Serial data to parallel ► Parallel data to serial ► Serial data to serial ► Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one

In asynchronous transmission when the transmission line is idle, _________

► It is set to logic low ► It is set to logic high ► Remains in previous state ► State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one

In the following statement Z PIN 20 ISTYPE ‘reg.invert’;The keyword “reg.invert” indicates ________

► An inverted register input ► An inverted register input at pin 20 ► Active-high Registered Mode output ► Active-low Registered Mode output Question No: 20 ( Marks: 1 ) - Please choose one

A Nibble consists of _____ bits

► 2

► 4 ► 8 ► 16 Question No: 21 ( Marks: 1 ) - Please choose one

The output of this circuit is always ________.

► 1 ► 0 ► A ► Question No: 22 ( Marks: 1 ) - Please choose one

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?

► 2 ► 4 ► 6 ► 8 Question No: 23 ( Marks: 1 ) - Please choose one

A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.


The high density FLASH memory cell is implemented using ______________

► 1 floating-gate MOS transistor ► 2 floating-gate MOS transistors ► 4 floating-gate MOS transistors ► 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one

In order to synchronize two devices that consume and produce data at different rates, we can use _________

► Read Only Memory ► Fist In First Out Memory ► Flash Memory ► Fast Page Access Mode Memory Question No: 26 ( Marks: 1 ) - Please choose one

If the FIFO Memory output is already filled with data then ________

► It is locked; no data is allowed to enter ► It is not locked; the new data overwrites the previous data. ► Previous data is swapped out of memory and new data enters ► None of given options Question No: 27 ( Marks: 1 ) - Please choose one

The process of converting the analogue signal into a digital representation (code) is known as ___________

► Strobing ► Amplification ► Quantization ► Digitization Question No: 28 ( Marks: 1 ) - Please choose one

Above is the circuit diagram of _______.

► Asynchronous up-counter ► Asynchronous down-counter

► Synchronous up-counter ► Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one

is an example of ______________

► Product of sum form

► Sum of product form ► Demorgans law ► Associative law Question No: 30 ( Marks: 1 ) - Please choose one

Q2 :=Q1 OR X OR Q3The above ABEL expression will be

► Q2:= Q1 $ X $ Q3

► Q2:= Q1 # X # Q3

► Q2:= Q1 & X & Q3

► Q2:= Q1 ! X ! Q3

Question No: 31 ( Marks: 1 )

How the “hour counter” is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)? Question No: 32 ( Marks: 1 )

The top of the stack contains the value “5” and bottom of the stack contains the value “6”, a pop (read data from stack) operation was executed, which value would be read?


What kind of devices use the shift register based First In First Out (FIFO) memory?

Ans:


Differentiate between positive-edge triggered flip-flop and negative edge-triggered flip-flop.


Name some of the important operating characteristics of flip-flops


Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans:Question No: 38 ( Marks: 5 )

Explain Flash Analogue-to Digital Converter.


Explain the next-state table with the help of a table for any sequential circuit.


Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of “PRE” and “CLR” inputs on flip-flops.


Explain the following in context of Memory:

Address signalsData signals

CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one

The output of an AND gate is one when _______

► All of the inputs are one ► Any of the input is one ► Any of the input is zero ► All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one

The OR Gate performs a Boolean _______ function

► Addition ► Subtraction ► Multiplication ► Division Question No: 3 ( Marks: 1 ) - Please choose one

A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.

► True ► False Question No: 4 ( Marks: 1 ) - Please choose one

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

► A > B = 1, A < B = 0, A < B = 1 ► A > B = 0, A < B = 1, A = B = 0 ► A > B = 1, A < B = 0, A = B = 0 ► A > B = 0, A < B = 1, A = B = 1 Question No: 5 ( Marks: 1 ) - Please choose one

NOTGatelevel

OR Gatelevel

ANDGatelevel

The diagram above shows the general implementation of _____ form ► boolean ► arbitrary ► POS ► SOP Question No: 6 ( Marks: 1 ) - Please choose one

The device shown here is most likely a

► Comparator ► Multiplexer ► Demultiplexer ► Parity generator Question No: 7 ( Marks: 1 ) - Please choose one

Demultiplexer converts _______ data to __________ data

► Parallel data, serial data ► Serial data, parallel data ► Encoded data, decoded data ► All of the given options.


Flip flops are also called _____________ ► Bi-stable dualvibrators ► Bi-stable transformer ► Bi-stable multivibrators ► Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one

If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop ► 0 ► 1 ► Invalid ► Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop ► 0 ► 1 ► Invalid ► Input is invalid Question No: 11 ( Marks: 1 ) - Please choose one

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________ ► Doesn’t have an invalid state ► Sets to clear when both J = 0 and K = 0 ► It does not show transition on change in pulse ► It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

► Set-up time

► Hold time ► Pulse Interval time ► Pulse Stability time (PST)


We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________

► Using S-R Flop-Flop ► D-flipflop ► J-K flip-flop ► T-Flip-Flop Question No: 14 ( Marks: 1 ) - Please choose one



A negative edge-triggered flip-flop changes its state when ________________ ► Enable input (EN) is set ► Preset input (PRE) is set ► Low-to-high transition of clock ► High-to-low transition of clock Question No: 17 ( Marks: 1 ) - Please choose one

A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

► 10 mW

► 25 mW

► 64 mW

► 1024


__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. ► Race condition ► Clock Skew ► Ripple Effect ► None of given options Question No: 19 ( Marks: 1 ) - Please choose one

A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status. ► 3

► 7

► 8 ► 15


A divide-by-50 counter divides the input ______ signal to a 1 Hz signal. ► 10 Hz ► 50 Hz ► 100 Hz ► 500 Hz Question No: 21 ( Marks: 1 ) - Please choose one

The design and implementation of synchronous counters start from _________

► Truth table

► k-map ► state table ► state diagram Question No: 22 ( Marks: 1 ) - Please choose one

A synchronous decade counter will have _______ flip-flops ► 3

► 4 ► 7

► 10


The output of this circuit is always ________.

► 1 ► 0 ► A ► Question No: 24 ( Marks: 1 ) - Please choose one

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?


In _______ the output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. ► Moore machine ► Meally machine ► Johnson counter ► Ring counter Question No: 26 ( Marks: 1 ) - Please choose one

In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register.

► Moore machine

► Meally machine ► Johnson counter ► Ring counter Question No: 27 ( Marks: 1 ) - Please choose one

Which is not characteristic of a shift register?

► Serial in/parallel in ► Serial in/parallel out ► Parallel in/serial out ► Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)


The _________ of a ROM is the time it takes for the data to appear at the DataOutput of the ROM chip after an address is applied at the address input lines

► Write Time ► Recycle Time ► Refresh Time ► Access Time Question No: 30 ( Marks: 1 ) - Please choose one

The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2) ► 2n (n multiplied by 2) ► 2n (2 raise to power n) ► n2 (n raise to power 2) Question No: 31 ( Marks: 1 )

In the statement "X PIN 22 ISTYPE ‘reg.buffer"What is the meaning of the keyword “reg.buffer”


What are the two basic operations which are performed on memory?


Explain state assignment process. Question No: 34 ( Marks: 2 )

What is RAM Stack, which register stores the address of the top of the stack?


How can we calculate the frequency of an unknown signal? Question No: 36 ( Marks: 3 )

Explain dynamic RAM in your own words. Question No: 37 ( Marks: 3 )

Suppose a 2 bit up-down counter having states “A, B, C, D”. the counter counts upward when X=1 and downward when X=0. Write down IF-THEN-ELSE statements to show how present states change to next states and previous states. Question No: 38 ( Marks: 5 )

Explain memory read operation with the help of an example.


Draw the next-state table of any sequential counter with the help of J-K flip flop transition Question No: 40 ( Marks: 10 )

You are given the diagram of up-down counter; explain how it works as an up and down counter.


Consider a state sequence a, b, c, f, d, d, c, f, d, c, a, f, d, c. Starting from initial state a, draw a table for the inputs and outputs for the state diagram given below (up to first ten transitions).


Caveman number system is Base ______ number system


The output of an XOR gate is zero (0) when __________I) All the inputs are zeroII) Any of the inputs is zeroIII) Any of the inputs is oneIV) All the inputs are one ► I Only ► IV Only ► I and IV only ► II and III only Question No: 3 ( Marks: 1 ) - Please choose one

The decimal “17” in BCD will be represented as _________10001(right opt is not given)


A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.


The simplest and most commonly used Decoders are the ______ Decoders

► n to 2n ► (n-1) to 2n

► (n-1) to (2n-1) ► n to 2n-1


The _______ Encoder is used as a keypad encoder.

► 2-to-8 encoder ► 4-to-16 encoder ► BCD-to-Decimal ► Decimal-to-BCD Priority Question No: 7 ( Marks: 1 ) - Please choose one

3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions


If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop ► 0 ► 1 ► Invalid ► Input is invalid Question No: 9 ( Marks: 1 ) - Please choose one

If the S and R inputs of the gated S-R latch are connected together using a ______ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) ► AND ► OR ► NOT ► XOR Question No: 10 ( Marks: 1 ) - Please choose one


The low to high or high to low transition of the clock is considered to be a(n) ________ ► State ► Edge

► Trigger ► One-shot Question No: 12 ( Marks: 1 ) - Please choose one


RCO Stands for _________

► Reconfiguration Counter Output

► Reconfiguration Clock Output

► Ripple Counter Output

► Ripple Clock Output


Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state

► Ten ► Eight ► Three ► Two Question No: 15 ( Marks: 1 ) - Please choose one

___________ is one of the examples of asynchronous inputs. ► J-K input ► S-R input ► D input ► Clear Input (CLR) Question No: 16 ( Marks: 1 ) - Please choose one

__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. ► Race condition

► Clock Skew ► Ripple Effect ► None of given options Question No: 17 ( Marks: 1 ) - Please choose one

A transparent mode means _____________

► The changes in the data at the inputs of the latch are seen at the output ► The changes in the data at the inputs of the latch are not seen at the output ► Propagation Delay is zero (Output is immediately changed when clock signal is applied) ► Input Hold time is zero (no need to maintain input after clock transition) Question No: 18 ( Marks: 1 ) - Please choose one

In ________ outputs depend only on the current state.

► Mealy machine ► Moore Machine ► State Reduction table ► State Assignment table Question No: 19 ( Marks: 1 ) - Please choose one

The alternate solution for a multiplexer and a register circuit is _________

► Parallel in / Serial out shift register ► Serial in / Parallel out shift register ► Parallel in / Parallel out shift register ► Serial in / Serial Out shift register Question No: 20 ( Marks: 1 ) - Please choose one

The alternate solution for a demultiplexer-register combination circuit is _________

► Parallel in / Serial out shift register ► Serial in / Parallel out shift register ► Parallel in / Parallel out shift register ► Serial in / Serial Out shift register


In asynchronous transmission when the transmission line is idle, _________

► It is set to logic low ► It is set to logic high ► Remains in previous state ► State of transmission line is not used to start transmission Question No: 22 ( Marks: 1 ) - Please choose one

Smallest unit of binary data is a ________

► Bit ► Nibble ► Byte ► Word Question No: 23 ( Marks: 1 ) - Please choose one

A Nibble consists of _____ bits

► 2

► 4 ► 8 ► 16 Question No: 24 ( Marks: 1 ) - Please choose one

A GAL is essentially a ________. ► Non-reprogrammable PAL ► PAL that is programmed only by the manufacturer

► Very large PAL ► Reprogrammable PAL Question No: 25 ( Marks: 1 ) - Please choose one

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. ► 1 ► 2 ► 4 ► 8


DRAM stands for __________

► Dynamic RAM ► Data RAM ► Demoduler RAM ► None of given options Question No: 27 ( Marks: 1 ) - Please choose one

FIFO is an acronym for __________

► First In, First Out ► Fly in, Fly Out ► Fast in, Fast Out ► None of given options Question No: 28 ( Marks: 1 ) - Please choose one

In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by which gate?

► AND ► OR ► NAND ► XNOR Question No: 29 ( Marks: 1 ) - Please choose one

The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2) ► 2n (n multiplied by 2) ► 2n (2 raise to power n) ► n2 (n raise to power 2) Question No: 30 ( Marks: 1 ) - Please choose one

Stack is an acronym for _________

► FIFO memory ► LIFO memory ► Flash Memory ► Bust Flash Memory Question No: 31 ( Marks: 1 )

Generally two types of D/A Converters are used. Name at least one.

One type of D/A converter is electromechanical-also called shaft- or position-to-digital-and electronic.


Name at least one device that converts signals form analog to digital or from digital to analogue.

A codec (coder/decoder) is a device that converts an analog signal into a digital signal.Mobile phone converts signals from digital to analogue and from analogue to digital.


How glitches due to race condition can be avoided?

A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 μm CMOS gate array ASICs, designed using VINYAS CAD tools.


For a four bit serial in/serial out shift register is initially set to “0000”. We want to enter the value “1111”. How many clock pulses will be required to enter the data and then again bring the contents of register to “0000”.

After 8 clock pulses the 4-bit data is completely shifted out of the shift register.The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right Question No: 35 ( Marks: 3 )

Define down counter.

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Down counters, are those which decrease (decrement) in value.Decrement the counter by one (if it's already zero, this leaves it unchanged) Question No: 36 ( Marks: 3 )

Explain Rotate Left Operation with the help of diagram.The serial output of the register is connected to the serial input of the register. Byapplying clock pulses data is shifted left. The data shifted out of the serial out pin at the left hand side is re-circulated back into the shift register input at the right hand side. Thus the data is rotated left within the register.


Explain dynamic RAM in your own words.

DRAM

Dynamic RAM (DRAM) is a type of RAM that contains a single transistor and a capacitor. DRAM is smaller than SRAM, and therefore can store more data in a smaller area. Because of the charge and discharge times of the capacitor, however, DRAM tends to be slower than SRAM. Many modern types of Main Memory are based on DRAM design because of the high memory densities. Because DRAM is simpler than SRAM, it is typically cheaper to produce.A popular type of RAM, SDRAM, is a variant of DRAM and is not related to SRAM.As digital circuits continue to grow smaller and faster as per Moore's Law, the speed of DRAM is not increasing as rapidly. This means that as time goes on, the speed difference between the processor and the RAM units (so long as the RAM is based on DRAM or variants) will continue to increase, and communications between the two units becomes more inefficient.


Explain memory write operation with the help of an example.

Memory write operation:

The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

A diagnostic memory write operation uses the same CSRs as the read. The data is written to the CSR data register, and the address at which the data is to be stored is written to the CSR diagnostic address register.


Convert the following state diagram into state table

Present state Next statQ2 Q1 Q0 Q2 Q1 Q00 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0


Given below is the circuit diagram of parallel in / serial out shift register. Explain how this circuit works (serially shifts the data)

Q

QSET

CLR

D

flip-flop 1

CLKQ

QSET

CLR

D

flip-flop 2Q

QSET

CLR

D

flip-flop 3Q

QSET

CLR

D

flip-flop 4

D0 D1 D2

Q3

SerialDataOut

1 2 1 2 1 2

D3

Q0 Q1 Q2

LOAD/SHIFT


Briefly explain address multiplexing in DRAM.

Documents

api.ning.comapi.ning.com/files/rEucCERnfozC9z6qsZqc2JrR7o0iLvlo1... · Web viewCS302 Final Exam (Fall 2009) Time 2 Hours Total questions 41 Objective questions 31 Subjective question