APB4 Multiplexer Datasheet - Roa Logic · The Roa Logic APB4 Multiplexer is a fully configurable interconnect IP to enable an APB4 Master to communicate with multiple APB4 slaves

APB4Multiplexer

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APB4MultiplexerDatasheet

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IntroductionTheAMBAAPBv2.0 bus protocol – commonly referred to as APB4 – defines alow-cost interface that is optimized for minimal power consumption andreduced interface complexity.Toenablea singleAPB4Master to communicatewith multiple APB4 Slaves (Peripherals) via a common bus, certain signalsrequiremultiplexing–theRoaLogicAPB4Multiplexer isa fullyconfigurable&parameterizedIPtoprovidethisfunctionalityasshownbelow:

Figure1:APB4MultiplexerExample

Features

• FullsupportforAPBversion2.0(APB4)protocol• FullyparameterizedIPwith:

o UserConfigurablenumberofperipheralssupportedo UserConfigurableaddressanddatawidths

• Supportforuserdefinedaddressmappingperperipheral

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TableofContentsIntroduction...........................................................................................................2Features..................................................................................................................................................................21 GettingStarted.................................................................................................41.1 Deliverables..............................................................................................................................................41.2 Runningthetestbench.........................................................................................................................41.2.1 Self-checkingtestbench...................................................................................................................51.2.2 Makefilesetup......................................................................................................................................51.2.3 Makefilebackup..................................................................................................................................51.2.4 NoMakefile...........................................................................................................................................5

2 Specifications....................................................................................................62.1 FunctionalDescription.........................................................................................................................62.2 MasterInterface......................................................................................................................................62.3 SlaveInterfaces........................................................................................................................................6

3 Configurations..................................................................................................83.1 Introduction..............................................................................................................................................83.1.1 SLAVES....................................................................................................................................................83.1.2 PADDR_SIZE..........................................................................................................................................83.1.1 PDATA_SIZE..........................................................................................................................................8

4 Interfaces..........................................................................................................94.1 GlobalSignals...........................................................................................................................................94.1.1 PRESETn.................................................................................................................................................94.1.2 PCLK.........................................................................................................................................................9

4.2 MasterInterface......................................................................................................................................94.2.1 MST_PSEL..............................................................................................................................................94.2.2 MST_PADDR..........................................................................................................................................94.2.3 MST_PRDATA.....................................................................................................................................104.2.4 MST_PREADY.....................................................................................................................................104.2.5 MST_PSLVERR....................................................................................................................................10

4.3 SlaveInterface.......................................................................................................................................104.3.1 SLV_PSEL[n]........................................................................................................................................104.3.2 SLV_PRDATA[n]................................................................................................................................104.3.3 SLV_PREADY[n].................................................................................................................................114.3.4 SLV_PSLVERR[n]...............................................................................................................................114.3.5 slv_addr[n]andslv_mask[n]........................................................................................................11

5 Resources.......................................................................................................12

6 RevisionHistory..............................................................................................13

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1 GettingStarted1.1 DeliverablesAll IP isdeliveredasazipped tarball,whichcanbeunzippedwithall commoncompressiontools(likeunzip,winrar,tar,…).

Thetarballcontainsadirectorystructureasoutlinedbelow:

The doc directory contains relevant documents likeuserguides,applicationnotes,anddatasheets.

The rtl directory contains the actual IP design files.Depending on the license agreement the APB4Multiplexer is delivered as either encrypted Verilog-HDLorasplainSystemVerilogsourcefiles.Encryptedfiles have the extension “.enc.sv”, plain source fileshave the extension “.sv”. The files are encryptionaccording to the IEEE-P1735 encryption standard.Encryption keys for Mentor Graphics (Modelsim,Questasim, Precision), Synplicity (Synplify, Synplify-Pro), and Aldec (Active-HDL, Riviera-Pro) areprovided.As such there shouldbeno issue targetinganyexistingFPGAtechnology.

If anyother synthesis or analysis tool is used then aplainsourceRTLdeliverymaybeneeded.Aseparatelicense agreement and NDA is required for such adelivery.

The bench directory contains the (encrypted) sourcefilesforthetestbench.

Thesimdirectorycontainsthefiles/structuretorunthesimulations. Section 1.2 ‘Running the testbench’providesforinstructionsonhowtousethemakefile.

1.2 Runningthetestbench

TheAPB4MultiplexerIPcomeswithadedicatedtestbenchthattestsallfeaturesofthedesignandfinallyrunsafullrandomtest.ThetestbenchisstartedfromaMakefilethatisprovidedwiththeIP.

The Makefile is located in the <install_dir>/sim/rtlsim/run directory. TheMakefile supports most commonly used simulators; Modelsim/Questasim,Cadencencsim,AldecRiviera,andSynopsysVCS.

To start the simulation, enter the <install_dir>/sim/rtlsim/run directory andtype: make <simulator>. Where simulator is any of: msim (for

doc

rtl

verilog

sim

rtlsim

bin

run

bench

verilog

Figure1-1:IPDirectoryStructure

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modelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec Riviera-Pro), or vcs (for Synopsys VCS). For example typemake msim to start thetestbenchinModelsim/Questasim.

1.2.1 Self-checkingtestbench

The testbenches is a self-checking testbench intended tobe executed from thecommand line. There is no need for a GUI or a waveform viewer. Once thetestbenchcompletesitdisplaysasummaryandclosesthesimulator.

1.2.2 Makefilesetup

The simulator is executed in its associated directory. Inside this directory isanotherMakefilethatcontainssimulatorspecificcommandstostartandexecutethe simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correctdirectoryandcallsthesimulatorspecificMakefile.

For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msimdirectory. Typingmakemsim loads themainMakefile,which then enters themsimsub-directoryandcallsitsMakefile. ThisMakefilecontainscommandstocompile the RTL and testbench sources with Modelsim, start the Modelsimsimulator,andrunthesimulation.

1.2.3 Makefilebackup

The <install_dir>/sim/rtlsim/bin directory contains backups of the originalMakefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletelycleantherundirectory.Usethebackupstorestoretheoriginalsetup.

1.2.4 NoMakefile

For users unfamiliar with Makefiles or those on systems that do not nativelysupport make (e.g. Windows) a run.do file is provided that can be used withModelsim/QuestasimandRiviera-Pro.

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2 Specifications2.1 FunctionalDescriptionTheRoaLogicAPB4Multiplexerisahighlyconfigurable,fullyparameterizedsoftIP to enable a singleAPB4basedMaster (Host) to communicatewithmultipleAPB4 Slaves (Peripherals). It is fully compliant with the AMBA APB v2.0 busprotocols.

TheIPcontainsasingleMasterInterfacetoconnecttotheAPB4Hostandauserdefinednumberof Slave Interfacesas shown inError! Reference source notfound.

Themultiplexerfunctionsasfollows:

• TransactionsontheAPB4BusaredecodedbymatchingaddressesontheAPB4addressbustoanaddressmapdefinedbytheslv_addr[n]andslv_mask[n]inputsofthemultiplexer(Seesection4.3.5)

• CommunicationwithaperipheralisenabledbyassertingtheappropriateSLV_PSEL[n]outputsignalbasedontheaddressmapping(Seesection4.3.1)

• Peripheral-specific control signals SLV_PSLVERR[n]andSLV_READY[n], together with the Read Data Bus signalsSLV_PRDATA[n]duringareadtransaction,arethenmultiplexedbacktotheMasterInterface.

2.2 MasterInterface

TheAPB4MultiplexerMasterInterfaceconsistsofthefollowingsubsetofAPB4bussignals:

• PADDRandPSELinputstoenableaddressspacedecoding• PREADYandPSLVERRoutputsderivedfromtheselectedperipheral• PRDATA read data bus output derived from the selected peripheral

duringareadtransaction

AllotherAPB4bussignalsareconnecteddirectlytoeachperipheral

2.3 SlaveInterfacesTheAPB4Multiplexergeneratesauser-definednumber(‘n’)ofSlaveInterfacesthatconsistofthefollowingsubsetofAPB4bussignals:

• PSEL[n] outputs used to select an individual peripheral during atransaction

• PREADY[n] and PSLVERR[n] control signal inputs from eachperipheralwhicharemultiplexedasoutputsontheMasterInterface

Paul Hardy� 26/4/2017 10:47Deleted: Figure2-1:APB4MultiplexerSignaling

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• PRDATA[n] read data bus inputs from each peripheral which ismultiplexedtotheMasterInterface

2.4 AddressSpaceConfigurationEach Slave Port has an Address Base (slv_addr[n]) and Address Mask(slv_mask[n]) port. Together these set the address range covered by eachSlavePort.(Seesection4.3.5)

WhiletheAddressBaseandAddressMaskvaluesmaybechangeddynamically,assigningstaticvaluesaccordingtoapredefinedaddressmapistypical.

Table2-1:APB4MultiplexerSignaling

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3 Configurations3.1 IntroductionTheRoaLogicAPB4MultiplexerisafullyconfigurableinterconnectIPtoenablean APB4Master to communicate with multiple APB4 slaves (i.e. peripherals).Thecoreparametersandconfigurationoptionsaredescribedbelow.

Parameter Type Default DescriptionSLAVES Integer 8 Numberofattachedslaves(peripherals)PADDR_SIZE Integer 8 AddressBusWidthPDATA_SIZE Integer 8 ReadDataBusWidth

Table3-1:CoreParameters

3.1.1 SLAVES

The SLAVES parameter specifies the number of slaves (i.e. peripherals) theAPB4Multiplexerwillsupport.

3.1.2 PADDR_SIZE

ThePADDR_SIZEparameterspecifiesthewidthoftheaddressbusfortheAPB4Interfaces. The Master and all peripherals sharing the APB4 Multiplexer areexpectedtohavethesameaddresswidth.

3.1.1 PDATA_SIZE

The PDATA_SIZE parameter specifies the width of the APB4 data bus. Thisparameter must equal an integer multiple of bytes. The Master and allperipherals sharing the APB4Multiplexer are expected to have the same datawidth.

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4 Interfaces4.1 GlobalSignalsThefollowingcommonsignalsaresharedbetweenalldevicesontheAPB4bus.

Port Size Direction DescriptionPRESETn 1 Input AsynchronousactivelowresetPCLK 1 Input ClockInput

Table4-1:GlobalSignals

4.1.1 PRESETn

When the active low asynchronousPRESETn input is asserted (‘0’), the APB4interfaceisputintoitsinitialresetstate.

4.1.2 PCLK

PCLKistheAPB4interfacesystemclock.AllinternallogicfortheAPB4interfaceoperatesattherisingedgeofthissystemclockandAPB4bustimingsarerelatedtotherisingedgeofPCLK.

4.2 MasterInterface

TheAPB4InterfacedecodesthesignalingofanAPB4busmasterandthereforeimplementsasubsetofaregularAPB4SlaveInterface.

Port Size Direction DescriptionMST_PSEL 1 Input PeripheralSelectMST_PADDR PADDR_SIZE Input AddressBusMST_PRDATA PDATA_SIZE Output ReadDataBusMST_PREADY 1 Output TransferReadyMST_PSLVERR 1 Output TransferErrorIndicator

Table4-2:APB4MasterInterfacePorts

4.2.1 MST_PSEL

TheAPB4MastergeneratesPSEL, tosignal toanattachedperipheral that it isselectedandadatatransferispending.ThissignaldrivestheAPB4MultiplexerMST_PSELportand isdecodedtoselect the individualperipheralbyassertingthecorrespondingSLV_PSEL[n]output..

4.2.2 MST_PADDR

MST_PADDR is the APB4 address bus. The bus width is defined by thePADDR_SIZEparameterandisdrivenbytheAPB4Master.

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4.2.3 MST_PRDATA

MST_PRDATAdrivestheAPB4readdatabus.Theselectedperipheraldrivesthisbusduringreadcycles,viatheAPB4Multiplexer.

The bus width must be byte-aligned and is defined by the PDATA_SIZEparameter.

4.2.4 MST_PREADY

MST_PREADYisdrivenbytheselectedperipheralviatheAPB4Multiplexer.ItisusedtoextendanAPB4transfer.

4.2.5 MST_PSLVERR

MST_PSLVERR indicates a failed data transfer to the APB4 Master whenasserted(‘1’)andisdrivenbytheselectedperipheralviatheAPB4Multiplexer.

4.3 SlaveInterfaceTheSlaveInterfaceprovidesthefollowingsignalsforeachindividualperipheral.Thenumberofperipherals supported,and therefore instancesof the followingsignals,iscontrolledbytheSLAVESparameter(seesection0).

Port Size Direction DescriptionSLV_PSEL[n] 1 Output PeripheralSelectSLV_PRDATA[n] PDATA_SIZE Input ReadDataBusSLV_PREADY[n] 1 Input TransferReadyInputSLV_PSLVERR[n] 1 Input TransferErrorIndicatorslv_addr[n] PADDR_SIZE Input TransferReadyInputslv_mask[n] PADDR_SIZE Input TransferErrorIndicator

Table4-3:SlaveInterfacePorts

4.3.1 SLV_PSEL[n]

The APB4 Multiplexer generates SLV_PSEL[n], signaling to an attachedperipheralthatitisselectedandadatatransferispending.

4.3.2 SLV_PRDATA[n]

SLV_PRDATA[n] is the APB4 read data bus associated with the attachedperipheral. The peripheral drives this bus during read cycles, indicated when

Note: Eachindividualportnameisreferencedbytheindex‘n’,where‘n’isanintegervalueintherange0toSLAVES-1.E.g.SLV_PSEL[2]

Thisnomenclatureisusedthroughoutthisdatasheet

Paul Hardy� 26/4/2017 10:47Deleted: 3.1.1

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PWRITE isnegated (‘0’), and thedata is thenmultiplexed to theMST_PRDATAoutputport.

The bus width must be byte-aligned and is defined by the PDATA_SIZEparameter.

4.3.3 SLV_PREADY[n]

SLV_PREADY[n] is driven by the attached peripheral andmultiplexed to theMST_PREADYoutputport.ItisusedtoextendanAPB4transfer.

4.3.4 SLV_PSLVERR[n]

SLV_PSLVERR[n]indicatesafaileddatatransferwhenasserted(‘1’).

AsAPB4peripheralsarenotrequiredtosupportthissignalitmustbetiedLOW(‘0’)whenunused.

4.3.5 slv_addr[n]andslv_mask[n]

slv_addr[n]isthebaseaddresswheretheattachedperipheralistoappearinthesystemmemorymap. It isbitwise ‘AND’edwith thecorrespondingaddressmask slv_mask[n] input to define the overall address range of eachperipheral.

As a consequence, these ports are typically assigned hard-coded values ratherthanconnectedtootherlogicinthedesign.

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5 ResourcesBelowaresomeexampleimplementationsforvariousplatforms.

All implementations arepushbutton, no efforthasbeenundertaken to reduceareaorimproveperformance.

Platform DFF LogicCells

Memory Configuration

Cyclone-IV 0 84 0 SLAVES=23PADDR_SIZE=16PDATA_SIZE=8

Table5-1:ResourceUtilizationExamples

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6 RevisionHistoryDate Rev. Comments01-Feb-2017 1.0 InitialRelease

Table6-1:RevisionHistory

Documents

APB4 Multiplexer Datasheet - Roa Logic · The Roa Logic APB4 Multiplexer is a fully configurable interconnect IP to enable an APB4 Master to communicate with multiple APB4 slaves