AP3101 Application Note V1.3 080107

8/8/2019 AP3101 Application Note V1.3 080107

1/5

Application Note 1020

BCD Semiconductor Manufacturing Limited

1

Jan. 2008 Rev. 1. 3

IntroductionWith the development of power technology, the

demand for low standby power in power systems hasincreased. The AP3101 is a green current mode PWMcontroller. Its input power can be less than 0. 3W in265V AC input at no load condition. The targetAP3101 application fields consists of LCD Monitor/ TV and other off-line AC-to-DC adapters.

This application note includes a general description,detailed description of major functions, and providesnotes for typical applications in SMPS.

1. General DescriptionThe AP3101 acts as a programmable fixed frequency

PWM control during normal operation, and an externalresistor is used to set the osillating frequency. Whenoutput power of a SMPS falls below the given level,the IC automatically enters the skip cycle mode toreduce power consumption.

Owing to low start-up current of 30 A and low oper-ating current of 3mA, the AP3101 can reduce standbypower dissipation of the startup resistor, and improveoperating efficiency. In addition, totem driver outputstage with 0. 6A current capacity is helpful for drivingMOSFET directly.

With the built-in limited power control, the AP3101

can turn off the PWM output after 23 ms in overload orshort circuit conditions, and the input power of aSMPS can drop close to zero. Also, the perfect protec-tion against over-temperature is automatically per-formed. Furthermore, leading edge blanking (LEB)technology is included in the AP3101 for noise immu-nity; built-in slope compensation ensures the stabilityof peak current mode control.

Figure 1 is the functional block diagram of AP3101.Figure 2 is AP3101's Pin Configuration.

Green Mode PWM Controller AP3101-- Function Description and Design Consideration

Figure 1 . Functional Block Diagram of AP3101

ON/OFFDriver

OSC

LEB

VCC

6V

SlopeCompensation

Short circuitProtection

Q D

CLKRB

Skip Cycle

16V/10V

RI

VCC

VIN

GND

R

GATE

ADJ

FB

SENSE

Internal Bias

UVLO

8

5

2

1

4

7

3

6

OTP

PWM

2R

6V

R

4R

Current Limit

0.85V

Prepared by Wu QuanqingSystem Engineering Dept.


2/5



2

Jan. 2008 Rev. 1. 3

2. Pin DescriptionsGND (pin 1) The combined control circuitry and

power ground.FB (pin 2) The feedback voltage pin is connected tothe external opto-coupler, and its typical source currentis 1. 3mA. This FB pin together with the current sensepin will determine the PWM duty cycle.

VIN (pin 3) The pin is shorted to the VCC internally. Itcan be pulled high to the rectified line input through aresistor for startup.

RI (pin 4) Frequency set pin. A resistor between the RIand GND will generate a constant current source, andthe current source will determine the oscillating fre-quency by charging an internal capacitor.

ADJ (pin 5) An external resistor from this pin toground can adjust the voltage level when the systementers the skip cycle mode.

Sense (pin 6) It is used for current mode control andpulse-pulse current limit. A voltage proportional to theinductor current is connected to this pin.

VCC (pin 7) The power supply for the device.

GATE (pin 8) The PWM output directly drives thegate of MOSFET.

3. Function Descriptions3. 1 Green Mode

In normal operation with heavy load, the AP3101works at a fixed switching frequency, and the voltageon the FB pin (V FB) corresponds to a larger peak cur-

rent. When load power drops to a lower level, the V FBdecreases as well as the peak switch current. If peak current drops to a given set point where the non-invert-

ing voltage of the skip cycle comparator (V FB-0. 9V) islower than its inverting input (V ADJ ), the AP3101 willenter skip cycle mode and start to blank its outputpulse.

Figure 4 illustrates the actual skip cycle waveform at

the gate pin. The power transfer now depends upon thelength of the pulse bunches. Suppose we have the fol-lowing component values:LP, primary inductance: 1mH;f S, oscillating frequency: 65kHz;IP: 200 mA.

At light load, the converter will enter the DCMmode. And the theoretical power transfer is therefore:

0. 5*L P*IP2*f S=1. 3W.

Figure 2. Pin Configuration of AP3101

GND

VIN

FB

RI

GATE

VCC

SENSE

ADJ

8

7

6

5

1

2

3

4

V R

R R

RV

ADJ

ADJ

ADJ

ADJ ADJ )24

2496(

24144

++

+=

Figure 3. R ADJ(K) Sets The Skip Cycle Point

Figure 4. The Skip Cycle Waveform

ADJ

GND

AP3101 R ADJ


3/5



3

Jan. 2008 Rev. 1. 3

If the device enters the skip cycle mode with a bunchlength of 15 ms over a recurrent period of 100 ms,then the total power transfer is: 1. 3*15/100= 195 mW.

3. 2 Start-upFor low standby power, the high resistance value of

the startup resistor is selected. However, it will causelonger startup time. To reduce the startup time, we canuse a speedup startup circuit. The value of capacitorC1 should be less than capacitor C2. (see Figure 5)

Moreover, the value of C1 and C2 should be selectedcarefully in the actual design. Once the AP3101 startsto work, the C2 will be charged by the transformer butthe voltage for C1 will reduce rapidly because startupcurrent can't maintain the IC operation current. So, theC2 should also be charged as quickly as possible. Thusthe power of C2 through a transformer can take overthe C1 smoothly and the output voltage will not dropor repeat many times during the startup process.

At last, the design of R START should meet the limi-tation of IC startup condition and maximum voltageoperation condition with its maximum load, whichalways indicates the maximum and minimum equiva-lent resistor of IC (V/I).

4. 3 Oscillator A resistor RI between RI and GND will generate a

constant current source, and the current source willdetermine the oscillating frequency by charging aninternal capacitor.

The oscillating frequency can be expressed as:

The recommended oscillation range frequency is 50

kHz to 100 kHz. (see Figure 6)

A small capacitor (not over 50pF) connected in par-allel with resistor RI can be utilized to avoid noise.

4. 4 Output DriverTotem-pole output stage can directly drive MOS-

FET, and its maximal output voltage is clamped at22V. In addition, typical rise and fall time of outputpulse is 250ns and 50ns respectively.

4. 5 The Compensation.The normal compensation mode is illustrated as

Figure 7. Its feedback compensation network transferfunction can be deduced as :

In general design, the crossover frequency f C of thepower system can be determined with the main powerparameter design. Then, we can place a compensatorzero (f Z) around f C /3 and place a compensator pole(f P) above 3f C. Thus, we can obtain a good responsefeature and stability margin. In addition, the output LC

Figure 5. Speedup Start-up Circuits

)][

1690kHz

k R f

I

15 18 21 24 27 30 33 36 39 42

40

60

80

100

120

O s c

i l l a

t o r

F r e q u e n c y

( k H z )

Timing Resistor (k )

Figure 6. Frequency vs. Timing Resistor

B B

1C 1

D11

B

O

BF FB C sR1

)C Rs(R1s1

R RC R

(s)V

(s)V (s)G

+++

==

B BP C R

f 2

1=

1)(21

C R R f C 1 Z +=

VCC

GND

AP3101 C1 C2

D1 D2 R1

Line V DC

RSTART


4/5



4

Jan. 2008 Rev. 1. 3

filter should enable to bring some amount of phaseshift and should be considered for real application.

4. 6 Over Temperature ProtectionThe AP3101 will automatically turn off the PWM

output when junction temperature rises up to a givenvalue; the typical value is 150 oC, with hysteresis of 25oC.

5. Adapter Application5. 1 How to Reduce Standby Power

First, a high value for the startup resistor is selectedto lower loss. In Figure 8, a start-up resistor R1 of 1.5M is selected to ensure that VCC hold up capaci-

tor C3 is charged up to 16V even under low line volt-age of 85VAC, and the maximum power loss on R1 is90mW. Once the AP3101 begins to work, an auxiliarywinding of the transformer T1 will provide operatingcurrent for the IC.

Second, adjusting the skip cycle level can reduceswitching loss on MOSFET. The resistor R ADJ on pinADJ is used to adjust the skip cycle frequency; alarger resistor corresponds to a lower skip cycle fre-quency, so lower input power can be obtained. How-ever, with the larger resistor it also needs a larger VCChold-up capacitor and the peak switching current willalso become larger correspondingly. Also, a low-valuecapacitor can't provide enough energy to the AP3101at light load condition or less.

5. 2 How to Avoid Audio NoiseThe transformer T1 is the main noise source. Under

light or no load, the AP3101 will operate in skip cyclemode with lower switching frequency, and audio noisefrom the transformer T1 will probably be heard.

Therefore, 0. 5 to 1kHz of skip cycle frequency is pre-ferred to compromise between standby power andaudio noise. In addition, the adhesives in the trans-former construction are required.

The snub capacitor C2 is another noise source.Polypropylene capacitor can greatly reduce this noise.(see Figure 8)

5. 3 PCB LayoutPCB layout is a critical portion of switching power

supply. Improper layout will adversely affect RFI radi-ation, component reliability, efficiency and stability.

Within an adapter, there are four major currentloops. Two of the loops conduct the high-level ACcurrents needed by the supply. They are the powerswitch AC current loop and the output rectifier ACcurrent loop. The currents are the typical trapezoidalcurrent pulses with very high peak current and veryrapid di/dt. The other two current loops are the inputsource and the output load current loops, which carrylow frequency current being supplied from the voltagesource to and from the load respectively.

For the power switch AC current loop, current flowsfrom the input filter capacitor through the transformerwinding and the power switch then back to the nega-

tive terminal of the input capacitor. Similarly, the out-put rectifier current loop's current flows from thesecondary transformer winding, through the rectifierto the output filter capacitor and back to the winding.The filter capacitors are the only components that cansource and sink the large levels of AC current in thetime needed by the switching power supply. The PCBtraces should be made as wide and as short as possible,which can minimize parasite resistive and inductiveeffects. These traces should be laid out fistly. As forthe input source and output load current loops, both of these loops must be connected directly to their respec-tive filter capacitor's terminals. All the current pathloops, particularly with high frequency switching,should be as short as possible. Thus it will reduce theso-called conduction or radiation interference.

The grounds are extremely important to the properoperation of the switching power supply. The analogcontrol ground should be connected first and thenconnected to other circuitry. "One point grounding"must be used. Single-point grounding keeps the noisesources separated from the sensitive control circuits.

Vref

VFB

VO

RD

RC C1

R1

R2

RB

CBRbias

AP3101 FB

GND

Vref

VFB

VO

RD

RC C1

R1

R2

RB

CBRbias

AP3101 FB

GND

Figure 7. AP3101 Normal Compensator with AZ431


5/5



5

Jan. 2008 Rev. 1. 3

Figure 8. Typical Application of AP3101

R11

C8

C3

R12

R10

C2

R7

R4

NTC

R3

R13620

R60.5

Q17N60

BD1

R2

12V/3A

J2J1C1

1

2

4

3

U2 p521

Q2AZ431

D2

D1

R8

R1

C7

L2D3

C6

T

C5

R9

ADJ

5

SENSE

6

VIN

3

RI

4

GATE

8

VCC

7

FB

2

GND

1

U1AP3101

Cb

Care must be taken that pin ADJ and pin RI are placedaway from noise sources which are sensitive or maydisturb the signal.

Documents

AP3101 Application Note V1.3 080107