AO Brochure

8/9/2019 AO Brochure

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Analog

Ofce


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A key aim is to develop highly accurate models or

transistors and passives such as spiral inductors at

requencies up to 40 GHz. Analog Ofce sotware

enables us to accurately model active devices, passives,

and interconnects on SoS so that our customers realize

frst-time-right designs.

Yash Moghe, Design Engineering Manager

Sapphicon Semiconductor

The Analog Ofce RFIC design environment is a unique user experience as it combines

ease-o-use, exibility and accuracy with all the tools essential or RFIC design in a

single desktop solution. It also lets you control and seamlessly integrate best-in-class

third-party tools to capture, synthesize, simulate, optimize, layout, extract, and veriy

designs rom system to fnal tape-out. Built upon AWRs Unifed Data Model, Analog

Ofce sotware gives you the power to streamline your design process, increase

productivity, and shorten time-to-market.

PRODUCTIVITy-FOCUSED DESIGN FLOW

Windows UI: simply an elegant interace Since the company was ounded in

1994, AWRs mission has been simple: To provide a superior high-requencydesign ow, whether youre learning a new capability or preparing a fnal design

or the oundry. Every element o the Analog Ofce sotware environment is so

well integrated its easy to orget that working behind the scenes is

exceptionally powerul design sotware.

Unifed Data Model: schematic and layout The cornerstone

o AWRs design ow, our single, object-oriented database is

synchronized at its core, in the database, not through multiple layers

o sotware. So whether youre driving the design rom the schematic,

simulation, or layout, the Analog Ofce design environment lets you

take your ideas rom concept through simulation and directly to

physical implementation all in one platorm.

Open, standard-based PDKs: true interoperability Analog Ofce

sotware lets you export design layouts to an OpenAccess-based

database using interoperable PDK libraries (IPL) so you can access

the same libraries across all design tools rom OpenAccess-based

tool vendors. oull save time, achieve optimum perormance, and

get your product through development aster.

USER-FLEXIBLE DESIGN ENVIRONMENT

AWRs Analog Ofce RFIC design platorm is unique in its ability to let you integrate

third-party tools at all stages o the design process.

DRC/LVS: signed o/approved links to EDA vendors Analog Ofce supports

multiple sign o verifcation ows including PowerDRC/LVS, Mentor Graphics

Calibre, Cadences Assura and open-source ICED. All are easily managed rom

within the Analog Ofce environment.

HSPICE: direct import o ormatted netlists Import HSPICE-ormatted encrypted

netlists directly into Analog Ofce sotware or ready simulation within the AWR

environment. This makes it possible to bring in legacy designs as well as those

rom other groups or companies.

Advancing the

Design o RFICs

Analog Ofce sotware handles mixed-signal

designs like this complex PLL in a 0.13um

RFCMOS process.


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EM Socket: seamless integration o third-

party EM point tools AWRs EM Socket interace

allows you to directly and seamlessly integrate popular EM

solvers into the Analog Ofce design environment. Choose

high-requency EM tools like AXIEM, CST, and Sonnet, as well as specialized silicon-

wise tools rom OEA International.

INNOVATIVE TECHNOLOGIES

All o AWRs sotware tools are continually enhanced to ensure they always

represent the state-o-the-art in technology while making sure they serve to

increase your productivity. AWR innovations include:

APLAC Simulation Technology APLAC high-requency circuit simulator

technology ,used by Nokia mobile phones or more than a decade today is a

standard component o the Analog Ofce design suite. Powerul APLAC engines

deliver efcient simulators tailored or harmonic balance and time-domain analysis

o large-scale and extremely nonlinear RFIC designs. APLAC harmonic balancesimulation is urther enhanced by patent-pending Multi-Rate Harmonic Balance

(MRHB) technology or even more complex designs.

Intelligent Net (iNet) Technology iNet delivers on the y

interconnect extraction, similar in concept to timing-driven

or wire-driven digital design, yet tailored to the needs o RF

designers. iNet ocuses on accurate RF interconnect modeling

and analysis throughout the entire RFIC design process.

ACE Automated Circuit Extraction Technology ACE technology

dramatically reduces the time required to perorm initial modeling

o complex interconnects by using layout-based models or circuitextraction - automating identifcation o transmission lines rom

layout and partitioning these structures into pre-existing models.

AXIEM 3D Planar EM Technology AXIEM transorms RFIC

design by enabling EM analysis to be accurate and ast enough

to serve as an upront design diagnostic utility. AXIEM is tailored

to 3D high-requency planar components, delivering exceptionally

accurate EM simulation that is ast, efcient and capable to

handle extremely large and complex designs.

Analog Ofce sotware is a complete

analog and RFIC design environment

thats readily complemented by

third-party EDA tools.

Ring oscillator layout in Analog Ofce.

ANALOG OFFICE

DESIGN FLOW

DesignEntry

OpenAccess

Circuit Sim.HB/APLAC

HSPICE

SpiralExtraction

AXIEM

Calibre,Assura, ICED

DRC & LVSPowerDRC/

LVS

Circuit Sim.Spectre

EM SimulatorCST, Sonnet

NetExtraction

ACE/Net-An

System Design &Simulation: VSS

Tape-out

Block/ChipLayout


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Analog Ofce in the Design Process

Linear and nonlinear circuit simulation

Layout with parasitic extraction

EM analysis

Co-simulation with system tools

Statistical design and design centering

Link to back-end DRC/LVS

Features at a Glance

High perormance harmonic balance and transient solver technologies

Harmonic balance

Transient-assisted harmonic balance

MRHB multi-rate harmonic balance

Transient/time-domain

Transient, AC and noise analysis using both HSPICE and APLAC

Intelligent Nets (iNets) interconnect extraction technology

ACE automatic circuit extraction technology

EM Socket interace or integration o third party tools:

OEA International NET-AN or 3D RLCK extraction

AXIEM 3D planar EM analysis or upront design diagnostics and post-

layout verifcation

DRC/LVS tools such as PowerDRC/LVS, Calibre, Assura and ICED

Seamless integration with AWRs Visual System Simulator design suite

or system co-simulation

USA

Corporate Headquarters

AWR Corporation

1960 E. Grand Avenue, Suite 430

El Segundo, CA 90245

+1 310 726 3000

+1 310 726 3005 (ax)

Japan

AWR Japan KK

Level 5, 711 Building

7-11-18 Nishi-Shinjuku, Shinjuku-ku

Tokyo 160-0023 Japan

+81 3 5937 4803

Korea

AWR Korea Co. Ltd.

B-1412, Intellige-II, 24 Jeongja-dong,

Bundang-gu, Seongnam-si,

Gyeonggi-do, South Korea, 463-811

+82.31.603.7772~3

UK

AWR UK

2 Hunting Gate

Hitchin, Herts

SG4 0TJ, UK

+44 (0) 1462 428 428

Finland

AWR APLAC

Lars Sonckin kaari 16

FI-02600 Espoo, Finland

+358 10 834 5900

France

AWR France

140 Avenue Champs Elysees

75008 Paris, France

+33 1 70 36 19 63

Copyright 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Analog Ofce, MicrowaveOfce and APLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, EM Socket, iNet,Unifed Data Model are trademarks o AWR Corporation. All others are property o their respective holders.

www.awrcorp.comwww.awr.tv

BR-AO-2010.5.6

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