FEA Modeling of a Wafer Level Seam Sealing Approach for MEMS Packaging

Weidong Wang Center for Ocean Technology, College of Marine Science, Univ. of South Florida

David Fries Center for Ocean Technology, College of Marine Science, Univ. of South Florida

Abstract

A wafer level seam sealing process using resistive heating method is proposed in this paper. Using this method, microelectromechanical (MEMS) devices can be capped and protected at wafer level before other post packaging processes are performed. The sealing process can be done by localized resistive heating at the contact areas between heating electrodes and the edges of the lid cover. A 3-D finite element analysis (FEA) model was created to simulate the thermo-electric behavior of the proposed approach. Temperature and electrical potential distributions were calculated using FEA. The simulation results indicated that this method would provide a feasible solution for wafer level hermetic seam sealing for packaging MEMS using locally heated eutectic bonding or soldering techniques. During the entire sealing processes, MEMS devices will remain at the room temperature. Thus, thermal effect on MEMS devices from heating sources can be minimized.

Introduction One of the most important areas for developing and commercializing MEMS is packaging [1, 2], since packaging normally represents 50%~80% of the total costs of MEMS. So it is essential to develop some low cost MEMS packaging technologies. One of the most challenging aspects regarding MEMS packaging is that MEMS have moving parts, which differentiate their packaging requirements from standard microelectronic packaging counter parts. The released moving parts are very delicate and very easy to be damaged during packaging processes. For example, released MEMS parts simply can't go through dicing process without using special tooling and care. It is not practical to release a huge amount of small MEMS dies after dicing either, since that would create difficulties for handling.

One way to solve this problem is to protect MEMS devices at wafer level right after they are released using certain capping techniques [2], so that the chance of damage to MEMS devices will be minimized. Capping normally is done by using soldering or wafer to wafer bonding [2, 3]. Normally entire wafers would be heated up to certain temperatures simultaneously in order to reflow solders or to make wafer bondings. Even at temperature level of 150C~200C, many MEMS devices will still suffer from performance degradation. For example, change of curvatures of MEMS micromirrors due to temperature rising will cause optical beams to change their shape, such that optical transmission efficiency will be reduced. Some micro fluidic devices will not be able to tolerate temperature higher than 100C in the cases of that fluids are pre-injected in the MEMS devices. Thus, localized heating right at the bonding areas is preferred for sealing MEMS devices at wafer level. A number of localized heating approaches were proposed by researchers, including using polysilicon micro heaters or laser heating [4, 5].

Here we propose using resistive heating techniques to realize local heating at wafer level MEMS packaging. This method can be done using commercial off the shelves (COTs) IC packaging equipments with minimum modifications, which would be advantageous in terms of shortening product development cycle time, lowering R&D and manufacturing costs, reducing time of transition from R&D to manufacturing, and reducing time to market.

Principle of operation Wafer level packaging for MEMS devices is illustrated in Figure 1. After last fabrication step of MEMS devices, they will be released as a whole wafer in order to increase process efficiency and manufacturability. Right after releasing, each individual die will be covered and protected immediately with caps to minimize any chance of contaminations and damages to moving parts from environment and handling. Each individual cap can be put on wafer using high throughput pick and place technology, then tacked on wafer. The whole wafer with caps will be presented into a hermetic parallel seam sealer, which has good environmental control to ensure low moisture level during seam sealing. Moisture can be removed using vacuum bake-out oven that comes with hermetic seam sealer. Each cap will be hermetically sealed onto substrate using localized resistive heating method.

Figure 1. Wafer level packaging for MEMS Figure 2 shows a schematic cross sectional view of a single device packaging. During the sealing process, electrodes will touch the edges of lid cover from both sides, and the electrodes will be rolling along the edges of lid cover. Voltage or current will be supplied onto the electrodes, causing current flow through the high resistance lid cover. Joule heating resulted from current flow will cause local temperature rising around the contact areas as well as the bond sealing lines, thus, soldering or eutectic bonding will occur once the electrodes move away and bond lines get cooled down to room temperature. Since the sealing process involves liquid solder or eutectic reflows, the requirements on surface flatness can be much less than those from direct fusion or anodic bonding. Hence, metal traces can be run through under the bonding lines to make the interconnections from MEMS devices to the outsides of the caps. Alternatively, micro vias through lid cover or substrate can also be used for interconnections.

Figure 2. Schematic cross sectional view of device packaging After sealing process is done, wafer will go through wafer test. Known good dies will be marked, and they will be picked up after dicing. The good devices can then be treated using standard microelectronic packaging techniques, such as pick and place, injection molding, flip chip, chip on board and so on. None of these post processes would require high-class clean room since MEMS devices have already been protected very well.

FEA modeling and simulation approach ANSYS Multiphysics7.0 was used to model the packaging approach proposed in earlier section. The 3-D model created using ANSYS is shown in Figure 3. Only half of the structure was modeled based on symmetry in order to reduce the model size. Note that this may create some deviation for the modeled results from the real situation when electrodes move close to the corners of the package. The material type, material properties [6, 7] and dimensions used in the simulation are summarized in Table 1.

Figure 3. 3-D model created using ANSYS

Table1 Materials used in simulations

Lid cover Electrodes Bonding Line Substrate

Material Si Cu/Cr Alloy Au Si

Young's modulus (Mpa)

1.8 x 105 1.17 x 105 7.8 x 104 1.8 x 105

Poisson's ratio 0.262 0.29 0.44 0.262

CTE (10-6/K) 2.33 17.6 14.2 2.33

Thermal conductivity (pw/um-K)

1.57 x 108

3.24 x 108

3.23 x 108

1.57 x 108

Resistivity (T ohm-um)

1.0 x 10-11

1.0 x 10-10

1.0 x 10-9

2.16 x 10-14

2.05 x 10-14

-

Dimension (mm) 2 x 2 x 0.3 1.0 (OD) x 2.6 (L) 4.2 x 0.05 x 0.01 6.2 x 6.2 x 0.5

As an example, silicon was used for lid cover in the following simulations. Its sidewall thickness is 0.3mm. The thickness and width of lid edge, as shown in Figure 2, are 0.15mm and 0.8mm respectively. Three values of resistivity of lid cover were simulated to evaluate its impact on required electrical signals. These resistivity values can be achieved using different level of boron doping in silicon wafers. Also, the resistivity of silicon would vary with temperature. Further more, the relationship between the resistivity and temperature may vary depending upon boron doping level. To simplify the problem at initial study, the temperature dependence of resistivity, as well as other material properties were not taken into account in this paper.

Other high resistance materials, such as Kovar or Invar, can also be used as lid cover. The same model can be used to simulate their behaviors. Copper/Chromium alloy was used for heating electrodes, which are commonly used in resistive welding. The electrodes have a 10 taper at the ends where electrodes and lid edges are making contacts. The tapered sections are 0.6mm long. Gold was used for bonding ring. Note that other thin intermediate layers, such as solder layers, can also be used. Substrate is silicon, where MEMS devices are fabricated. There should be a thin layer of silicon nitride on top of substrate for electrical isolation. Because it is so thin, so the effect of it is ignored in this simulation.

SOLID69, 3-D thermo-electric coupled field model, was used to mesh the lid cover, electrodes, and bond line. SOLID70, thermal analysis model, was used to mesh the substrate, since only heat conduction property of the substrate is concerned for this thermo-electric modeling. Due to the highly irregular shape around electrode-lid edge contact area, tetrahedral meshing was used. Steady state simulations were performed to evaluate the temperature distributions, which can be used as initial temperature conditions for next step transient analysis as electrode moving along the edges of the lid.

The meshed model is shown in Figure 4. The close up view of meshed area around electrode-lid edge contact area is shown in Figure 5. At the contact area, micro deformation was introduced to simulate the contact between electrodes and lid edge. The contact area is roughly 50um square. Ideal thermal and electrical contacts were assumed between all contact surfaces. Fine mesh was used around electrode-lid edge contact areas, as well as bond line areas. Other areas were meshed using coarser elements, as shown in Figure 4 and 5.

Figure 4. Meshing of solid model

Figure 5. Zoomed in view of meshed area around electrode-lid edge contact point

Room temperature boundary conditions were applied to the far ends of two electrodes and the bottom of substrate. Voltages were applied to the far end of one electrode, while zero volts were applied to the far end of the other electrode.

Heat losses due to radiation and convection have been ignored for most of the simulations, as discussed in following section.

Results and Discussion Initially, the heat losses due to convection and radiation were examined. The heat loss due to convection from exterior surfaces of the package and electrodes can be described by Newton's Law of cooling [8]:

)( TaTshAEc = where h is the convection heat transfer coefficient, A is the area of the exterior surfaces of the package or electrodes, Ts is the temperature of the surface A , and Ta is the ambient temperature. The heat loss due to radiation from exterior surfaces of the package and electrodes can be described by Stefan-Boltzmann equation [8]:

)( 44 TaTsAEr = where =5.67 x 10-8 pW/um2-K4 is Stefan-Boltzmann constant, is the emissivity of the surface A . The above convection and radiation boundary conditions were applied onto the exterior surfaces of the packages and electrodes in an FEA simulation for a situation of lid resistivity of 1x10-10 T -um and 18V load, using =1, which represents the maximum radiation of an ideal black body, and the heat transfer coefficient of h =25pW/um2-K [9] for free air convection. It was found that the temperature changes due to convection and radiation were less than 1C by comparing the results between with and without convection and radiation boundary conditions applied. This is due to that the high temperature zone is highly concentrated (as being discussed later), and the thermal conductivities of the package and electrodes are so good, thus the conduction heat transfer mode becomes dominant completely. This result is similar to the findings from literature [9] for an FEA simulation of a spot resistive welding, where less than 2C temperature changes due to convection and radiation were found. Hence, in the following simulation and analysis, heat losses due to convection and radiation were ignored.

The temperature and electrical potential distributions, simulated for 18V load, 1x10-10 T -um lid resistivity, are shown in Figure 6 and Figure 7. As it can be seen, even if the maximum local temperature around electrode-lid contact area can reach higher than 1000C, the substrate areas right under the lid where MEMS devices stay, still remain at room temperature. So MEMS devices will not see high temperatures at all during the entire sealing process. The most part of the lid has uniform electrical potentials across, indicating it has enough conductivity.

Figure 6. Temperature contour plot for 1x10-10 T -um lid resistivity, 18V load

Figure 7. Electrical potential contour plot for 1x10-10 T -um lid resistivity, 18V load Figure 8 and 9 show the close up temperature distributions around electrode-lid edge contact areas and bond lines for loaded (Figure 8) and grounded electrodes (Figure 9). It can be seen that they have the same temperature profiles. The high temperature zones are highly constrained around electrode-lid contact areas,

so the heat impact zones are very small. Figure 10 and 11 show the close up electrical potential distributions around electrode-lid edge contact areas for loaded (Figure 10) and grounded (Figure 11) electrodes. It can be seen that they have different electrical potential distributions. The majority of the voltage drop is around electrode-lid contact areas also.

Figure 8. Zoomed in view of temperature contour around loaded contact area for Fig. 6

Figure 9. Zoomed in view of temperature contour around grounded contact area for Fig. 6

Figure 10. Zoomed in view of potential contour around loaded contact area for Fig. 7

Figure 11. Zoomed in view of potential contour around grounded contact area for Fig. 7

Also for 18V load, 1x10-10 T -um lid resistivity, the total current flow is calculated as 3.98A. So the total power is 71.6W. Based on this, the equivalent resistance can be estimated as 4.5 . The heat dissipations through the loaded electrode, grounded electrode, and substrate are calculated as 12.6W, 12.6W, and 46.4W, representing 17.6%, 17.6%, and 64.8% of the total power of 71.6W, respectively.

The thermo-electric behaviors of the sealing process have been simulated for three different lid resistivities, as listed in Table 1. The simulations were done regarding to achieve maximum temperature in the range of about 400C~1300C, such that it won't reach the melting temperature of silicon (1414C). It has been found that the voltages required for reaching such maximum temperature range are about 4V~7V (maximum temperature range: 452C~1322C), 10V~19.5V (maximum temperature range: 378C~1353C), and 32V~58V (maximum temperature range: 420C~1311C) for lid resistivities of 1x10-11, 1x10-10, and 1x10-9 T -um, respectively. As an example, the temperature profiles for lid resistivity of 1x10-10 T -um are shown in Figure 12 with applied voltages as parameters. Figure 12 was obtained by plotting the temperature data on a path defined on the symmetry plane, from a point in maximum temperature zone (point 3) to a point in the area below bond line (point 4), as shown in Figure 13. The center of top surface of bond line is roughly located at the distance of 140um away from the maximum temperature point on the path (point 3). The centers of bond lines are corresponding to the second last group of data points in Figure 12. The temperature profiles for the other two values of lid resistivities are similar to the curves plotted in Figure 12, just with different voltage ranges.

Figure 12. Temperature profiles as a function of distance from maximum temperature zone

Figure 13. Path for the temperature profiles plotted in Figure 12 From Figure 12, the relationships between maximum temperatures on the path (Tmax, at point 3 in Figure 13), bond line temperatures (Tb, where the path crosses the top surface of the bond line in Figure 13) and the voltage squares are obtained and plotted in Figure 14. The voltage squares are proportional to the powers applied. Again, Figure 14 shows the data for lid resistivity of 1x10-10 T -um. The plots for the other two resistivities are similar to Figure 14 just with different voltage square ranges. From Figure 14, it can be seen that the process shows ideal conduction dominated heating phenomenon (as discussed earlier), since R-squares of the linear regressions between maximum temperatures, bond line temperatures and voltage squares are exactly 1. From the linear regression equations obtained in Figure 14, one can calculate maximum temperatures and bond line temperatures for any given applied voltage. When voltage is zero, both maximum and bond line temperatures should reach room temperature, 30C. The minor differences between the results for zero volts calculated from the equations in Figure 14 and 30C, are likely due to limited data points in the charts were used for regressions, as well as the rounding effects in the computations.

Figure 14. Maximum temperatures and bond line temperatures vs. voltage squares

As an application example, Figure 15 shows the relationships between the required voltages and lid resistivities for achieving bond line temperatures (Tb) of 350C and 400C. A temperature of 350C should be sufficient for getting good Au-Sn soldering, while a temperature of 400C should be sufficient for realizing good Au-Si eutectic bonding. The voltages required for realizing these bondings can be easily calculated from Figure 15 for any given lid resistivity. It also can be seen that voltage square and resistivity have a linear relationship, which is the result of the resistive heating model used in the simulation.

Figure 15. Linear relationship between voltage square and resistivity of lid cover The percentages of heat dissipations through loaded electrode, grounded electrode and substrate, as well as the equivalent resistance Re, are calculated and listed in Table 2 for three lid resistivities. Using the equivalent resistances, the power required for achieving certain bond line temperature can be calculated from the voltage squares of Figure 15.

Table2 Percentage of heat dissipations and equivalent resistance Re

Resistivity of Lid (T ohms-um)

1.0 x 10-11 1.0 x 10-10 1.0 x 10-9

Loaded electrode 15.5% 17.6% 18.5%

Grounded electrode 15.5% 17.6% 18.5%

Substrate 69.0% 64.8% 63.0%

Re (ohms) 0.5 4.5 43.2

Further modeling includes transient analysis to simulate the temperature history as well as the residual stress, and their impact on package reliability. Also, temperature dependent material properties, such as thermal conductivity and resistivity, would be considered into future simulations to get more accurate temperature distributions and required powers.

Conclusion We proposed using localized resistive heating as a wafer level hermetic sealing process for packaging MEMS devices. 3-D finite element analysis using ANSYS Multiphysics 7.0 was used for modeling and

simulation of the proposed approach. The simulation results indicate that the heat impact zone is very small during the sealing process, so that the possible detrimental thermal impact on MEMS devices during the packaging process can be minimized. Certain bonding technologies, such as soldering (Au-Sn) and eutectic bonding (Au-Si) can be achieved using this method to realize hermetic seam sealing at wafer level. The design procedure for calculating temperatures and powers based on FEA simulation method provided in this paper will be validated as soon as experimental data is available.

Acknowledgement The authors would like to thank Larry Langebrake, Director of Center for Ocean Technology, for his support to this work. We also would like to thank Dr. Scott Samson and Dr. John Bumgarner for valuable discussions.

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IntroductionPrinciple of operationFEA modeling and simulation approachResults and DiscussionConclusionAcknowledgementReferences