ANAND INSTITUTE OF HIGHER TECHNOLOGY

KAZHIPATTUR-603103

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION

Sub : VLSI DESIGN Class : VII sem

Code : EI2403 Year : VI

PART A

UNIT I

1. What are the second order effects of the MOSFET devices?(Dec-2013)

Following are the list of second order effects of MOSFET.

a.Threshold voltage variations

b.Source to drain resistance

c.Variation in I-V characteristics

d.Subthreshold conduction

e.CMOS latchup

2. Write the equation for drain current of NMOS transistor considering channel length modulation.

(May/June 2013)

I ds = Qc (Chargeinduced∈channel )Electrontransit time(τ ) =

QcL2 µV ds Where, (τ sd= L2

µV ds)

3. What are the factors that cause drain punch through in MOS transistors? (May/June 2013)(Dec-2012)

4. Give the expression for drain current for different modes of MOS transitor. (Dec-2012)

a.cut off region ID=0b.Linear region ID = kn[(VGS-VT)VDS-VDS2/2]C.Saturation region ID = (kn/2)(VGS-VT)2

5. What is the advantage of CMOS over PMOS and NMOS technology.(Nov 2011)

CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together.

6. Write the reasons for the limited load driving capabilities of MOS transistors. (Nov 2011)

7. What are the different fabrication processes available to CMOS technology?(Nov-2010)

a. p-well processb. n-well processc. Twin-tub processd. Silicon o Insulator (SOI)/ Silicon On Sapphire (SOS) process

8. Plot the current-voltage characteristics of a nMOS transistor (Nov-2010)

9. Define accumulation mode.(NOV-2009)

The initial distribution of mobile positive holes in a p type silicon substrate of a MOS transistor for a voltage much less than the threshold voltage10. Give the different mode of operation of MOS transistor.(NOV-2009)

Cut off mode Linear mode Saturation mode

UNIT II

1. Compare Inverting and non-inverting Supper buffers.(Dec-2013)

2. Stae the significance of Lamda based rules(Dec-2013)

3. What are the drawbacks of NMOS inverters over CMOS inverters? (May/June 2012)

a.The steady state power dissipation of the CMOS inverter circuit is negligible.b.The voltage transfer characteristics (VTC) exhibits a full output voltage wing between 0V and VDD. This results in high noise margin.

4. Write the pull up / pull down ratio required when an inverter is driven through pass transistors.

(May/June 2012)

5. Draw the stick diagram of a p-well CMOS inverter. (Nov 2011)

6. Why BiCMOS technology does not offer speed advantage in applications like ALU and ROM

subsystems? (Nov 2011)

When bipolar and MOS technology are merged, the resulting circuits are referred to as BiCMOS circuits. High gain vertical npn transistors with their collectors tied to the positive rail, and medium-gain lateral npn transistors are both compatible with conventional CMOS processing. BiCMOS gates can be used to improve the performance of line drivers and sense amplifiers.

7. What is the advantages of twin-tub process?(DEC 2010)

Advantages of twin-tub process are

i.Seperate optimized wells are available.

ii.Balance performance is obtained for n and p transistors8. What is body effect?(DEC 2010)

The threshold voltage VT is not a constant w.r.to the voltage difference between substrate and the source of MOS transistor. This effect is called substrate-bias effectOr body effect

9. what is channel-length modulation?(Dec-2009)The current between drain and source terminals is constant and independent of the applied voltages over the terminals. This is not entirely correct. The effective length of the conductive channel is modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.

10. Define fall time(Dec-2009)Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

UNIT III

1.What are the static properties of complementary CMOS Gates?(Dec-2013)a.They exhibits rails-to-rails swing with VOH=VDD and VOL=GND.b.The circuits have no static power dissipation, since the circuits are designed such that the pull-down and pull-up networks are mutually exclusive.c.The analysis of the DC voltage transfer characteristics and the noise margin is more complicated than for the inverter, as these parameters depend upon the data input patterns applied to the gate.

2.Draw the equivalent RC model for a two-input NAND gate? (Dec-2013)

Vdd vdd

M1 M2

a

a¿¿

bb

3.What are the major limitations associated with complementary CMOS gate? (Dec-2012)a.The number of transistors required to implement an N fan-in gate is 2N. This can result in a significantly large implementation area.b.The propagation delay of a complementary CMOS gate deteriorates rapidly as a function of the fan-in.

4.What is meant by ratioed logic? (Dec-2012)

outout

PDN 1 PDN 2

In the ratioed logic, a gate consists of an nMOS pull-down network that realizes the logic function and a simple load device, which replace the entire pull-up network. A ratioed logic which uses a grounded pMOS load is referred to as a pseudo-nMOS gate.

5.What is true single phase clocked register? (Dec-2011) The true single-phase clocked register (TSPCR) uses a single clock, CLK. For the positive latch, when CLK is high, the latch is in the transparent mode and corresponds to two cascaded inverters; the latch is non-inverting, and propagates the input to the output. On the other hand, when CLK=0, both inverters are disabled, and the latch is in the hold mode.

6.Define a tally circuit?(DEC 2011) A tally circuit counts the number of inputs that are high and outputs the answer. If there are N inputs there are N+1 possible outputs, corresponding to 0, 1, 2.... N inputs that are high.

7.Draw the CMOS implementation of AB+CD? (Dec-2010) vdd

a b

c d

ab+cd

ca

b d

8.Draw the CMOS implementation of 4-to-1 MUX using transmission gates?(DEC 2010)

9.What are the various modelling used in Verilog? (Dec-2009)1.Gate-level modelling2.Date-flow modelling

gnd

3.Switch-level modelling4.Behavioural modeling5.10. What is the structural gate-level modelling? (Dec-2009) Structural modelling describes a digital logic networks in terms of the components that make up the system. Gate-level modelling is based on using primitive logic gates and specifying how they are wired together.

UNIT IV

1. What are the importances of the PLA/FSM in VLSI?(DEC 2013)I. Regularity: It has a standard, easily expandable layout.

II. Convenience: Little design effort is required.III. Compacted: It is efficient for small circuit.IV. Modularity: It makes it possible to design hierarchical PLAs and FSM into large sequential systems.V. Suitability to being computer generated.

2. Give the structure of a CPLD. (DEC 2013)

A CPLD comprises multiple circuit blocks on a single chip, with internal wiring resource to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL. It includes four PAL like blocks that are connected to a set of interconnection wires. Each PAL like block is also connected to a sub circuit labeled I/O block, which is attached to a number of the chip’s input and output pins.

3. Give the CPLD packages available. (DEC 2012)

a. PLCC package: The PLCC package has pins that “wrap around” the edges of the chip on all of its four sides. The socket that houses the PLCC is attached by solder to the circuit board, and the PLCC is held in the socket by friction.

b. quad flat pack packages: The QFP package has pins on all four sides, and they extend outward from the package, with a downloading-wiring shape. The QFP’s pins are much thinner than those on a PLCC, which means that the package can support a larger number of pins; QFP’s are available with more than 200 pins.

3. Give the structure of MAX 7000 CPLD. (DEC 2012)

4.What is meant by FPGA? (DEC 2011)

A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of up to about 20,000 equivalent gates. FPGAs are quite different from CPLDs because FPGAs do not contain AND or OR planes. Instead, they provide logic blocks for implementation of the required functions.

5 Give the general structure of FPGA. (DEC 2011)

6. What are the different commercial FPGA products? (DEC 2010) Manufacturer FPGA products Actel Act 1,2 and 3,MX,SX Altera FLEX6000,8000 and 10k APEX 20k Atmel AT6000,AT40k Lucent ORCA 1,2 and 3 Vantis VFI Xilinx XC3000,XC4000,XC5200,Virtex

7. What are the types of FPLA?(DEC 2009) PROM [Programmed Read-Only Memory] PAL [Programmed Array Logic]

8. What are the applications of PAL? (DEC 2009) Control logic application Input/output Data-path logic

9. What is finite state machine (FSM)? (DEC 2009)When feedback is added to AND-OR PLA structure, then it becomes FSM.

10.What are the characteristics of PLA/FSM? (DEC 2009) Regularity Modularity Suitability Efficiency

UNIT V

1) What are packages and what is the use of these packages?(Dec2013)

A package declaration is used to store a set of common declaration such as component type’s procedures and functions these declarations can then be imported into other design units using a use clause.

2) What is variable class, give example for variable? (Dec2013)

An object of variable class can also hold a single value of a given type. However in this case different values can be assigned to a variable at different time.

Ex: variable ss: integer.

3) Name 2 subprograms and give the difference between these two. (Dec2012)1) Function.2) Procedure.

Only one output is possible in function. Many outputs possible using procedure.

4) What is subprogram overloading? (Dec2012) If 2 or more subprogram to be executed in a same name, overloading of subprogram should be performed.

5) Write the VHDL coding for a sequential statement (d-flipflop).(Dec 2011)

Entity dff is

port (clk,d:in std_logic;

q:out std_logic);

end;

architecture dff of dff is

begin

process(clk,d)

begin

if clk’ event and clk=’1’ then

q<=d;

end process; end;

6) What are the different kinds of The test bench? (Dec2011) Stimulus only Full test bench Simulator specific Hybrid testbench Fast testbench7) What is Moore FSM? (Dec2010)

The output of a Moore finite state machine (FSM) depends only on the state and not on its inputs. This type of behavior can be modeled using a single process with the case statement that switches on the state value.

8) Write the test bench for AND gate(Dec2010)entity testand2 isend entityarchitecture io of testand2 issignal a,b,c:std_logic;beging1:entity work.and2(ex2) port map(a,b,c)a<=’0’,’1’ after 100 ns;b<=’0’,’1’ after 150 ns; end;

9) What is testbench? (Dec2009) A test bench is a model which is exercise and verify the correctness of a hardware model.

10) What are the 2 methods to generate stimulus values? (Dec2009) To create waveforms and apply stimulus at discrete time intervals. To generate stimulus based on the state of the entity or output of the entity.

PART B

UNIT I

1. Explain the various steps involvedin CMOS fabrication Process for an inverter. (DEC-2013)

2. (i) Derive the current equation of a MOS device.(10)

(ii) Draw and discuss the MOS transistor model. (6) (DEC-2013)

3. (i)Explain the different steps involved in NMOS fabrication process with neat diagram. (8)

(ii)An NMOS transistor has the following parameters: oxide gate thickness=10nm, relative

permittivity of gate oxide=3.9,electron mobility=520cm2/V-sec and threshold voltage =0.7V. The

permittivity of free space =8.85 x10-14 F/cm. Cal the gate capacitance and also determine the drain

current when VGS=2V and VDS=3 V. The width and length of the channel are 10µm and 0.5µm

respectively. (3+5) (May/June 2012)

4. (i)Explain the small signal model of MOS transistor with neat diagram and expressions. (8)

(ii) Explain the significance of threshold voltage and body effect with equations.(8) (May/June 2012)

5. (i) Explain the operation of NMOS enhancement and depletion mode transistors with neat diagrams.

(6) (Nov 2011)

(ii) Enumerate the different steps involved in twin tub CMOS fabrication process with neat diagrams.

Compare the performance of CMOS inverters fabricated using twin tub process and n-well process.

(7 + 3) (Nov 2011)

6. (i) Explain the characteristics of NMOS transistors with necessary equations for the drain current in

the different regions of operation and necessary diagrams. (8) (Nov 2011)

(ii) Explain the second order effects. (8) (Nov 2011)

7. NMOS fabrication?(NOV 2010)(April 2011)8. Explain PMOS fabrication?(NOV-2010)9. Explain TWIN TUB process with neat diagram?(NOV 2009)10. Explain NMOS current Equation?)(Nov 2009)

UNIT II

1. Design a digital BICMOS circuit that implements the function f=c.k.r + r.k.p. (DEC-2013)

2. (i)Draw the stick diagram for XOR gate.(6)

(ii) Discuss the transfer characteristics, output characteristics, Pull-up-pull down ratios, timing and

fan-out consideration of a CMOS inverter. (DEC-2013)

3. (i) Draw the stick diagram and layout of NMOS inverter (8) (May/June 2012)

(ii)Explain the operation of an inverting and non inverting NMOS supper buffer.(8)

4. (i) Explain the operation of an BiCMOS inverter and two i/p BiCMOS NOR gate.(4+6)

(ii)give a brief note on the theory and design of pass transistor logic (May/June 2012)

5. (i) Draw and explain briefly the lambda based design rules for NMOS and CMOS transistors (10)

(ii) Give a brief note on steering logic (6) (Nov 2011)

6. Draw and explain the operation of

(i) An NMOS and a CMOS superbuffer (5+5)

(ii) BiCMOS two input NAND gate. (6) (Nov 2011)

7. Explain CMOS inverter and derive its DCcharacteristics. (Nov-2010)

8. Explain the process of Stick layout and Lamda based rule.(Nov-2010)

9. (a) Draw the stick diagram for NAND,NOR gates?-8

(b)Draw the stick diagram for NMOS inverter?-8(Dec-2009)

10. Draw and explain the operation of(Dec-2009)

(i) An NMOS and a CMOS superbuffcr

(ii) BiCMOS two input NAND gate

UNIT III

1. Design a 8:1 Mux using dynamic CMOS and clocked CMOS,assess the efficiency of each

implementation. (DEC-2013)

2. Design and draw the CMOS structure and layout diagram for a 4bit barrel shifter. (DEC-2013)

3. (i)Draw and explain the operation of NMOS and CMOS ex-or structure.(8)

(ii)Explain the various methods to improve the speed of four bit adders.(8) (May/June 2012)

4. (i) Explain the operation of 4x4 barrel shifter with neat diagram(8)

(ii) Draw and explain the NMOS and CMOS implementation of a 4 to 1 MUX (May/June 2012)

5. (i) Describe the operation of a dynamic CMOS three input NOR gate with necessary diagrams.

(ii)Explain the operation of a four input tally circuit designed with pass transistors. (Nov 2011)

6. (i) Explain the operation and implementation of a basic four bit adder, Describe the different

approaches of improving the speed of the adders.

(ii) Draw and explain the operation of four bit multiplier array with

necessary diagram and expressions. (8) (Nov 2011)

7. Draw NAND-NAND implementation for following expressionsa. Y=ABC+DEFb. Y=(A+B+C)(D+E+F) (Dec-2010)

8. Draw NOR-NOR implementation for following expressionsa. Y=ABC+DEFb. Y=(A+B+C)(D+E+F) (Dec-2010)

9. Explain the various methods to improve the speed of four bit adders?(DEC-2009)

10. a.Draw static AOI to realize,(6)

y=(AB+CD) ?(DEC-2009)

b. Explain Barrel Shifter?(5)c.Draw and explain the NMOS and CMOS implementation of a 4 to 1 MUX?(5)

(DEC-2009)

UNIT IV

1. Implementation the following function using PAL 16R8.Use minimum no.of product terms to

implement the expression. (DEC-2013)

F1(a,b,c,d)=∑(1,5,7,9,14)

F 2(a,b,c,d)=∑(0,4,8,14)

2. Discuss the significance and working flow of programmable IOB,switch matrix and programmable

logic blocks of any FPGA with neat diagram. (Dec-2013)

3. (i) Explain NMOS NAND-NAND PLA realisation and illustrate its application with example and

neat diagram.(8)

(ii)Write brief note on dynamic logic arrays. (8) (Dec-2012)

4. (i) Describe the implementation of clocked FSM using PLA and write its application. (8)

(ii) Explain the programmable interconnects and I/O blocks used in FPGA. (8) ((Dec-2012)

5. (i) Explain the NMOS NOR-NOR PLA realization with a neat stick diagram. (8)

(ii) Draw and describe the structure of clocked PROM and PAL. (8) (Nov 2011)

6 (i) Describe the implementation of FSM using PLA and also describe the importance of PLA/FSM in

VLSI. (8)

(ii) Explain the logic cells and interconnects used in FPGA. (8). (Nov 2011)

1. Explain briefly PLD and its characteristics?( Nov 2010)

2. Explain the logic cells and interconnects used in FPGA and its implementation?(DEC 2010)

3. Explain the NMOS NAND-NAND PLA realization and illustrate its application with suitable examples

and neat diagrams?(Dec-2009)

4. (a)ASIC design flow explain?(8)

(b)Explain CPLD packages and programming?(8) (Dec-2009)

UNIT V

1. Write behavioural and structural VHDL code and test bench program for JK flip flop.(Dec-2013)

2. Write behavioural VHDL code and test bench program for a 4-bit synchronous gray converter.

(Dec-2013)

3. (i) Write the VHDL description of a 4 bit ripple counter.

(ii) Explain the data types and operators supported by VHDL.

4. (i) Explain the different sequential statements in VHDL.

(ii)Discuss the declaration of VHDL function and procedure with suitable examples. (May/June 2012)

5. (i) Write the VHDL entity and behavioral description of a 4 to 1 MUX and 4 bit counter. (10)

(ii) Explain the different timing controls available in VHDL with suitable examples. (6) (Nov 2011)

6. (i) Write a VHDL code for 1:8 demultiplexer. (10)

(ii) Write a test bench for a FSM used to detect the sequence 1101.(6) (Nov 2011)

1. Write VHDL entity and behavioraldescription of 4 to 1 MUX..(DEC 2010)

2. Write Test bench for FSM used to detect the sequence 1101..(DEC 2010)

3. Explain the data types and operators supported by VHDL.(NOV-2009)

4. Write a program for any 4-Flipflop.(NOV-2009)