Analysis of signal probability in logic circuits using stochastic models

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. I , NO. 3, SEPTEMBER 1993 365

Analysis of Signal Probability in Logic Circuits Using Stochastic Models

Amitava Majumdar, Member, ZEEE, and Sarma B. K. Vrudhula (a.k.a. Sarma Sastry)

Abstract- We analyze the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classillcation of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type Wig determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows us to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits indicate that the methods are applicable for fast estimation of gate signal probabilities in general circuits. Flnally, this work provides a complete generalization of earlier work on relating aggregate structural characteristics of a circuit to its signal probability behavior.

Keywords- Signal probability, stochastic models, testability analysis.

I. INTRODUCTION

IVEN a combinational circuit, we can associate with G each gate 9, a subset V i of input vectors that produce a logic 1 at 9. The subset of vectors that produce a logic 0 at g is, therefore, V - V, where V is the set of all possible input vectors. If we can associate with each vector v E V, a probability (T, of applying II at the primary inputs, we can then associate with each gate g a probability p , that a logic 1 is seen at 9. The relation between p , and (T,'s is given by p , = CuEL:b' oU. The quantity p , is called the signal probability (or 1-controllability) of gate 9.

Signal probability estimates of gates find their main use duringtest generation (ATPG; see [4]), test evaluation (such as

Manuscript received October 14, 1992; revised March 16, 1993. This work was supported in part by NSF award No. MIP-9111206 and by an ACM- SIGDA graduate research scholarship.

A. Majumdar is with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.

S. B. K. Vrudhula is with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721.

IEEE Log Number 9210700.

fault coverage analysis; see [21], [18], [lo]) or during design for testability (DFT) (such as test point insertion; see [15], [17]). The goal of signal probability analysis is to establish a relation among

P1: primary input signal probabilities, P2: circuit structure and function, and P3: gate signal probabilities.

Since exact signal probability computation is NP-complete (see [13]), several heuristics have been developed over the years. These heuristics are either based on a procedural (algo- rithmic) relation among P1, P2, and P3 above (examples are SCOAP [5], the cutting algorithm [16], COP [3], PREDICT [19], [20] and PROTEST [22]) or rely on logic simulations (such as STAFAN [7]).

An inherent characteristic of any procedural heuristic is that its complexity is at least proportional to n, the number of gates in a circuit (i.e., at least O(n)). In general, there exists a trade-off between accuracy of estimates and algorithm complexity. Thus, algorithms with low complexity (such as COP) may yield inaccurate estimates whereas STAFAN, PREDICT, PROTEST and the cutting algorithm guarantee better estimates but take more time.

A. Motivation

Consider a simple adder module which can be used in implementing a function. During synthesis, many instances of this module may be placed in different parts of the circuit. Input signal probabilities for each instance of the adder are expected to be different. Due to this reason, estimating the testability (and, in particular, signal probability) of gates in k instances of the adder may require k different iterations of the same algorithm. The complexity of any such algorithm is at least O(n) (where n is the number of gates in the adder). Therefore, testability estimation for different instances of any logic cell requires executing a linear time (or more complex) algorithm as many times as the number of instances of a logic cell re- quired in a particular realization of the specified function. This problem is compounded by the fact that during synthesis many different realizations of the same function may be evaluated.

In order to alleviate this cost of signal probability evaluation we consider the problem of establishing simple functional relations among the quantities P1, P2, and P3 (listed above). Using such a relation, each combination of input signal probabilities corresponding to an instance of a logic cell in a realization, can be represented by a single point in a space. Internal gate signal probability estimation then involves evaluation of a function at that point (as opposed to running an algorithm).

1063-8210/93$03.00 0 1993 IEEE

366 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 1993

The main use of the results presented in this paper is in the area of fast testability analysis. Combined with a branching process model for fault propagation (see [ 14]), this technique allows fast prediction of aggregate propagation characteristics of faults from different levels of a circuit [9]. These propagation characteristics form the basis for defining a suitable transparency metric for logic blocks under random or pseudorandom test. They also provide a relative measure of observabilities of faults in different levels of a circuit (see [9]).

Such transparency metrics are used extensively during scheduling of data flow graphs for high level synthesis for Built-in Self Test (BIST) [12]. Therefore, the techniques presented in this paper help in speeding up the process of scheduling (and synthesis, in general) where the number and locations of BIST registers are determined. Furthermore, these metrics can also be used in defining suitable testability measures for sequential circuits. Work towards developing such measures is already underway.

B. Literature Review

A number of attempts have been made to relate testability of a circuit to its gross structural and functional Characteristics [6], [l], [8]. Recognizing that, in general, this is a difficult, if not impossible problem, these researchers examined signal probability values for restricted classes of circuits.

Huang and Breuer [6], derive expressions for signal probabilities of gates in irredundant, nand gate circuits where every gate at a given level has the same number of inputs. Using expressions for signal probability that depend on structural characteristics of a circuit, they develop recurrence relations that express the average number of faults detected by a random vector at one level in terms of the average number detected at lower levels (i.e., towards the primary inputs). Conceptually similar results were reported by Agarwal and Agarwal [l]. The circuits considered in [l] are fanout free nand networks with all levels containing gates having equal number of inputs. These restrictions allow the authors to consider only primary input faults. Expressions for signal probability of gates at different levels are used to compute the probability of detecting faults on primary input lines.

More recently, Lipsky and Seth [8] consider tree networks consisting of alternate levels of in-input and gates and n- input or gates. Such circuits are quite similar to the ones considered in [I] , differing in the fact that gates in alternate levels have different numbers of inputs. The authors define a signal probability transfer function (SPTF), which expresses the signal probability of a gate in terms of signal probabilities of gates at the previous level. This function is used to study the limiting behavior of signal probability as the number of levels in the circuit increases.

Testability analysis using aggregate characteristics of general circuits has been reported in [14]. Fault propagation characteristics are expressed in terms of gross structural and functional properties of a given circuit. Based on these expressions fast observability analysis of a circuit can be done. This necessitates prior signal probability estimation of a circuit which is the subject of this paper.

C. Summary and Use of Results

We present a generalization of results presented in [ 11, [8]. The circuits we consider consist of any number of and, or, nand and nor gates, allowing each gate to have any number of inputs. Obviously, the analysis of such circuits cannot be specific to a given circuit, but rather to a population of such circuits described or characterized by certain aggregate structural properties. In other words, a circuit is viewed as being chosen from a given population. The population will be described by viewing fanins of gates as stochastic quantities and each gate being one of and, or, nand, nor with some probability.

Based on this view, each circuit is represented in a space by 1) two parameters whose values are an aggregate of its functional characteristics and 2) a parameter for the distribution of gate fanins. A functional relation depending on these parameters is established between internal gate signal probabilities and input signal probabilities. This function expresses the distribution of signal probabilities of gates in each level in terms of that of gates in the previous level. Thus, we can obtain the distribution of signal probabilities of gates in level i by iterating on this recurrence relation i times. A step- wise procedure for performing this task is outlined in Section IV.B.l.

Although, the analytical techniques presented here are based on reconvergence free circuits, we illustrate their applicability as approximations to general circuits (with possibly many reconvergences) by presenting results of experiments with well-known benchmark circuits as well as other practical circuits. Comparison of observed values of average signal probability with values predicted by our models support our view that even such a simple model can be used for obtaining fairly accurate behavioral characteristics of signal probability in general circuits.

The rest of the paper is organized as follows. In Section I1 we introduce our notation and define some concepts that are commonly used in the paper. In Section I11 we describe the population of circuits considered in the following analysis and define a dual space of circuits to which any given circuit can be transformed. The main analysis characterizing signal probabilities in different levels of a general circuit is presented in Section IV. This includes results for circuits with no restriction on the distribution of gate fanins (Section IV.B), circuits with modified geometric fanin distribution (Section 1V.D) and circuits consisting of only one type of gate (Section 1V.E). In Section 1V.C we show that the results derived in [l], [8] are special cases of those presented in this paper. Results of experiments with different circuits are presented in Section V. Finally, some concluding remarks are offered in Section VI. For the sake of readability all proofs of results are presented in the appendix.

11. NOTATION

Y,: Random variable representing the signal probability of a gate at level i. p: Random variable representing the fanin of a gate. p j m ) : mth moment of the random variable Y,.

MAJUMDAR AND VRUDHULA ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS

pi = p:’): the first moment of K. gp(s): Probability generating function of p. g( , ) (x ) : g ( g ... ( g ( x)) . . .) where g(x) is a function on x.

Dejinition 1: Topological level or level of a gate is the unique number assigned to it by carrying out a topological sort of gates in a combinational circuit. Thus, primary inputs are assigned level 0. The level of any other gate g whose inputs are g1,g2 ,” . ,gr is given by l+max(!!l,!!2,...,!!,) , where ei is the level of gate gi , 1 5 i 5 T .

Definition 2: The probabi l i ty generat ing f u n c t i o n ( p g f ) of a discrete random variableX, denoted by g x ( s ) , is defined as g x ( s ) = C ~ = o s k ~ { X = k}.

Definition 3: A f i x e d p o i n t of a function f (x) is a number p such that p = f ( p ) .

Definition 4: Let f (x) and f’(x) (the first derivative of f) be continuous in the interval ( a , b) , which contains a fixed point p of f(x).

If for some constant c, If’(x)l 5 c < 1 for a 5 2 5 b, then the sequence defined by p , = f (p , -1 ) will converge to p. In this case, p is called an at t rac tor fixed point.

If 1 f’(x)l > 1 for a 5 2 5 b, then the sequence defined by p , = f(p,-l) will diverge from p. In this case, p is called

- n t i m e s

a repeller fixed point.

111. POPULATION OF CIRCUITS

The circuits considered in this paper are combinational circuits consisting of and, nand, or, and nor gates, as well as inverters and buffers. Without loss of generality, we assume that feed forward is not present in these circuits, i.e., all inputs to a gate g at level i are from gates at level i - 1. Circuits with feed forward can be transformed to one without feed forward by replacing each feed forward line with strings of buffers.

Remark: By representing feed forward lines as buffers we view a level of gates as inclusive of feed forward lines crossing that level. This fact is reflected in the results presented. The need for this transformation arises from its end application in estimating fault propagation characteristics in combinational circuits (as indicated in Section LA). From a fault propagation standpoint, it is necessary to consider feed forwards as buffers (see [ 141). This, in turn, necessitates the above transformation even though the proportion of single input gates increases.

To have a uniform representation for the space of circuits described above, we transform a given circuit C into a circuit C’ by applying the rules shown in Fig. 1. The resulting circuit C’ will then have only nand gates and possibly inverters or buffers on inputs and output of each gate. The space of circuits consisting of such gates is called the dual space. It should be noted that any other single gate type (i.e., or, nor, or and) representation can also be used in the above transformation instead of nand gate representation.

Fig. 2 illustrates the transformation of a circuit S into S’. Note that even if there are two concatenated inverters, we do not functionally merge them into a single buffer. This rule is stipulated in order to maintain the identity of each original gate in the dual circuit.

@!-! P : ,. .................................................

I...... ............................................ Fig. 1, Rules for transforming a gate to a nand gate representation.

h

Fig. 2. Transformation of a circuit to its dual.

361

Fig. 3. Stochastic model of a gate with fanin IC in the dual space.

It is clear that for any line .! in C there is a corresponding line e’ in C’ such that the signal probabilities and observabilities of .! and .!’ are the same. Since the signal probability of a gate depends on signal probabilities of its inputs, and thus on its fanin, the population of combinational circuits will be characterized by viewing the fanin of a nand gate in C‘ as a random variable, denoted by p. Thus, the fanins of the collection of gates in a circuit are assumed to be independent realizations of p. Note: We could easily generalize this by making p dependent on the level (see Definition 1) of a gate. This only adds to complicate the expressions but does not alter any part of the analysis that follows.

IV. ANALYSIS OF SIGNAL PROBABILITY

A stochastic model of a gate g at level i of a circuit represented in the dual space is illustrated in Fig. 3. Its fanin k is a realization of the random variable p. We wish to express the signal probability of a gate at level i in terms of the signal probabilities of its inputs at level i - 1. We first obtain such a relation conditioned on p = k.

In the transformed circuit C’ each input and the output of a gate will either have a buffer or an inverter. Such a situation is described by two random variables, o and p , which are

-

368

defined as follows 1 if a buffer is present on an input (output)

* ( P I = { 0 if an inverter is present on an input (output) (1)

such that P{o = 1) = w and P { p = 1) = A. Let Y , denote the signal probability of a gate at level i as

shown in Fig. 2. To express Y , in terms of X-1 we define the following quantities

yi = signal probability of any input buffer or inverter to a gate at level i .

I‘i =signal probability of a nand gate at level i of C’ (see Fig. 3).

Referring to Fig. 3, the random variables 7zyi,j and K - I , ~ , 1 5 j 5 k, are independent realizations of I; and E-1, respectively. Therefore, an implicit assumption is that there are no reconvergent funouts in the circuit. Thus, conditioned on the fanin p = k, we have

= p + (1 - 2P) JJ 7ij. (4) j=1

Using (4) we can express all moments (and therefore the distribution function) of Y , in terms of the proportions of buffers, inverters, and moments of gate fanin distribution. This is stated in the followin theorem.

Theorem 1: Let pCmf denote the mth moment of K (p im) = E [ y m ] ) , vi”’ denote the mth moment of yi (.;(“I =

k } s k ) . Then E[7?1) and be the pgf Of p = C k > O P { P =

m-1

j = O

p =[w + ( - l ) j ( l - w ) ] p Y 1 +

U Equations ( 5 ) and (6) provide a way to compute all moments

of signal probabilities at each level. A simple way to do this is

pure NAND

\

Fig. 4. The (w,X) stochastic dual space and corresponding circuit phenotypes.

to estimate X and w (proportions of output and input buffers, respectively) and the distribution function of gate fanin. Of particular interest at this point is the expected value of the signal probability at level i. Substituting m = 1 into ( 5 ) and (6) results in

Pz = E(Y,) = X + (1 - 2X)gp((l -U) + (2w - l)&-.l). (7)

Equation (7) expresses the average signal probability at level i (p i ) in terms of the average signal probability at level i - 1 (p i - - I ) . Naturally, this depends on the various types and fanins of gates present in the circuit. These dependencies are captured in the parameters w, X and gp. Before proceeding to take a closer look at pi, let us see how one may interpret the parameters w and A.

A. Dual Space in Terms of w and X and Circuit Phenotype Classijication

The dual circuit space described in Section I11 can be represented as a two-dimensional (w, A) space as shown in Fig. 4(a). We should note that such a compact representation of the complete dual space (which is the space of all realizable circuits) is possible only because of our stochastic representation of a gate in terms of the random variables U and p (see Fig. 3). Due to this reason we shall call this space as the stochastic dual space (SD space) of circuits. Since gate fanin distribution is not included in this representation, each point (a ,b ) in this space, therefore, represents a class of circuits with w = a and X = b.

As a consequence, the identity of each individual circuit is lost. Instead, we consider its characteristics only in terms of the two parameters w and A. Its justification derives from ( 5 ) and (6), where the distribution of signal probabilities in a circuit are expressed in terms of these parameters.

The extreme points of this space represent circuits having only one type of gate. For example, the point (U, A) = (1 , l ) represents circuits, which when transformed, contains nand gates with buffers at inputs as well as outputs. That is, the original circuits consist only of nand gates. Similarly, the point ( w , X ) = (O,O), (w ,X) = ( 0 , l ) and (w,X) = (1,O) represent circuits with all gates being nor gates, or gates and and gates, respectively. We will refer to such circuits as pure circuits.

MMUMDAR AND VRUDHULA ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS

-

369

From Fig. 4(a) it seems natural to partition the ( U , A) space into four regions as shown in in Fig. 4(b). These regions define four different circuit phenotypes. The word phenotype is used in order to emphasize the similarity among gross signal probability characteristics of circuits within each region. This will become clear as our discussion progresses.

The four regions, named R1 through R4, and the corresponding phenotypes are defined below.

R I = { ( U , A) 1 0 5 w 5 0.5,O 5 A 5 0.5) nor-type R2 = { ( w , A) 1 0 5 w 5 0.5,0.5 5 A 5 1) or-type R3 = { ( U , A) I 0.5 5 w 5 1,0.5 5 A 5 1) nand-type R4 = { (w ,A) 1 0.5 5 w 5 1 ,0 5 A 5 0.5) and-type.

(8) The partitioning of the ( U , A) space and the corresponding

classification of a circuit as being one of the four types is purely intuitive at this point. The terms are used to con- vey a predominance of one particular type of gate. A more quantitative characterization and classification is possible by examining the behavior of pi. We study such a classification next.

B. Signal Probability Behavior in Different Circuit Types

We first define two functions, h and f as follows.

From (7) we see that expected signal probability at level i

To understand the behavior of pi we need to examine the

Lemma 1: For a given circuit, let ( w , A) be its representa-

if (w, A) E R4 then h is monotonically increasing and convex. if (w,A) E R2 then h is monotonically increasing and concave. if (w ,A) E R3 then h is monotonically decreasing and concave. if(w, A) E R 1 then h is monotonically decreasing and convex. 0

Lemma 2: For a given circuit, let (w, A) be its representa-

a) If ( U , A) # ( 1 , O ) and if (w, A) # (0 , l ) (i.e., the circuit is neither pure and nor pure or-) then h has exactly one fixed point (see Dejnition 3) in the interval (0 , l ) .

b) If (w , A) = (1,O) or (w, A) = ( 0 , l ) then h has exactly two fixed points at s = 0 and at s = 1, respectively. 0

Fig. 5 shows the various possible shapes of the function h as described by Lemmas 1 and 2. The following theorem shows the behavior of the expected signal probability in each of the regions.

properties of h and f . These are stated below.

tion in the stochastic dual space.

tion in the stochastic dual space.

fixed point

0 I o I 0.5

0.5 I 1 I 1 (o,h) = (091)

fixed point

0.5 I o I 1

0 0.5 P 1

Fig. 5. Shapes of h for different circuit types.

Theorem 2: For a given circuit let ( U , A) be its representation in the stochastic dual space such that w, A E (0 , l ) . Further, let p be the unique fixed point of h. Then

a) ~ i - 1 = p implies pi = p. b) if (w,A) E R2 U R4 then i) pi-1 p * pi E ( P , P ; - I ) . c) if ( U , A) E RI U RS then i) pi-1 p and ii)

0 Let us take a closer look at the implications of Theorem

2. Consider the situation where (w,A) E R2 U R4 (Theorem 2b). This situation represents circuits that are either or-type or and-type (see Figs. 4(b) and 4(d)). Theorem 2 asserts that if p a - l p for some i then the sequence of expected signal probabilities is monotonically decreasing and bounded below by p , i.e., pi-1 > pi > pi+] > . . . > p. These observations are summarized in the following lemma.

Lemma 3: If ( w , A) E R2 U R4 then limi+oo pi = p, where 0

Note that in the two extreme cases where (w,A) = ( 1 , O ) (pure and) or (w,A) = ( 0 , l ) (pure OR), h has two fixed points, namely, s = 0} and (s = 1. When(w, A) = ( 1 , O ) and PO # 1 then s = 0 is the attractor fixed point (see Definition 4) of h. That is, if the expected signal probability at the primary input is not equal to 1, expected signal probabilities at successive levels tend to 0 as the number of levels increases. This is easily seen by examining Fig. 5(a). Similarly, when (w, A) = (0 , l ) and PO # 0, then s = 1 is the attractor fixed

Pa-1 > P 3 Pi < P.

p is the unique fixed point of h.


point of h (see Fig. 5(c)) and expected signal probabilities tend to 1 as the number of levels increases.

Now, consider situations where (w, A) E R1 U R3 (Theorem 2c). This situation represents circuits that are either nor-type or nand-type (see Figs. 5(f) and 5(h)). In such cases, Theorem 2 asserts that the expected signal probabilities at two consecutive levels lie on either side of p , i.e., if pi-1 p and vice versa. This implies that signal probabilities in alternate levels lie on the same side of p . Because of this altemating behavior of pi, we need to examine the function f (see (10)) which relates p; to pi-2 (i.e., pi = f(p;-2)).

Lemma 4: Let h be a monotonic function on set S ( c 8) to itself and let f(s) = h(h(s ) ) . Then

a) if p is the unique fixed point of h then p is also a fixed

b) q is a fixed point of f if and only if h(q) is a fixed point o f f . 0

Thus if q l , q 2 , . . . , q r , q r + l ( = p ) , for { r 2 01, are fixed points of f , then h ( q l ) , h(qZ), . . . , h(q,) are also fixed points of f . Hence f has an odd number of fired points when (w ,A) E R I U R3 (since h(qT+l) = qr+l). Furthermore, in this case h is monotonically decreasing and q; and h(q;), for 1 5 i 5 r lie on opposite sides of p (see Theorem 2c). Therefore, we can order the 2r + 1 fixed points as follows. Let 91 < q2 < . . . < q, < q,+l(= p ) , then q,+l(= P) < h(q,) < h(qT-l) < . . . < h(q1). The following lemma shows how the number of fixed points of f depends on h’(p).

LRmma5: Let(w,A) E (RlUR3)-{(0,0) , ( l ,1)}andlet 41 < ... < q, < q,+i(= p ) < h(q,) < . . . < h(q1) be the 2r + 1 fixed points of f , for r 2 0.

point of f.

1) If -1 < h’(p) < 0 then

a) r is even ( r = 2k) , i.e. the number of fixed points of f is a number of the form 4k + 1, for some integer k 2 0.

attractor fixed points (see Definition 4) of f

fixed points of f .

b) qr+l(= ~),~,-1,h(q,-1),~~-3,h(q,-3),..., are

while qr , h(q,), qr--2, h(q,-z) , . . . , are repeller

2) If h’(p) < -1 then

a) r is odd ( r = 2k + l), i.e., the number of fixed points of f is a number of the form 4k + 3, for IC 2 0.

b) qr+ l (= P), q,--l, h(q,--l), ~ ~ - 3 , h(q,-3), . . . , are repeller fixed points of f while q,, h(q,) , q r - 2 , h(q,-z) , . . . , are attractor fixed points of f . 0

The shape of f and the nature of its fixed points as described in Lemma 5 are shown in Fig. 6 for r = 2 and r = 3. From Lemma 5 we can clearly see the behavior of pi when ( w , A) E RI U R3. For example, suppose that pi E ( q j , q J + l ) , for some i and j , where q j and qj+l are two consecutive fixed points of f . Suppose further (without loss of generality) that qj is an attractor and q j+ l is a repeller. If -1 < h’(p) < 0 then the sequence of average signal probabilities p;+2, p;+4, . . . will be a monotonically decreasing sequence which converges to q j

Fig. 6. Shapes of f for T = 2 and T = 3.

while the sequence p i + l , p;+3,. . . will be a monotonically increasing sequence which converges to h(q j ) . The exact opposite situation occurs if h’(p) < -1. These results are summarized in the following lemma.

Lemma 6: Let (U, A) E R1 UR3 - {(O,O), ( 1 , l ) ) . Further, let q be an attractor fixed point of f which is closest to po, i.e., there is no fixed point in between q and PO. Then

l imi+,= p2; = q for i = 0,1 , . . . and 0

Lemmas 4-6 provide a complete characterization of average signal probabilities when ( w , A) E RI U R3.

Using the Results: These results can be used in defining techniques for estimating signal probabilities (as well as their limiting behavior) in circuits. For a given circuit, the steps involved in determining expected signal probabilities are as follows.

limi+m pzi+l = h(q) for i = 0,1 , . . ..

Transform the circuit to obtain its representation in the stochastic dual space (or SD space). Estimate parameters w and A. Determine the distribution of gate fanins ,B in the circuit and obtain its pgf g p ( s ) . Determine function h using the relation given in (9). Determine po, the expected primary input signal probability. Compute p; as h(;)(po) (ith order composition of h). order to determine the limiting behavior of expected

signal probabilities, we need to determine the fixed points of functions h and f depending on the region of the SD space that the circuit belongs to. Assuming w, A and g p ( s ) have been estimated we can define the following steps for determining the limiting behavior of expected signal probabilities.

1) If ( U , A) E R2 U R4 then determine the unique fixed point p of function h. This can be done either analytically or by using a numerical method. From Lemma 3, expected signal probabilities of successive levels approach this point p .

2) If ( w , A) E R 1 U R3 then we need to examine both functions h and f . In general, analytical determination of the number and location of fixed points of the function f , is difficult. Numerical methods may be used for this purpose. Thus,

Determine po, the expected primary input signal probability. Estimate (numerically) the largest fixed point q 5 po and the smallest fixed point q’ 2 ,UO of the function f .

a)

b)

MAJUMDAR AND VRUDHULA: ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS 37 1

c) d)

Determine slope of f at q.

If f’(q) 5 1 then q is an attractor fixed point and q’ is a repellor. In this case set &,,, = q.

is a repellor fixed point. Therefore, q’ has to be

For the levels consisting of n [m]-input nand gates the pmf Of p can be expressed as

Otherwise, if f’(q) > 1 then we know that q (12) 1 k = n [ m ] ’

an attractor (since q and q’ are consecutive fixed points). In this case set leven = 4’.

Expected signal probabilities in even-numbered levels converge to C,,,, .

Similar steps can be defined for odd-numbered levels. We start from p1 instead of po (p1 can be determined by computing h ( p 0 ) ) and determine the attractor fixed point [odd closest to p1.

It is important to note that all the results up to this point are general in the sense that no particular distribution of fanins is assumed. Further results can be obtained for circuits whose gate fanins follow a known distribution or circuits consisting only of one type of gates (pure circuits). Before we present these results we first show that the circuits considered (and therefore the results presented) in [ 11 and [8J are special cases of those derived in this paper.

e)

C. Analysis of Previously Studied Circuits as Special Cases

Consider a logic tree consisting of nand gates each with n inputs (as studied in [l]). In this case, ( U , A) = (1, 1)and the distribution of /3 can be expressed as

0 k # n 1 k = n ’ P { p = k } =

This implies that g p ( s ) = Cr=lppk~k = s”. Therefore, from (9) and (lo), we get h(s) = 1 - sn and f (s) = 1 - (1 - sn),. Such a circuit lies in region R3 of the dual space and according to Lemmas IC and 2h has one fixed point p E (0,1), is monotonically decreasing, and concave. Furthermore, h( 0) = 1 and h( 1) = 0. These are verified easily from the expression for h above.

Therefore, in this special case, f(0) = h(h(0) ) = h(1) = 0 andf(1) = h(h(1)) = h(0) = 1. Thus f has fixed points at s = 0 and s = 1. This, combined with the result of Lemma 4 tells us that f has at least three fixed points at s = 0 , p , 1. For n > 1, we can see that f’(0) = f’(1) = 0 < 1. Using these facts we can obtain the signal probability of gates in each level. For each n we can obtain p by solving for s in the equation h(s ) - s = 0. Thus for n = 2 we get p = 0.618 as found in [l], [2] first and subsequently in [8].

A more general form of the above circuits (regular and-or trees) is considered by Lipsky and Seth in [8]. These circuits, when transformed, are represented in the dual space as pure nand trees, i.e., (U, A) = (1 , l ) . In [8], the trees considered, have altemate levels of n-input and gates and m-input or gates. This translates to a nand tree consisting of altemate levels of n-input gates and m-input gates. An implicit assumption is that if level 0 consists of or gates, we consider the circuit from level 1 onwards.

Thus we have two different p g f s for the two distributions. Labeling the two random variables as p, and ,& we have gp, (s) = s j and hj(s) = 1 - sj where j = m, n. Thus the results of [8] can now be obtained by assuming the degenerate p m f for fanins given by (12).

The function f relating pi to pi--2 can be expressed in two ways. Distinguishing between the two forms by labeling them f,(s) and fn(s) we can express these as f,(s) = 1 - (1 -

These functions are identical to the signal probability transfer functions (SPTF’s) considered in [8]. For these functions as well, we find that fL(0) = f&(l) = 0 whenever m and n are greater than 1. Let us consider only the case where gates in the first level have m inputs. The expected signal probabilities of all even numbered levels can be characterized by the function f, (s) and that of the odd levels by f, (s). The respective fixed points p , and p , of the two functions f,(s) and f,(s) in the region ( 0 , l ) are determined by m and n.

It is clear that if m = n then p , = p , = p which is in accordance with our model. If m # n then p , need not equal p, . Using these functions we can obtain signal probability of individual gates in each level of a circuit. We can also determine the limiting behavior of signal probabilities. Consid- ering only even numbered levels, expected signal probabilities in these levels are obtained by repeated compositions of the function fm(s). As shown in [8], this function has three fixed points at s = 0 , l and p out of which s = 0 and s = 1 are attractor fixed points. Thus depending on po, expected signal probabilities at even-numbered levels either approach 1 or 0.

s,), = h,(h,(s)) and fn(s) = 1 - (l-sn), = h,(h,(s)).

D. Special Case: Fanin Distribution from Parametric Family

Analytical results derived in Section 1V.B are applicable to all circuits and do not make any assumption about gate fanin distribution. If a given circuit belongs to either region R2 or region R4 in the SD space (see Fig. 3(b)), then we can easily determine expected signal probability in all its levels as well as the limiting value of expected signal probability from the corresponding function h. This is discussed in Section IV.B.1. However, when a circuit belongs to either RI or R3 regions, the limiting behavior of expected signal probability is dependent on characteristics of the corresponding function f . As is mentioned in Section 1V.B. 1, analytical determination of the number and location of its fixed points is difficult and requires numerical algorithms.

In this section, we specialize our analytical results of Section 1V.B for the case where the distribution of p is assumed to be a member of a parametric family of distributions. Our choice of the parametric family is based on intuition as well as experimentally observed phenomena. Study of well-known ISCAS ’85 benchmark circuits and other circuits revealed that the proportion of gates in a circuit, with two or more inputs decreases with increase in fanin. However, the proportion

-


? Mod. G e o m fit

b = 0.122699 8 = 0.443580 0.3

i ; ; H i l o

Fanin

o:l\cfualdistdbution *: Mod. GeomMxic fit 2 0.4 8 = 0.232376

b = 0.150289

Gates: 443 0.2

'1 2 3 4 5 6 7 8 9 10 Panin

Fig. 7 . Modified geometric fit for gate fanin in a Viterbi decoder circuit and C880.

0: Actual dimibution

a = 0.131868 b = 0.084942

Gates: 587 0.4

0.2

Panin

0: Actual distribution 0.6

8 = 0.277778 b = 0.082353

Gats: 881 0.2

' 1 2 3 4 5 6 7 Panin

Fig. 8. Modified geometric fit for gate fanin in Cl355 and an 8-bit multiplier.

of single input gates varies independently of proportions of multiple input gates.

This led us to adopt the family of modz$ed geometric distributions to represent the actual distribution of gate fanins in a given circuit. The reason for selecting modified geometric distributions becomes clear when we examine its p m f given by

(13) k = l

P{P= k } = a , { ( 1 - a ) ( l - b)b"-2, k 2 2 '

The parameter a allows us to accomodate variations in the proportion of single input gates. For k 2 2, we see from (13) that, for b E (0, l ) , probability values decrease with k. Given a circuit, maximum likelihood estimates of parameters a and b are obtained from its structural representation. Comparison between actual distributions of gate fanins in several circuits and corresponding modified geometric fits are illustrated in Figs. 7-10.

Our concern is mainly with circuits belonging to RI U R3, which are characterized by monotonically decreasing h. For these circuits, the actual difficulty lies in determining the

0: Acmd distrihticm

8 = 0.498864 b=0.285251

Gates: 913 0.1

'1 2 3 4 5 6 7 8 9 10 Panin

*: Mod. Geomchic fit 8 = 0.468085 b = 0.234694

6 3 B b l O Fanin

Fig. 9. Modified geometric fit for gate fanin in Cl908 and C2670.

0: Actunl dishibutim *: Mod. Ge0"e

8 = 0.428999 b = 0.247830

- 2

7 8 9 1 0 Panin

0: Actual distribatim

a = 0.401481 b = 0.201368

0.4

0.2 Gates: 3719

Panin

Fig. 10. Modified geometric fit for gate fanin in C3540 and C7552.

number and locations of fixed points of the function f(s) = h(h(s)) .

Under these conditions, the pgf of P is given by

as + (1 - a - b)s' 1 - bs g d s > =

and the corresponding function f can be expressed as

where

A ( s ) = X + ( 1 - w + ( 2 ~ - l)s)(a(l - 2X) - bX)+ (1 - w + (2w - l )S) ' ( l - 2A)(1 - a - b)

and B ( s ) = l - b ( l - w + ( 2 w - l ) s ) , C1 = (1-2X)(2w-l), C, = ( 2 ~ - l)(bX + a ( 1 - 2X)), C3 = WX + (1 - b)( l - w ) ( l - A), c4 = 1 - b(1 - U ) , c5 = b(2W - 1).

Since A ( s ) and B(s) are second andjrst degree polynomials in s, respectively, it is clear from (9) that the numerator and denominator of f are, respectively, fourth and third degree polynomials in s. The general form of f in this case is described in Lemma 7.

373 MAJUMDAR AND VRUDHULA: ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS

P P 9 P h(qJ

Fig. 11. Shapes of f for circuits with modified geometric gate fanins. 0 P 1 0 P I

7: Let E R3 and let P be a modified geometric rv with parameters a and b. The corresponding function f has either one fixed point or three fixed points

Fig. 12. Shapes of f for pure nand circuits with modified geometric gate fanins.

in (0,1]. 0 Possible shapes of f are illustrated in Fig. 11. The exact

number of fixed points that f has (either one or three) is determined by h‘(p) as shown in Lemma 5, where h is obtained by substituting (14) in (9) and p is its unique fixed point in (0 , l ) . Characteristics of f and limiting behavior of expected signal probabilities in such circuits can be summarized as follows.

P1 f has exactly one fixed point p E (0 , l ) if and only if -1 2 h’(p) < 0. Furthermore, p is an attractor fixed point. This follows from the fact that f(0) 2 0 whenever h(0) 2 0 and from Inequality 22, we know that h(0) 2 0. In this case, (as with circuits in R2 and R4)

lim pi = p i-+ 00

regardless of whether i is even or odd. p2 f has exactly three fixed points p l , p , p2 E [0, 11 if and

only if h’(p) < -1, where p l < p < p ~ , P I = h ( p 2 ) and p2 = h(pl). In this case, if U , X E (0, l ) , then p l

and pa are both attractor fixed points. Assuming PO < p, we get

lim p2i = p l

lim p2i+1 = p 2 .

a-+ 00

i-00

E. Single Gate Type (Pure) Circuits

One shortcoming of the analysis presented above is that some results (such as Lemma 5 and item P2 in Section 1V.D) pertaining to circuits in R1 U R3 do not apply to pure nor and nand circuits. This is because, functions h and f for pure and impure circuits, respectively, differ in some of their characteristics. These characteristics and their consequences are discussed in this section. Since the difference between signal probability characteristics of pure nor and nand circuits is little, we confine ourselves to a discussion of pure nand circuits only.

The main difference between a pure nand circuit and an impure nand-type circuit lies in the corresponding function h. For a pure nand circuit, (U, A) = (1,l). Substituting this in

h(s ) = 1 - gfJ(s). (16)

Combined with the fact that gp(0) = 0 andgp(1) = 1, we

(9), we get

get h(0) = 1 and h(1) = 0. With f defined as in, we get

f(0) = h(h(0)) = h(1) = 0 f(1) = h(h(0)) = h(0) = 1. (17)

Therefore, s = 0 and s = 1 are fixed points of the function f . When a nand type circuit is not pure nand, h(s) , f(s) E

(0 , l ) whenever s E [0,1] (see Inequalities 22 and 23) and therefore s = 0 and s = 1 cannot be fixed points. Another consequence of these inequalities (refer to the proof of Lemma 5 ) was that the first fixed point of f is always an attractor fixed point.

In the case of pure nand circuits, however, the first fixed point off is always q1 = 0. Due to this reason q1 need not be an attractor fixed point (in fact we provide conditions for which s = 0 and s = 1 are repellor fixed points). Therefore, Lemma 5 is applicable to pure nand circuits only if f’(0) < 1. This condition can be tested easily. Since f(s) = h(h(s ) ) , using (16), we get f‘(0) = h’(l)h’(O) = gb(O)gb(l) = P { p = l}E[P]. When f’(0) > 1 then we can obtain a characterization similar to that of Lemma 5. This is summarized below.

1) If -1 < h’(p) < 0 and f’(0) > 1, then 0 is a repellor and p is an attractor. This means that there are an even number of fixed points between s = 0 and s = p (see proof of Lemma 5). Therefore, the total number of fixed points including s = 0 , p and 1, is odd (of the form 4k + 3.

2) If h’(p) < -1 and f’(0) > 1, then p is a repellor fixed point. Since both s = 0 and s = p are repellors, there must be an odd number of fixed points between s = 0 and s = p. Therefore, in this case, the total number of fixed points including s = 0 , p and 1, is odd (of the form 4k f 1.

Pure NAND Circuits with Mod$ed Geometric Fanins Specializing the distribution of /3 as in Section IV.D, we achieve further simplifying restrictions on characteristics of f . Combining Lemma 7 and (17), we conclude that, given a pure nand circuit such that P is a modified geometric rv, f has exacrly three fixed points at s = 0 , p and 1 (where p is the unique fixed point of h). Possible shapes of f are illustrated in Fig. 12.

We can now derive conditions for characteristics of the three fixed points. Using Lemma 5, we know that when -1 < h’(p) < 0, then p is an attractor fixed point of f . This implies that s = 0 and s = 1 are both repellors. On the other hand, when h’(p) < -1, p is a repellor. In this case, s = 0 and s = 1 are attractor fixed points of f .

The above statements in terms of h’(p) can be equivalently stated as follows. When f’(0) < 1 (i.e., s = 0 and s = 1 are attractor fixed points), p is a repellor fixed point. Similarly, when f’(0) > 1, p is the attractor fixed point.

314

Circuit 1 N = 2237

A = 0.32. w = 0.34

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 1. NO. 3, SEF’rEMBER 1993

I Circuit 3 N = 2337

X = 0.39, w = 0.49

Circuit 2 N = 2093

A = 0.46. w = 0.47

A simpler characterization of f can be obtained as follows. For pure nand circuits with modified geometric @, the function h is expressed as

as + (1 - a - b)s2 h(s) = 1 - g p ( s ) = 1 -

1 - bs

(18) (1 - ~ ) [ l + ~ ( 1 - U - b)]

1 - bs - -

(see (14)). We know that f ’ ( 0 ) = h’(l)h’(O) = f’(1). Using (18),

we get h’(1) = and h’(0) = -a. Thus f ’ ( 0 ) =

@&J. Solving the inequationf’(0) < 1, we get a(2 - a ) + b(1 - a ) < 1 + a + b < 1. Similarly, for f ’ ( 0 ) > 1, we get the condition a f b > 1. These results are summarized below. For a pure nand circuit where p is a modified geometric rv with parameters a and b

1) if a + b > 1 then p is an attractor fixed point and limi-oopi = p ,

2) if a + b < 1 then 0 and 1 are the attractor fixed points and assuming po p , limi+m p2i+1 = 0 and limi--toop2i = 1.

Similarly, f ’ ( 0 ) = 1 if and only if a + b = 1. This is the special case where gate fanins are distributed according to a standard geometric distribution. It can be shown easily that in this case f ( s ) = s, i.e., every point s E [0,1] is a fixed point.

Summarized below are the main characteristics of expected signal probability in nand-type circuits with modified geometric gate fanins.

1) Behavior of expected signal probabilities falls into two

Either expected signal probabilities in all levels converge to a value p E (0 , l ) or expected signal probabilities in alternate levels diverge from p such that those of even numbered levels converge to y1 p (or vice versa).

2) The main difference between pure nand and (impure) nand-type circuits in their respective characteristics of expected signal probability behavior is as follows. For impure nand-type circuits, when expected signal probabilities diverge from p (see b above) then the points q1 E ( 0 , p ) and 42 E (p , 1). Whereas, for pure nand circuits, y1 = 0 and q2 = 1. Thus, in pure nand circuits we find that expected signal probabilities in alternate levels approach 0 and 1, respectively.

broad classes.

a)

b)

V. EXPERIMENTAL RESULTS

We now present some experimental results in support of our theoretical models. We restrict our attention to circuits with gate fanins distributed according to a modified geometric law. Theoretical results for these circuits are presented in Section 1V.D. Results for circuits with gate fanins following other distributions (although omitted from this discussion) can be easily obtained using the formulae given in Section 1V.B.

Experiments conducted by us involved the following steps. For a given circuit we first estimate X and w (parameters that describe its phenotype) and a and b (parameters for gate fanin distribution). Next we simulate T input patterns and record the number of times ti that gate gi has a logic ‘1’ at its output. This is done for all gates in the circuit. The ratio $ is used as our estimate of signal probability of gate gi. This procedure is used in STAFAN [7] and is known to provide fairly accurate estimates of gate signal probabilities. Next we compute $i which is our experimental estimate of expected signal probability at level i. This is done by averaging (over all gates in level i) individual gate signal probabilities estimated in step 2. We then compute theoretical values of expected signal probabilities pi for level i using (9) and (1 1) given in Section 1V.B. In order to illustrate the accuracy of our theoretical estimates we also generate the standard deviation of gate signal probabilities at level i. This can be computed as

SD(Y, ) = Jm = Jm. For

pj2) we use the recurrence relation of ( 5 ) with m = 2. Experiments were conducted on both randomly generated

circuits as well as on well-known benchmark and other practical circuits. For generating random circuits we used twelve different values for X and w (three each from the four regions RI through Rq; see Fig. 3). Values for fanin distribution parameters were varied without any particular constraints. Results of experiments with these circuits are presented first.

We simulated between 2000 and 3000 input patterns with primary input signal probabilities po set to 0.5. (Results for other settings of po can be found in [9]) Observed values C;i

and estimated values of pi of expected signal probabilities for these cases are presented in Tables I-IV. In the following tables N indicates the number of gates in the corresponding circuit.

We can see that for most of the above cases, observed values of expected signal probability are quite close to theoretical estimates. Even for cases, where observations do not match theoretical predictions, we can see that experimental values

MNUMDAR AND VRUDHULA: ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS

Viterbi decoder C880 N = 306 N = 4 4 3

X = 0.27, w = 0.59 X = 0.39, w = 0.69

~

375

C1355 N = 587

X = 0.88, w = 0.99

TABLE II

ESTIMATED STANDARD DEVIATION OF SIGNAL PROBABILITIES AT DIFFERENT LEVELS OF THREE or-TYPE CIRCUITS (REGION R2) FOR po = 0.5.

ESTIMATED AND OBSERVED VALUES OF EXPEXTED SIGNAL PROBABILITIES AND

R I II Circuit 6 Circuit 4 Circuit 5 N = 1974 11 N = 2220 11 N = 2228

11 I A = 0.85. w = 0.22 11 X = 0.93.w = 0.30 11 X = 0.76.w = 0.40 11

TABLE I11 ESTIMATED AND OBSERVED VALUES OF EXPECTED SIGNAL PROBABILITIES AND

ESTIMATED STANDARD DEVIATION OF SIGNAL PROBABILITIES AT DIFFERENT LEVELS OF THREE ~ u ~ ~ - T Y P E CIRCUITS (REGION R3) FOR po = 0.5.

TABLE IV

ESTIMATED STANDARD DEVIATION OF SIGNAL PROBABILITIES AT DIFFERENT ESTIMATED AND OBSERVED VALLIES OF EXPECTED SIGNAL PROBABILITIES AND

LEVELS OF THREE Und-TYPE CIRCUITS (REGION R4) FOR po = 0.5.

H I Circuit 10 [[ Circuit 11 11 Circuit 12 I N = 2009 11 N = 2306 11 N = 2375

11 I X = 0 . 2 1 . ~ = 0.83 11 X = 0.30. w = 0.93 11 X = 0 . 4 1 , ~ = 0.78 11

f i i de within one standard deviation of theoretical predictions pi. In other words, for all the cases above !&d << 1. For pure circuits (see [9], [ 113) we found that our theoretical estimates of average signal probability are even better than those obtained for impure circuits (Circuits 1-12). This is explained by the fact that the contribution of different gate types to the variance of signal probabilities is not present in pure circuits.

S D (Y, )

C1908 C2670 N = 913

X = 0.85. w = 0.99 N = 1502

X = 0.49, w = 0.87

The collection of results presented so far is related only to randomly generated circuits. This in itself does not illustrate the applicability of these techniques to general circuits. In order to further test our model we conducted similar experiments with a set of well-known circuits with possibly many reconvergences. The first circuit is part of a Viterbi decoder implementing a butterfly network. Four other circuits, namely C880, C1355, C1908, and C2670, were selected from the set of ISCAS '85 benchmarks. Results of experiments with these circuits are presented in Table V.

It is clear from this table that even for general circuits with many reconvergences (as is the case with these circuits) our theoretical predictions of average signal probability agree remarkably well with observed values. Although observed and predicted values are not equal, we find that in a majority of cases (i.e., in different levels in different circuits) they are quite close. Furthermore, a general observation is that for all levels in all the circuits, experimental values fall well within one standard deviation of corresponding theoretical values.

One must note that this agreement exists in spite of several approximations made in our analysis. However, variances in


some levels can be quite large. This is mainly the effect of aggregating (possibly large) variations in parameter values (over different levels) into a few parameters (such as a single parameter X for a whole circuit).

Further improvements in accuracy of predictions (with neg- ligible increase in computational effort) may be obtained by considering heterogeneity among levels, in terms of gate- type and fanin distributions. This would remove the effects of aggregating parameter values and theoretical predictions would be expected to track these variations among levels, more closely. Another way of improving accuracy is to cluster different gates or levels so that parameter variations within a cluster is low. Our techniques can then be used to predict signal probability distributions within each cluster and the results can be combined later. Development of such clustering techniques is part of the future work in this area.

Based on these results we conclude that the models and techniques developed here are applicable to general circuits which may have many fanout reconvergences. The fact that reconvergence is not explicitly considered in our models, does not seem to affect the results significantly.’ However, in the worst case, depending on structural and functional characteristics of a given circuit, line reconvergences can cause theoretical predictions to deviate significantly from observed values.

We now address the question of determining the complexity of our procedure. It is clear that we need values of parameters A, w, a and b (and, in general, parameters of gate type and gate fanin distributions). A maximum likelihood (ML) method can be used to obtain these estimates. Data for ML estimation is extracted from a given circuit by making one pass of that circuit. From this it would appear that, for a circuit with n gates, an O ( n ) algorithm has to be executed before signal probability estimates can be obtained. This is misleading, since for a circuit (or module in the case of cell-based synthesis procedures), these parameters do not change and they need to be estimated only once (they can be stored as attributes of that circuit).

The only parameter that may change is the set of primary input signal probabilities. For each primary input condition, different moments of signal probability at successive levels can be estimated using repeated composition of a simple algebraic function. Thus, estimation of the first k moments of signal probability at levels 1 through i (given the corresponding moments at level 0) requires IC x i different computational steps (see ( 5 ) and (6)). This is because the jth moment can be used in computing the j + lth moment. Furthermore, since the first four moments usually provide an accurate estimate of the distribution, k is seldom greater than 4.

Based on this reasoning, we see that the complexity of our technique is O ( m ) for a circuit with m levels and is therefore independent of the number of gates in the circuit. In general,

‘ A similar observation was made in the context of fault propagation characteristics in [9]. A study showed that the proportion of faults that propagate or fail to propagate due to line reconvergences is usually less than 5% and therefore the effects of reconvergences may not be significant. The presence of redundant faults, however, can be attributed primarily to the presence of reconvergences. The above low figure of 5%. thus indicates that only a small proportion of the faults in the circuits studied, are redundant.

for a circuit with m levels and n gates, m << n. Due to this reason and based on our experimental results, we conclude that the techniques developed here may be more suitable for signal probability analysis during circuit synthesis and, in general for fast signal probability evaluation, than procedural heuristics used hitherto.

VI. CONCLUSIONS

In this paper, we present a new methodology for statistical characterization of signal probabilities of gates in different levels of a circuit. We establish a relationship between the distribution of signal probabilities in a level and aggregate structural and logical Characteristics of a circuit. This work generalizes earlier research in relating signal probability to such aggregate characteristics [I], [8] (see Section 1V.C).

We define a transformation by which a circuit can be represented in a dual space consisting of only nand gates, buffers, and inverters. According to this transformation a gate is represented as a nand gate with buffers or inverters at its inputs and output. Based on this, we develop a new classification of circuits. Thus, a circuit is viewed as belonging to one of four basic circuit-types, namely and-type, or-type, nand-type and nor-type. After transforming a circuit, its “type” can be determined by estimating two parameters.

The significance of this classification is that each circuit class exhibits its unique characteristics of signal probability behavior. Thus, by simply estimating two parameters from a circuit, we can determine some basic behavioral patterns of signal probabilities. Further characterization requires the distribution of gate fanins. This is determined from the circuit specification.

The distribution of signal probabilities in a level is expressed in terms of its moments which are functions of gate fanin distribution and the two parameters that determine its circuit type. We show that the limiting behavior of expected signal probabilities in successive levels of a circuit is determined by the fixed points of a function that expresses the expected signal probability of a level in terms of the expected signal probability of the previous level.

Results of experiments with several circuits (such as ISCAS ’85 benchmarks and other circuits) illustrate the effectiveness of this methodology in approximating gate signal probabilities in general circuits as well, i.e., circuits with possibly many reconvergences. Given that the complexity of these computa- tions is proportional only to the number of levels in a circuit (as opposed to the number of gates; see Section V), this technique may be more suitable for fast testability estimation in a synthesis environment than the procedural heuristics currently used.

Future work includes extending these models to study and possibly include the effect of reconvergence on signal probability behavior. Some results in this direction can be found in [9]. Research towards applying these results for weighted random pattern generation and higher level testability evaluation is already underway.

MARTMDAR AND VRUDHULA: ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTlC MODELS

APPENDIX

Proofs Theorem 1:

pim) = E[Y,"] =C(AE[Y;" I p = k , p = l ]

k

+ (1 - x)E[xm I p = k, p = O])P(P = k}

Since yi,j are iid random variables, we can see that

Therefore, (19) can be rewritten as

m-1

+ x (-l)j ( y ) g p ( v p ) ) . j=O

Using similar arguments we can derive (6). This proves the theorem. U

Lemma 1: From (9), we get

h ' ( ~ ) = ( 2 ~ - i)(i - 2X)gb((i - U) + ( 2 ~ - 1)s)

(20)

(21)

h"(s) = (2w - 1 ) 2 ( 1 - 2X)g&'((l - w ) + (2w - 1)s)

We know that for any positive, discrete random variable such as P, all order derivatives of gp(s) (its pgf) are positive. (This is a consequence of probability values being greater than 0; see Definition 2). Thus gp(s) is monotonically increasing and concave. Substituting values of X and w from (8) into (20)

0 and (21), we prove the lemma.

~

371

Lemma 2: From Lemma 1, it follows that for circuits in regions RI and R3 (i.e., nor and nand type circuits), since h is monotonically decreasing, there is exactly one fixed point. Now consider circuits in R2 and R4 such that (w, A) # ( 1 , O ) and (w,X) # (0 , l ) . When X # 0 or w # 1, we see from (9) that

h(0) = x + (1 - 2X)gp(l - w )

h(1) = x + (1 - 2X)gp(w) E ( 0 , l ) whenever X E ( 0 , l ) (22)

E (0 , l ) whenever X E (0, l ) . (23)

Inequalities 22 and 23 follow from the fact that gp (1 - w ) and gp(w) lie between 0 and 1 whenever w lies between 0 and 1. Given the above inequalities and the fact that h is monotonic and either concave or convex (see Lemma 1) in the closed interval [0,1], we can see that there exists exactly one fixed point p of h between 0 and 1. In other words, if h has more than one fixed point then either it is not monotonic or if it is monotonic then it cannot be concave or convex (i.e., the slope of h cannot be monotonic). This proves Lemma 2a.

For Lemma 2b, let (U, A) = ( 0 , l ) (pure OR circuits). Then from (9) we get h(s) = 1 - gp (1 - 9). Since gates cannot have 0 fanin, we know that gp(0) = 0. Also, gp(1) = P { p =

Therefore, 8 = 0 and s = 1 are fixed points. If h has more fixed points, it cannot be concave. Thus h has exactly two fixed points. A similar proof can be given for pure and circuits with

Theorem 2: The relation between pi-l and pi is given in (II) , i.e., pi = h(pi-1). Thus, Theorem 2a follows immediately from the definition of fixed points (Definition 3).

For circuits in the region R2 U R4, h is monotonically increasing (Lemma 1 and Fig. 5) . Assuming pi-1 0 and h(1) < 1 whenever w , X E (0 , l ) . This means that h(s) > s fors E [O,p) and h(s) < s for s E (p, 11. Assuming pi-1 < p, we get pi = h ( p i - I ) > pi-1.

Thus pi E ( p i - 1 , ~ ) whenever pi-1 < p. Similar arguments are used to show that pi E (p, piPl)whenever pi-1 > p. This proves Theorem 2b.

When (w,X) E RI U RJ, h is monotonically decreasing. Assuming pi-1 h(p) = p. A similar proof holds for the case pi-1 > p. 0

Lemma 3: Consider the sequence { p i } (i = 0,1, . . e). Let po L: p. Then we know (from the above discussion) that { p i } is monotonically increasing and bounded above by p. Thus, { p i } converges to a point l 5 p. Assuming l < p , we get h(!) = C since it is a limit point of the sequence. This contradicts Theorem 2b. Therefore, ! = p. Similarly, if po 2 p then { p i } is monotonically decreasing and bounded below by

0 Lemma 4: From the definition of f (lo), we know that

f(p) = h(h(p) ) = h(p) = p. This proves part a. For part b, let h(q) be a fixed point of f, i.e., f ( h ( q ) ) =

h(q) . Expanding f we get h(h(h(q))) = h ( f ( q ) ) = h(q). h is

k} = 1. Thus h(0) 1 1-gp(1) = 0 and h(1) = l-ga(0) = 1.

(U, = (1, 0) . 0

p. Therefore, { p i } converges to p.


a monotonic function (Lemma 1). Therefore, its inverse is well defined. Taking inverses on both sides of the above equation, we get f ( q ) = q proving q is a fixed point of f.

Similarly, let q be a fixed point of f , i.e., f ( q ) = q. This means that h ( f ( q ) ) = h(q). Expanding the left-hand side we get h(h(h(q))) = h(q) . Now we can collect compositions of function h on the left-hand side to get f ( h ( q ) ) = h(q) proving

U Lemma 5: From (10) we get f’(s) = h’(h(s))h’(s). Thus

f’(p) = h’(h(p))h’(p) = (h’(p))’ . From Lemma 1 we know that when (w ,X) E RI U R3 h is monotonically decreasing. Using this fact and the equation above, we see that p is an attractor fixed point of f (i.e. f’(p) < 1) if and only if -1 < h’(p) < 0 and p is a repellor fixed point of f if and only if h’(p) < -1.

We establish another small fact before proceeding with the proofs. Let z and y be two fixed points of f such that either both are attractors or repellors. Also, without loss of generality, let z < y. Then the number of fixed points between x and y is odd. Similarly when z is an attractor and y is a repellor (or vice versa), the number of fixed points in between z and y is even. The reason for this is as follows.

First, let us consider the case where z and y are both attractors. The proof for this is based on the fact that when s E (x,z + t) (for some E > 0) f(s) < s and when s E (y - 6,y) (for some 6 > 0) f(s) > s. (We do not consider the case where the slope of f is 1 at any fixed point) Therefore, values of f in the neighborhoods described above, lie on opposite sides of the line f = s. This can happen only if there are an odd number of fixed points in between x and y. Similarly, when 2 and y are both repellors, f(s) > s for s E (z, z + E) and f(s) < s for s E (y - 6,y). Again, since f is on opposite sides of the f = s line, the number of fixed points in between z and y is odd. However, when z is an attractor and y a repellor (or vice versa) then values of the function f in the above neighborhoods lie on the same side of the line f = s. This can happen only if the number of fixed points in between x and y is even.

From Inequalities 22 and 23, we know that h(s) E ( 0 , l ) for s E (0 , l ) . This implies that f (0) = h(h(0)) > 0 since h(0) E (0, l ) . Given that q1 is the smallest fixed point of f, it is clear that it is an attractor fixed point.

Now consider the case where -1 < h’(p) < 0 (i.e., p is an attractor fixed point of f) . Since q1 is an attractor fixed point, we know that there are an odd number of fixed points in between q1 and p. Thus, the number of fixed points of f (including q1) that are smaller than p is an even number 2k. Let these fixed points be ordered as q1 < . . . < q 2 k < p. For every fixed point qi (1 5 i 5 2k), we know that h(q;) is also a fixed point (from part b of Lemma 4). Therefore, when -1 < h’(p) < 0, the total number of fixed points of f , which are different from p , is 4k and thus f has a total of 4k + 1 fixed points. This proves part a. Part b follows simply because, given two consecutive fixed points, one is an attractor and the other a repellor.

The proof of part c uses similar arguments. Let h’(p) < -1 (i.e., p is a repellor fixed point of f). Since q1 is an attractor fixed point, the number of fixed points in between q1 and

that h(q) is a fixed point of f.

p is even. Thus, the number of fixed points (including q1) smaller than p is odd, i.e., of the form 2k + 1. Therefore, the total number of fixed points of f (using similar arguments as above) is of the form 4k + 3. Proof of part d is essentially the

0 Lemma 6: From (1 l), we know that pa; = f(p2i-2). Con-

sider the sequence {pa;}. Since q is the closest attractor fixed point and f is monotonic (increasing), {poi} converges to q (see proof of Lemma 3). Further, p2i+1 = h(p2i ) . Therefore, limi+m p2;+l = lim;+m h(p2i ) = h(limi-m pzi) = h(q) . This proves the lemma. U

Lemma 7: The fixed points of f are solutions to the equation f ( s ) - s = 0. Using the expression of (15), we see that f (s) - s results in a function whose numerator and denominator are fourth degree polynomials in s. Therefore, it has at most four solutions for s E [0,1]. From Lemma 5 , we know that f has an odd number (either 4k + 1 or 4k + 3 for some nonnegative integer k) of fixed points. Furthermore, from Lemma 4a, we know that f has at least one fixed point, namely p which is the unique fixed point of the corresponding function h. Combining these, we see that f has either one or

0

same as that for part b.

three fixed points for s E (0, I].

REFERENCES

P. Agrawal and V. D. Agrawal, “Probabilistic analysis of random test generation method for irredundant combinational logic networks,” IEEE Trans. Comput., vol. C-24, pp. 691-695, July 1975. P. Agrawal and V. D. Agrawal, “On Monte Carlo testing of logic tree networks,” IEEE Trans. Comput., vol. C-15, pp. 664-667, June 1976. F. P. Brglez, “On testability analysis of combinational networks,” in Pmc. IEEE Int. Symp. Circuits Syst., June 1984, pp. 221-225. S. J. Chandra and J. H. Patel, “Experimental evaluation of testability measures for test generation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 691-695, July 1975. L. H. Goldstein and E. L. Thigpen, “SCOAP Sandia Controllabil- ity/Observability Analysis Program,” in Proc. 17th Design Automation CO&, 1980, pp. 190-196. H. Huang and M. A. Breuer, “Analysis of the detectability of faults by random test patterns in a special class of NAND networks,” in Computer Electrical Engineering, vol. 1. Elmsford, NY: Pergamon, 1973, pp. 17 1-1 86. S. K. Jain and V. D. Agrawal, “STAFAN: An alternative to fault simulation,” in Proc. 21st Design Automation Con$, 1984, pp. 18-23. L. Lipsky and S. C. Seth, “Signal probabilities in AND-OR trees,” IEEE Trans. Comput., vol. 38, pp. 158-1563. Nov. 1989. A. Majumdar, “Stochastic models for testability analysis of digital circuits,” Ph.D. dissertation, Dept. of Electrical Engineering-Systems, Univ. Southern California, Costa Mesa, 1992. A. Majumdar and S. Sastry, “On the distribution of fault coverage and test length in random testing of combinational circuits,” in Proc. 29th ACM/IEEE Design Automation Cont. 1992, pp. 341-346. A. Majumdar and S. Sastry, “Statistical analysis of controllability,” in Proc. 6th Int. Con$ VLSI Design, (Bombay, India), 1993, pp. 55-60. A. Majumdar, “Partitioning data flow graphs under multiple path constraints,” Dept. of Electrical Engineering, Southern Illinois Univ., Tech. Rep. SIUC-DEE-TR93-1, 1993. K. P. Parker and E. J. McCluskey, “Probabilistic treatment of general combinational networks,” IEEE Trans. Comput., vol. C-24, pp. 668-670, June 1975. S. Sastry and A. Majumdar, “A branching process model for observability analysis of combinational circuits,” in Proc. 28th Design Automation Con$, 1991, pp. 452457. Y. Savaria, B. Lague, and B. Kaminska, “A pragmatic approach to the design of self-testing circuits,” in Proc. IEEE In?. Test Cont. 1989, pp. 745-754. J. Savir, G. S. Ditlow, and P. H. Bardell, “Random pattern testability,” IEEE Trans. Comput., vol. C-33, pp. 79-90, Jan. 1984. B. H. Seiss, P. M. Trouborst, and M. H. Schulz, ‘Test point insertion for scan-based BJST,” in Proc. European Test Cont. 1991, pp. 253-262.

MAJUMDAR AND VRUDHULA: ANALYSIS OF SIGNAL PROBABILITY IN LOGIC CIRCUITS USING STOCHASTIC MODELS 379

[18] S . C. Seth, V. D. Agrawal, and H. Farhat, “A statistical theory of digital circuit testability,” IEEE Trans. Computers, vol. 39, pp. 582-585, Apr. 1990.

[I91 S . C. Seth and V. D. Agrawal, “A new model for computation of probabilistic testability in combinational circuits,” INTEGRATION, V U 1

[20] S . C. Seth, L. Pan, and V. D. Agrawal, “PREDICT Probabilistic Estimation of Digital Circuit Testability,” in Proc. Fl‘CS-15, 1985, pp. 220-225.

[21] K. D. Wagner, C. K. Chin, and E. J. McCluskey, “Pseudorandom testing,” IEEE Trans. Compur., vol. C-36, pp. 332-343, Mar. 1987.

[22] H. J. Wunderlich, “PROTEST A tool for probabilistic testability analysis.” in Proc. 22nd Design Automation Cont. 1985, pp. 204-21 1.

J., vol. I, pp. 49-75, 1989.

Amitava Majumdar (S’88) received the B.E. (honors) degree in electrical and electronics engineering from Birla Institute of Technology and Sciences, Pilani, India, in 1983, the M.S. degree in electrical and computer engineenng from the University of Massachusetts, Amherst, in 1986, and the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, in 1992.

Since 1992, tie has been an Assistant Professor in the Department of Electrical Engineering at South- em Illinois University, Carbondale. His research

interests include VLSI design automation, testability analysis of digital circuits, design for testability, fault tolerant computing, reliability modeling, and performance evaluation of computer networks

Sa” B. K. Vrudhula (a.k.a. Sarma Sashy) received the B.Math (honors) degree from the Univer- sity of Waterloo, Ont., Canada, in 1976. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, in 1980 and 1985, respectively.

During 1985-1992 he was an Assistant Profes- sor of Electrical Engineering at the University of Southern California. In 1992 he joined the ECE Department at the University of Arizona as an Associate Professor. His current research interests

are in the area of design automation and testing of digital systems. These include optimization problems that arise in VLSI chip design, stochastic models for testability analysis of circuits, partitioning for built-in self-test, logic synthesis, automatic synthesis of asynchronous designs and, formal methods for design specification.

Documents

Analysis of signal probability in logic circuits using stochastic models