Analysis of n-channel MOS-controlled thyristors

1612 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 38, NO 7. JULY 1991

Analysis of n-Channel MOS-Controlled Thyristors Q. Huang, G. A. J . Amaratunga, Member, IEEE, E. M. Sankara Narayanan, Student Member, IEEE, and

W. I. Milne

Abstract-The turn off of the n-channel MOS-controlled thyristor (NMCT) is analyzed using two-dimensional simulation. A lateral NMOS-controlled thyristor structure, LNMCT, suitable for HVIC application is also proposed. It is found that the operation of a parasitic lateral n-p-n transistor in NMCT-type structures degrades the forward voltage drop and the turn-off capability and hence should be suppressed. The maximum controllable current in the NMCT is not only a function of internal parameters but also depends on external supply voltage. This indicates that snubberless operation of an MCT-type device is not feasible. The advantages and disadvantages of the NMCT are compared with those of conventional MCT structures. The LNMCT turn-off speed is limited by the large amount of holes existing in the substrate, resulting in a turn-off waveform similar to an LIGBT.

I. INTRODUCTION OS-CONTROLLED power devices provide attrac- M tive characteristics due to their ease of integration,

very low driving power, and high ab’/& capability. In order to compete with the power bipolar transistor (BJT) in high-voltage applications, bipolar and MOS combination devices like the IGBT [ I ] were developed. Currently IGBT’s can switch off current density which is a factor of 20 greater than a 600-V power MOSFET and about a factor of 3 greater than a bipolar transistor. However, the modulation level in an IGBT, and as a consequence the forward voltage drop, is limited by the possible loss of gate control if it latches up in its parasitic thyristor path. This lower level modulation, together with its intrinsic MOS channel resistance, and more importantly the non- uniform flow of current makes the IGBT unsuitable for use in very high voltage applications because it has a rel- atively high forward voltage drop. When compared with a 600-V thyristor, an IGBT has a current density which is lower by a factor of 10 at a forward voltage drop of 1-V and about a factor of 50 at 2 V. Obviously, a thyristor with MOS turn “on” and turn “off’ is the best solution.

Recently, much effort has been directed towards the re- alization of MOS-controlled thyristors. Plummer et al. [2] described some lateral device structures which combined MOS and thyristor action, some of which also have MOS turn-off capability. A vertical structure, referred to as the MCT, has been proposed by Temple [4]. A lateral structure using Temple’s approach has also been proposed [3]. The key to accomplish MOS gate turn-off in all these de-

Manuscript received October 8 , 1990; revised March 6 , 1991. The authors are with the Department of Engineering, University of Cam-

IEEE Log Number 9100059. bridge, Cambridge CB2 IPZ, United ‘Kingdom.

Off gate Cathode

h p-base

n base

r-- p substrate

Anode

cz Fi off Gate

4

Anode

Fig. I . NMOS-controlled thyristor structure and it5 equivalent circuit.

vice structures is similar, that is, to realize a thyristor having a holding current controlled by a MOS gate. The holding current of the thyristor is normally dictated by p-base resistivity and the efficiency of the emitter short. There- fore, what a MOS-controlled thyristor should achieve using a MOS gate is to control the current through the emitter short from very low (corresponding to the MOS “off’) to very high (corresponding to MOS “on”). In the MCT, this is achieved by the use of a PMOS transistor integrated in the upper base region of the thyristor. By using a PMOS device as the turn-off element, the MCT suffers from lower gate controllable current density because of the lower carrier mobility in PMOS. A comple- mentary MCT is thus normally used in order to realize NMOS turn-off. However, the NMOS turn-off device can only be used as a replacement to p-channel IGBT devices.

0018-9383/91/0700-1612$01.00 0 1991 IEEE

HUANG er d.: n-CHANNEL MOS-CONTROLLED THYRISTORS 1613

The n-channel MOS-controlled thyristor (NMCT) structure was first reported by Stoisiek [l 11. The unit cell of such a device, is shown in Fig. 1 . On the right, its equivalent circuit is also shown indicating the emitter short controlled by the NMOS. The key feature of this structure is to integrate a short-channel NMOS at the top of the device. The connection of NMOS to the upper emitter/base junction of the thyristor is achieved by using the thyristor cathode as the NMOS source, while employ- ing a floated ohmic contact (FOC) across the NMOS drain and p-base. This allows a short to be formed between the p-region and the n+-drain. When the NMOS transistor is turned on, the same amount of holes flows to the FOC from the p-base to satisfy current continuity conditions as electrons from the NMOS source to its drain. Because it uses n-channel MOS as the control element, the NMCT is expected to show higher turn-off current capability. However, the results presented in[ 1 I ] showed somewhat worse characteristics compared with a conventional MCT, but no explanation has been given. In this paper, the NMCT is analyzed with the help of two-dimensional simulation. The device physics associated with the turn-off process will be discussed in the Section 11. Two-dimensional simulation results are presented in Section I11 while Section IV discusses the simulated results of a lateral thyristor structure using a similar NMOS-controlled emitter short.

11. NMCT TURN-OFF

The success of turning the thyristor “off’ relies on the fact that the latching condition can be broken, in other words bringing the holding current of the thyristor to a very high value in a very short time. This is achieved in the NMCT by turning the NMOS “on” to short the basel emitter junction of the upper n-p-n transistor in the thyristor path, hence diverting the hole current through the NMOS. The hole current in the p-base is in effect diverted by recombining with the electron current through the NMOS transistor at the FOC. The NMOS can be laid out in such a way that it surrounds every cathode n + diffusion in an interdigitated manner. Consider a unit cell of the NMCT shown in Fig. 1 . Before turn-off, in the ideal case, the hole current flow in the upper n-p-n transistor base is basically one-dimensional. The potential at the FOC should therefore be equal to the forward-biased voltage VJ at junction J1. When a positive voltage is applied to the NMOS gate, its channel starts conducting an electron current, which has to be met by the same amount of holes at the FOC. This can also be viewed as the turn-off process being that which changes the hole current flow from a one-dimensional mode to a more two-dimensional one. The NMOS channel resistance Rch determines how pref- erable this alternative current path is for holes as compared to the normal one across the forward biased p-n junction J l . The NMOS channel resistance R,,, together with the p-base resistance R,,, determines the maximum controllable current (MCC)

Imcc = VT.off/apnp * (Rch + R p ) ’ (1)

Here apnp is the current gain of the lower p-n-p transitor, Vr,off is the minimum voltage to keep junction 11 forward- biased, and Rp is the modulated p-base resistance. Note that this equation is somewhat different from that in [4], as in an NMCT the spreading resistance does not exist. However, it is clear that in order to achieve higher controllable current, a short-channel NMOS and low p-base resistance is essential. As an example, using an apnp of 0.4, emitter width L = 10 pm, VT.oE equal to 0.85 V , p-base modulated sheet resistance of 50 Q / 0, and an Rch value of 0.7 Q cm typical for an NMOS fabricated by a 3-pm CMOS process, the NMCT should turn off a current of 2730 A/cm2 at a gate voltage of 5 V. At a gate voltage of 20 V, it should turn off a current of more than lo4 A/cm2.

111. NUMERICAL ANALYSIS

In this section, a two-dimensional numerical simulator, BAMBI [6], is used to simulate the forward voltage drop of the NMCT and its turn-off capability. Doping profiles were chosen to achieve a forward-blocking voltage of more than 600 V with an n-base concentration of lOI4 ~ m - ~ . For simulation purposes, the FOC is treated as a current boundary condition, where a decoupled method is used to include a external resistance to allow the change of the floating region potential to achieve zero external current [12], [13].

A. Forward Drop

Simulation was first carried out on an NMCT cell without NMOS elements to check the effect of two-dimensional current flow in the region where the n+-emitter does not exist. The result, shown in Fig. 2, is compared with a one-dimensional solution taken from [4]. It is seen that the forward-voltage drop VF increases by about 0.4 V and 0.6 V for the NMCT cell with n+-emitter width L = 15 and 5 pm, respectively. Decreasing L increases VF. How- ever, as will be shown in the next section and predicted through ( l ) , smaller L results in higher turn-off current capacity. This suggests that a tradeoff exists between the maximum controllable current I,,,,, and the forward voltage drop V,. This, however, is not a severe limitation on device design as the increase of V, due to increasing L is small, only 0.2 V when L changes from 15 to 5 pm. L should therefore be chosen first from the requirement of the maximum controllable current Zmcc rather than from forward voltage drop V,.

Another factor which affects both V , and I,,,,, is the p-base junction depth X,, i.e., the resistivity of the p-base diffusion since it affects the upper n-p-n transistor gain anpn. A deeper junction depth results in higher forward voltage drop as expected because of lower alpn. When junction depth changes from 5 to 25 pm, simulation shows that the forward-voltage drop increases by about 0 .3 V at a current density of 1000 A/cm2. However, the increase

1614 HUANG et al.: n-CHANNEL MOS-CONTROLLED THYRISTORS

105 h

N < E 4 y I O 4 v

U : 101 B s a

0 1 2 3 4 5 6

Forward Voltage Drop (V)

Fig. 2. I-Vcharacteristics of the NMCT, I-D result i5 taken from (41.

in forward-voltage drop will be compensated by a higher gate-controllable current due to the lower sheet resistance in the p-base.

The result shown in Fig. 2 is the two-dimensional results from an NMCT cell without the NMOS elements and the FOC (thus it looks rather like a conventional GTO). However, the situation is more complicated when the NMOS element is considered. Simulation results in- cluding the NMOS element show an even higher forward- voltage drop which is not as expected. This higher forward-voltage drop, also observed experimentally in [I I ] and recently in conventional MCT [7], can be explained as follows. If one looks more carefully at the NMOS structure, or generally at any MCT structure, beside6 the two main coupling bipolar transistors, namely the lower p-n-p transistor and the upper n-p-n transistor, another parasistic bipolar transistor exists due to the introduction of the MOS element. In the NMCT, a lateral n-p-n transistor (LNPN), formed by the source and drain n+ diffusion under the NMOS channel exists (in a conventional MCT a vertical p-n-p transistor exits). In this LNPN transistor, its collector is shorted to its base via a lateral resistance and therefore conducts when the NMCT is in its “on’ state because the LNPN shares the same base/emitter junction J1 of the main thyristor. The forward-voltage drop V , of the NMCT increases due to the degradation of the upper transistor gain cynpn. This means that in the “on” state of the NMCT, ideal one-dimensional hole current flow in the p-base region is not achievedas some holes are diverted to the FOC to meet current continuity with the LNPN collector current (electron current in this case). This therefore increases the total hole current in- jected from the anode in order to maintain the same anode current density. Results from simulation show that most of the increased anode voltage appears at the p-base/ n-base junction J2.

The degradation of VF is thus asociated with the Fhar- acteristics of this parasitic LNPN transistor because the

holes diverted by the LNPN are equal to its bipolar com- mon emitter current gain times the base current driving it. The base current, considering the LNPN to be located at the top of the NMCT and its vertical dimensions to be very small compared with the total device dimensions, is only a fraction of the current driving the upper n-p-n transistor. However, its bipolar current gain Plnpn is quite high because of high injection efficiency and short basewidth. It should be noted that because of the FOC the LNPN can be viewed as having its collector clamped to the base. It is thus vital to reduce the bipolar current gain of the LNPN in order to minimize its effect on forward operation. There are, fortunately, some straightforward ways to control the LNPN’s Plnpn. One is to have an additional implantation of the same impurity as the p-base into the channel region so that its peak is located away from the Si02/Si inter- face. This could effectively reduce the bipolar current gain while not increasing the NMOS threshold voltage. An- other effective method is to adopt a recessed-gate geometry as described in [8] which virtually eliminates LNPN operation. Simulation shows, that after an additional implantation, the NMCT forward-voltage drop is close to that shown in Fig. 2 . To show how an implantation affects the operation of an NMCT, the electron current density and hole current density at the to of an NMCT cell (25 X 10 ,um) working at lo3 A/cm’, are shown in Figs. 3 and 4 with and without an implantation of dose 1.5 X lOI4 at 200 keV, respectively. Fig. 4 has a very high electron current density near the FOC region suggesting LNPN operating in its “on” state while Fig. 3 suggests much less active LNPN operation. The hole current density dia- gram further confirms that holes have to flow into the FOC region to satisfy the current continuity conditions there, this is equivalent to saying that the FOC acts like a recombination center which degrades the current gain of the upper n-p-n transistor. The recombination rate of such a center is dictated by the parasitic LNPN transistor. With the efficient suppression of LNPN operation, devices like the one shown in Fig. 3 should approach a conventional thyristor in terms of forward-voltage drop.

In some circumstances the LNPN could be viewed as being advantageous. Because the LNPN effect becomes stronger only at high forward current density, the NMCT thus has an inherent current limiting capability. This should make the NMCT have a better safe operation area (SOA) especially under high surge current conditions. By properly adjusting the performance of the LNPN using an implantation to control the LNPN current gain, an opti- mal tradeoff can be achieved.

B. Maximum Controllable Current

The operation of the parasitic LNPN also degrades the maximum controllable current (MCC). This is because in order to turn off the NMCT, the NMOS channel has to turn off the LNPN as well as the upper vertical n-p-n. It must divert two components of the hole current; one is the hole current driving the upper n-p-n transistor, and the

HUANG er ul: n-CHANNEL MOS-CONTROLLED THYRISTORS 1615

0 0

1 5 1 5

2 5

Fig. 3 . Electron and hole current density in the NMCT cell (top 25 x 10 pn) with an additional implantation.

Fig. 4. Electron and hole current density in the NMCT cell (top 25 X I O pm) without an additional implantation.

other is the hole current required to maintain LNPN conduction as described in the previous section. The first component cannot be diverted by the NMOS channel un- less the second component has already been diverted. This means some of the MOS channel current is "wasted" during turn "off." LNPN operation should therefore be suppressed to achieve higher controllable current.

Although (1) gives a fundamental guideline through which the MCC can be determined, the turn-off process is a dynamic process which limits the validity of (1). Fur- thermore, the resistance in (1) is a modulated value which cannot be easily obtained. The bipolar current gains cynpn

and apnp change dynamically during the turn-off. If during the time taken to turn "on" the NMOS channel, the sum of the dynamic current gain remains larger than unity then the NMCT cannot be turned off. As the NMOS is turning on, anpn decreases, however, apnp increases to compen- sate for the loss in the upper n-p-n current gain. From the

terminal voltage point of view, the beginning of NMOS conduction attempts to decrease the potential VFoc at FOC, which is reflected in the junction voltage VJ of J1. Any decrease of VJ causes a decrease in anpn and thus the forward conduction current. The reduction of any forward current is accompanied by an increase of anode voltage which, in turn, causes an increase of cypnp. The extent to which anode voltage increases is, however, governed by external circuit conditions. From this discussion, MCC can be defined as the forward conduction current at which

aanpn /a VFoc 2 ( a a p n p / a v, ) a v, /a VFoc (2 )

where V, is the anode voltage. Equation (2) shows that the MCC is the current at which the loss of bipolar current gain anpn due to the conduction of NMOS cannot be compensated by the increase of cypnp. If we define anpn,off as the current gain of upper n-p-n transistor after the NMOS turns on, then it can be expressed as [lo]

1616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991

(3)

where ZMos is the current passed by NMOS after it turns “on” and IN+ is the cathode current. This expression is similar to that of an emitter-shorted thyristor [lo]. From (3) the difference of the n-p-n current gain before and after the NMOS turns “on” can be obtained

A a n p n = ay ,n IMOs/ ( IMOs + IN+ 1. (4)

Substituting this into (2), using I,,,,, = IN+, the MCC can be expressed as

where Aapnp is the lower p-n-p current gain change after the NMOS turns “on.” The physical meaning of ( 5 ) is that, if after NMOS turn “on” there is no change in the bipolar current gain cypnp, e.g., Aapnp = 0, then I,,, is infinity. This means that the NMCT can be turned off at any current density. On the other hand, if Aapnp = anpn, then I,,, = 0. This means that if the lower p-n-p current gain can follow any change in the upper transistor current gain, maximum change equals cynpn, then the NMCT cannot be turned off. In practice, however, these conditions will not be adhered to since Aapnp = 0 or Aapnp = anpn cannot be achieved.

Compared to ( l ) , (5) gives a dynamic view of the turn-“off’ process. The importance of having a short NMOS channel is also very clear. It also suggests that a larger current gain anpn is helpful to have a higher MCC. If this is achieved by having a shallow p-base junction depth then it has a negative effect because IMos decreases due to the larger p-base resistance. However, if Aapnp can be made smaller the MCC can thus be increased. It could, therefore, perhaps be argued, that the NMCT, or MCT-type devices in general, will have a lower MCC when supply voltage goes up in resistive or inductive load conditions due to faster buildup of the n-base depletion layer resulting in an increased apnp. Besides this, when one is looking for the relationship between the breakdown voltage BV and the MCC, it is not difficult to predict a degradation in the MCC when BV increases. This is because higher breakdown voltage is normally achieved by having an extra lightly doped n-base, thus the term a a p n p / a V A is larger than that of a low breakdown-voltage device.

Although we cannot directly monitor the two terms in (2) with the increase of forward conduction current IF, we can monitor two other related device parameters at the FOC and anode terminal numerically. The two device parameters are anode conductance & and anode transconductance &OC, defined as

g A = arF/avA (6)

and

g F O C a r F / a v F O C . (7)

50 I I I

A(MTP point)

5 ’” 1 I anodecurrentconductance

--c- anode current transdonductance

l o l l

U loo00 15000 2oooO 0 5000

Forward Current Density (A/cm2)

(a)

anode current conductance

0 lo00 2000 3000 4000

Forward Current Density(A/cm2) (b)

Fig. 5 . NMCT anode conductance g, and anode transconductance gkoc as a function of the forward current density J,. for two emitter wldths of 5 and 15 pm.

Using this definition, we can redefine the MCC as the current at which

g A gFOC. (8)

This also means that an NMCT can be turned off if its anode current is very sensitive to the potential at the FOC. Note no attempt has been made to include the value of channel resistance here, hence (8) represents internal be- havior of the NMCT which is determined by its geometry and doping profile, while channel resistance is determined by the external gate voltage. ,

Simulation has been used to check the validity of (8). The value of g A and gFOC are constantly monitored in BAMBI at each I-V point. Fig. 5 shows the simulated results for the NMCT with L = 5 and 15 pm, respectively. Note that transconductance g F o C has a maximum, and that as expected a smaller L results in much higher sensitivity between the anode current and FOC potential. Transient simulations were carried out to ascertain

HUANG er al . : n-CHANNEL MOS-CONTROLLED THYRISTORS

Cathode OffGate

1617

Anode

p welubase

n drift region

p substrate

Fig. 6. Cross section of the proposed lateral NMCT (LNMCT) device with junction isolation.

whether an NMCT working near the cross point between g, and g F O c can be turned “off.” Gate voltage is kept constant and hence channel resistance is not a variable. It has been found that (8) overestimates the MCC as an NMCT working near the current density limit determined by (8) could not be turned off. This is understandable as (8) is not fully equivalent to (2). However, an NMCT working at the maximum transconductance point (MTP) (point A in Fig. 5 ) is always turned “off.” Thus the MTP gives the lowest estimation of MCC. It is desirable, therefore, that an NMCT be designed to work at the MTP. This will give the fastest switching speed for a given gate voltage and good SOA if inductive load conditions are involved.

If we take into account the NMOS channel resistance and assume the NMOS conducts instantly, (8) should be rewritten as

gFOC * gA * (9) If an NMCT works under resistive load conditions with load resistance RL, then AV, = -AI, R,. Thus (9) becomes

gA R, 5 1 . (10) It is very interesting to note that (10) gives the MCC determined by an external value RL and an internal param- eter g,. We note that g, is almost a linear function of forward conduction current in Fig. 5 , therefore (10) clearly suggests a reduction in MCC when supply voltage increases. This has been experimentally confirmed in [ l 13 .

IV. LATERAL NMOS-CONTROLLED THYRISTOR A lateral version of the NMCT, called the lateral

NMOS-controlled thyristor (LNMCT) is also proposed. Such a device, shown in Fig. 6, can be fabricated using a standard CMOS process and is for use in HVIC’s. The “off’ state performance of the LNMCT is achieved by using the RESURF principle [ 5 ] . All discussion about the

on-state performance of the NMCT should be in theory applicable to the LNMCT. At a current density of 300 A/cm2, simulation shows that the LNMCT has a forward-voltage drop of about 1.4 V for a 500-V device.

To turn “off’ the LNMCT, a postive gate voltage is applied to its turn-“off’ gate to divert holes in a similar way as in the NMCT. However, the hole current path is different to that in the NMCT as holes reach the FOC before emittedbase junction J1 . This is based on the as- sumption that holes flow laterally from the anode side to the cathode side. Although there is a parasitic thyristor formed by the n+-region in the FOC, p-well-base, n-drift region, and pf-anode, it will not be turned “on” during the turn “off’ of the LNMCT due to the fact that the ngOC /p-well-base junction will always remain zero or reverse-biased because of the lateral current flow in the p-well-base underneath the FOC. This is because the FOC potential, and hence the nFfOC potential, will be close to that of the p-well-base potential underneath the pgoc, which, in turn, is higher than that underneath the nloc. On the other hand, because of the lateral flow of the current in the LNMCT, it should have shorter storage time than the NMCT. This has been canfirmed by transient simulation. Shown in Fig. 7, is the simulated LNMCT turn-“off’ waveform. Storage time is less than 50 ns compared to 200 ns typically in the NMCT when a mi- nority-carrier lifetime of 1.2 vs is used in the simulations. The turn-“off ’ waveform has a plateau at a higher current level after latching is broken, and finally goes into a tail at low current levels. This is similar to that found in LIGBT turn-off [9] and is due to a large amount of holes in the p--substrate before turn-“off.” A slow recombination process is needed to recover n- epi/p- substrate junction which is forward-biased before turn-off. In order to verify this, the same LNMCT, but without a p- substrate (that is, replaced by an n- substrate, so that RE- SURF is not utilized) is simulated. This turn-off waveform is also shown in Fig. 7. Because the LNMCT is for

1618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991

400 : 9 300 < - 200

2

n- substrate . E Y c

8 100

O J I I

0 1000 2000 Time (ns)

Fig. 7. Tum-“off’ waveform for the LNMCT structure showing the affect of the p- substrate.

HVIC applications, a p- substrate is normally needed to provide junction isolation. From LNMCT simulation it can be concluded that in order to reduce turn-off time, a substrate ohmic contact is preferred in order to remove holes from the p- substrate. On the other hand, an LNMCT built using dielectric isolation (DI) should have a faster turn-off speed partly because there is no substrate junction which needs to recover before finally turning “off,” and partly because the current flow is more lateral in this case favoring turn-‘ ‘off ’ via the MOS channel.

V. CONCLUSION The turn-“off ’ of the NMOS-controlled thyristor

structure NMCT has been analyzed in detail. Turn-“off’ of such a device is accomplished by the turn-“on” of NMOS gates which surround every emitter finger of the thyristor. The affect of the parasitic lateral n-p-n transistor on NMCT performance has been analyzed. This LNPN transistor should be suppressed during NMCT operation. However, it is possible to use this LNPN to limit the current level of the NMCT at high current levels and thus achieve safe operation under any circuit condition in terms of SOA and turn-off capability. Higher controllable current can be achieved due to the higher channel mobility of electrons in NMOS. The maximum controllable current (MCC) is determined not only by internal device parameters but also by external circuit conditions such as supply voltage. The NMCT should be designed to operate at the maximum transconductance point (MTP) to opti- mize silicon area cost and device performance.

Compared with the conventional MCT, the advantages of NMCT are as follows: a) An NMOS-controlled turn- off, this makes the NMCT an attractive n-channel-type device alternative to the IGBT. b) Ease of fabrication. The NMCT can be made using a standard CMOS process, not a DMOS process as required for a conventional MCT. Both the NMCT and the MCT are inversion channel controlled devices, and should therefore show similar performance dependence on temperature, especially regarding the turn-off current capability. The disadvantages of NMCT could be stronger parasitic operation of the LNPN (compared with a p-n-p in MCT); more complicated in terms of top metallization as two contacts have to be formed on the top and the metallization has to be inter- ruped which could be a problem at very high current dens- ities.

A lateral structure, the LNMCT, is proposed and analyzed. The LNMCT has lower forward-voltage drop than an LIGBT and is compatible with a CMOS fabrication process which makes it suitable for HVIC applications.

REFERENCES

[ l ] B. J. Baliga, M. S . Adler, P. V. Gray, and R. P. Love, “The insulated gate rectifier (IGR): A new power device,” in IEDM Tech. D ig . . 1982, pp. 264-267.

121 B. W. Scharf and J . D. Plummer. “A MOS controlled triac device,“ in Int. Solid-State Circuit Cot$ Dig . , 1978, p. 222.

[3] M. N. Darwish, “A new lateral MOS-controlled thyristor.” IEEE Electron Device Le t t , . vol. 11. no. 6 , p. 256, 1990.

141 V. A. K . Temple. “MOST-controlled thyristors-A new class o f power devices,” IEEE Trans. Electron Devices, vol. ED-33, p. 1609, 1986.

[SI J . A. Appels and H. M. J . Vaes, “High voltage th in layer devices (RESURF devices),” in IEDM Tech. D i g . , 1979. pp. 238-241.

161 BAMBI Ver 1 .2 Users’ Guide, Tech. Univ.. Vienna. Austria, 198.5. [7] F. Bauer and P. Roggwiler. “Design aspects of MOS controlled thy-

ristor elements,” in IEDM Tech. D i g . . 1989. pp. 297-300. [8] S. Nishimatsu. “Grooved gate MOSFET,” Jupcrn. J . App/. Phys. .

vol. 16, suppl. 16-1, p. 179, 1977. [9] P. A. Gough. M. R . Simpson. and V. Rumenik. “Fast switching

lateral insulated gate transistor,” in IEDM Tech. D ig . , 1986, pp, 218- 21.

[IO] B . J. Baliga, Modern Power Device. 1111 M. Stoisiek and H. Strack, “MOS-GTO: A turn-off thyristor with

MOS-controlled emitter shorts.” in IEDM Tech. D ig . . 1985. p. 1.58. 1121 Q. Huang, G . Amaratunga, E. M. Sankara Narayanan, and W. I .

Milne, “Simulation of floating field limiting ring with circuit boundary conditions,” presented at NASECODE VII, Apr. 1991, Colo- rado, USA.

1131 -. “Simulation of reverse breakdown in planar p-n junctions,” to be published in Solid-Stute Electron.

New York: Wiley. p. 347.

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Analysis of n-channel MOS-controlled thyristors