Analysis of erratic bits in flash memories

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 4, DECEMBER 2001 179

Analysis of Erratic Bits in Flash MemoriesAndrea Chimenton, Paolo Pellati, and Piero Olivo

Abstract—This work presents experimental results concerningerratic behaviors in Flash memories obtained by tracking thethreshold voltage dynamics during any single erase operationand providing a deeper insight into their physical nature. Theparticular shape of the experimental erase curves allows thederivation of a nearly linear relationship between the amplitudeof erratic threshold shifts and the equivalent barrier heightcontrolling Fowler–Nordheim injection.

Index Terms—Erasing operations, flash memories, integratedcircuit reliability, reliability, semiconductor memories.

I. INTRODUCTION

I N THE LAST few years, Flash memories have encountereda tremendous interest, both in terms of research and applica-

tions. Nevertheless, a major aspect concerning the basic phys-ical operations, the problem of erratic bits, is still to be fullyunderstood, in spite of its cardinal impact on the whole memoryreliability and erasing performance [1]–[3]. Erratic erase is themost relevant mechanism of single bit failure in program/erasecycling and over erasing. In fact, due to the random nature ofthe erratic behavior, wafer-level tests cannot screen all erraticbits, as, for example, stress tests do for fast-erasing bits [3].Erratic bits are characterized by erasing dynamics exhibitingsudden and unpredictable jumps of the threshold voltageafter memory erasing, as can be seen in Fig. 1.

The nature of erratic behavior has been extensively studiedand attributed to positive point charges into the tunnel oxide,close to the floating-gate interface. Charge accumulation cen-ters have been related to intrinsic defects and not to externalcontaminations [1]. The origin of the positive charge has beenattributed to holes generated when a high bias is applied to thesource during the erase operation and injected by band-to-bandtunneling into the tunnel oxide [1], [2]. However, a definitiveconfirmation of such a model has not been provided and somepoints still require further experimental and theoretical investi-gations. This is particularly true for the dynamics of erratic be-havior during a single erase operation and for the physical andtechnological mechanisms that can trigger such an effect on onlya few cells.

In this work, we present some experimental results, obtainedby tracking the threshold voltage evolution during any singleerase operation. By means of a sequence of erasing pulses withincreasing amplitude, it is possible for any cell to reach an equi-librium condition characterized by a constant amount of chargeinjected from the floating gate by each pulse. These equilib-

Manuscript received May 24, 2001; revised October 16, 2001. This work wassupported in part by CNR under the MADESS II project.

The authors are with the Dipartimento di Ingegneria, University of Ferrara,44100 Ferrara, Italy (e-mail: [email protected]; [email protected];[email protected]).

Publisher Item Identifier S 1530-4388(01)11248-5.

rium conditions can be represented by an equivalent electricalparameter to be considered as a cell attribute for any given ex-perimental setup. Any erratic behavior is found to transfer theerasing dynamics from an equilibrium condition to a differentone; therefore, by analyzing the dependence of the equivalentelectrical parameter characterizing each equilibrium conditionon electrical, physical, and technological parameters, it is pos-sible to provide a deeper insight into the physical nature of er-ratic bits.

II. BASIC DEFINITIONS

The schematic cross section of a generic floating-gate (FG)device is shown in Fig. 2(a): the upper gate is the control gate,while the lower one, completely surrounded by dielectric, is thefloating gate. The basic concepts and the functionality of an FGdevice can be easily understood by determining the relationshipbetween the FG potential, which physically controls the channelconductivity, and the control gate potential, controlled by ex-ternal circuitry.

This can be done using the simple electrical model ofFig. 2(b), where and are the capacitancebetween the FG and control gate, source, drain, and bulkregions, respectively. The FG potential is [4]

(1)

where is the total capacitance, isthe floating-gate charge,

, and are the control gate, drain, source,and bulk coupling coefficients, respectively. The thresholdvoltage can be defined as the control gate voltage at whichthe MOS cell drains a predefined current.

Floating-gate cells are normally programmed via hot electroninjection and erased via Fowler–Nordheim tunneling (FN).

The FN tunneling current can be expressed as

(2)

that is valid for triangular barrier [5].In (2)

(3)

and

(4)

where represents the equivalent energy barrier, is theelectron free mass, is the electron effective mass in theoxide, is the gate area, is the electron charge, is the nor-malized Plank constant, and is the oxide electric field.

1530–4388/01$10.00 © 2001 IEEE

180 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 4, DECEMBER 2001

Fig. 1. Examples of the evolution ofV during cycling showing erratic behaviors. It can be observed that changes inV can easily be in the range of 40%.

(a) (b)

Fig. 2. (a) Schematic cross section of a generic floating-gate device. (b) Electrical model of a floating-gate device (junction capacitances are neglected).

As will be shown in Section IV, the use of the FN modelthroughout the whole analysis of erasing curves allows detectinganomalies related to erratic bits.

III. EXPERIMENTAL SETUP

All measurements have been performed on single sectors of512 kb of Flash test chips featuring a nominal tunnel oxide

nm. The considered test chips are standardNOR

Flash memories. They include a cell array, the decoders, andthe read path, but the internal finite state machine controllingwriting algorithms and internal generators providing program-ming and erasing waveforms are not present. By means of a

dedicated automated test equipment (Research Instrument forFLash Evaluation, or RIFLE [6]) it has been possible to per-form on high-density memories, but also on a single addressedcell, a set of experiments fully characterizing the impact of anymodification in the writing procedures.

Both erase (via FN tunnel) and program (via hot electron)operations have been performed by applying a sequence of boxpulses. In particular, during the erase operation, the cell con-trol gates have been biased by pulses with a constant ampli-tude V, while the common bulk was driven by a se-quence on pulses with increasing amplitude starting at

(see Fig. 3). The common source has been kept atto avoid the source/bulk junction turn on; the drains have been

CHIMENTON et al.: ANALYSIS OF ERRATIC BITS IN FLASH MEMORIES 181

Fig. 3. Shape of the erasing pulses applied to the bulk.

Fig. 4. Time evolution of the threshold voltage of different cells during anerase operation. Each point represents the threshold voltage measured after eachpulse, while the last one corresponds toV . Here,�V = 0:3 V, �t =

10ms,V = 3 V. The erasing levels on which the curves asymptotically moveare also shown.

left floating. Both control gate and bulk pulses have a constantduration .

It can be demonstrated that during erasing, an equilibriumcondition is soon reached so that after each erasing pulse,that is the threshold shift provoked by theth erasing pulse,is equal to . In such a condition, it can be guaranteedthat the charge injected from the floating gate by each pulse isconstant.

IV. EXPERIMENTAL RESULTS

The use of the erasing pulses shown in Fig. 3 allows to en-lighten some basic features of erratic bits during a single eraseoperation and, in particular, to photograph the moment at whicha cell deviates from its expected trend and exhibits an erratic be-havior. Fig. 4 shows the erasing curves, i.e., the time evolutionof the threshold voltage during an erase operation, for differentcells characterized by an almost equal threshold voltageafter programming. It can be observed that cells belonging to thesame sector and characterized by similar initial thresholds ex-hibit different erased thresholds . After the first few pulses,the erasing dynamic reaches the expected equilibrium condition,so that the erase curves move asymptotically on straight lineswhose slope is exactly for every cell. Hereafter, eachline will be referred to as “erasing level.”

Fig. 5. Erasing curves for the same cell and different initial thresholdsV .

As demonstrated in the Appendix, ’s expression is

(5)

where

(6)

(7)

(8)

and are the drain–bulk and source–bulk voltages, re-spectively, and is the threshold voltage that can be mea-sured after U.V. erase, i.e., when .

The expression (5) of the voltage reveals some impor-tant features useful in the analysis of erasing dynamics. In fact,it depends only on technological and physical parameters thatare supposed to remain constant in normal conditions and onelectric parameters that are kept constant during each erase op-eration. The natural distribution of technological and physicalparameters among an entire sector of cells justifies the mea-sured spread in . This is also true for cells exhibiting thesame , since some parameters controlling erase operationsare different from that involved during hot electron injection.

Moreover, (5) reveals that is independent of the startingvalue. This fact is also experimentally confirmed by the re-

sults of Fig. 5, where four different erasing curves are shown forthe same cell programmed at different s. It can be observedthat, when the equilibrium condition is reached, the erasing dy-namics ends on the same level, and this is caused by the factthat the physical, technological, and electrical parameters arethe same. Therefore, assuming that in normal conditions, thebarrier shape remains almost constant between two consecutivecycles, can be regarded as a cell attribute for a given set ofcontrollable parameters as and .

It must be observed that the curves of Figs. 4 and 5 exhibita normal behavior and that an equilibrium condition is alwaysreached.


(a)

(b)

Fig. 6. Some typical erratic behaviors. (a) Transition from one level to another;erasing level transition for an erratic cell: during cyclei+ 1 the erasing curvesmoves from the well-defined erasing level followed at cyclei to that to befollowed at cyclei+2. (b) Double transitions that cannot be detected by simplymonitoringV .

However, by analyzing the erasing curves of erratic bits, itcan be observed that the erratic behavior is characterized byone or more changes in the equilibrium level during the erasingoperation. Two typical behaviors are here shown in Fig. 6 forthe same erratic cell during cycling.

Fig. 6(a) shows that the erasing dynamics starts, for cycle, on the same level characterizing cycle, then it moves

to a different one with a transition that lasts for few pulses. Thenext erasing operation at cycle follows the final erasinglevel observed at cycle .

Fig. 6(b) shows a double level change. While in the case ofFig. 6(a), the erratic behavior can be observed by simply mon-itoring as normally done, the abnormal behavior exhibitedin Fig. 6(b) can be analyzed only by looking at the entire erasingcurve.

The following important properties can be summarized.

1) Erratic behavior is characterized, during a single eraseoperation, by one or more level transitions.

2) The transition can occur toward levels characterized byhigher or lower .

3) There is not a specific threshold or time during an entireerase operation at which these transitions are triggered.

4) A level change is not sudden but requires a transitory offew pulses.

5) If the cell is found on an erase level at the end of theerase procedure, the following program operation doesnot modify this state and the next erase procedure is char-acterized, at least initially, by the same level.

6) No significant changes in have been found during theerratic behavior.

These last two results demonstrate that program operationsand erratic phenomena are not correlated, while the physicalmechanisms responsible for the erratic behavior play a para-mount role only during erasing operations.

V. ANALYSIS OF CHANGES

Erratic behaviors can be studied by analyzing typical leveltransitions, such as those of Fig. 6(a). In such a figure, itcan be observed that cyclesand can be considered asnormal, since the erasing curves are characterized by straightline asymptotes, with different values. During cycle ,however, the erasing curve leaves the upper level and reachesthe lower one.

It is then possible to evaluate which parameters’ changes jus-tify different values for a cell erased under the same con-ditions and which physical mechanisms can produce such vari-ations.

From (5), it can be stated that any variation in can be in-duced by one or more of these six quantities:or .

However, it can be observed that: 1) and were keptconstant during the entire experiment; 2) is the floating gateversus control gate coupling coefficient and therefore it is con-stant; 3) by neglecting possible wearout induced variations inthe threshold voltage after U.V. and supposing that the

value is so small so that any variation in can beneglected, it can be assumed thatremains constant [see (6)]during each pulse, because the other parameters included inthis term are electrically controlled and never change during theerasing operation.

Therefore, any change in can be attributed only tochanges of or . By means of a sensitivity analysis, the varia-tion of can be ruled out, since a significant modification inproduces only a small change in . For instance, a variationof in the order of 20% only produces a change of %in , too low with respect to the much higher measuredvariations (see, for example, Fig. 1). It is worth noticing thatthe tunneling area appears only in the parameter [see (7)and (3)], so that erratic jumps cannot be explained by modelsthat assume an equivalent variation of the actual tunneling area.Large variations of can be explained by changes in, sincea total variation of 20% of produces % variation in .

From (8) and (4), the main responsibility for large variationsin has been found to be the equivalent barrier height.

The dependence of on is shown in Fig. 7. As canbe seen, despite the nonlinear expression for (5), in theconsidered range varies almost linearly with .

The strong dependence of erasing curves onis confirmedby the simulations of Fig. 8, where the different erasing curveshave been calculated with energy barrier heights varying bymultiples of 2% starting from a typical value of 3.11 eV.

CHIMENTON et al.: ANALYSIS OF ERRATIC BITS IN FLASH MEMORIES 183

Fig. 7. Calculated dependence ofV on� . � has been varied around3.11 eV�10%.

Fig. 8. Calculated erasing curves for different values of� . In each curve� varies by multiplies of�2% starting from 3.11 eV (solid line in the figure).The electrical parameters used for the simulation where those applied duringthe experiments.

Several physical mechanisms can be modeled as a variationof the equivalent barrier height. In particular, any mechanisminducing a gate current increase/decrease because of tunnelingbarrier shape variation can be modeled as a barrier height re-duction/increase in an equivalent triangular barrier. Therefore,a current increase can be justified by positive charge trapping orby negative charge detrapping within the oxide both thinning outthe tunneling barrier, while a current decrease can be attributedto positive charge detrapping or negative charge trapping boththickening the tunneling barrier. For the same reason, trap-as-sisted tunneling can also be modeled as a variation of the equiv-alent barrier height. Deviations from the expected FN behaviorhave been modeled by many authors taking into account severaldifferent combination of charge location within the oxide, andsign and density of the trapped charge [7]–[9]. Since the sameresult can be obtained by tailoring in different ways these chargeparameters, any speculation about a physical phenomenon ableto produce the actual change in the equivalent barrier height isnot intentionally discussed. Further investigations and experi-mental measurements are required to help in determining theactual “erratic” physical mechanism responsible for the equiv-alent barrier changes.

VI. CONCLUSION

Erratic behaviors in Flash memories have been studied by an-alyzing experimental erasing curves during single erase proce-dures characterized by sequences of box pulses with increasingamplitude.

The erasing curves for a cell exhibiting normal behavior havebeen found to reach asymptotically a straight line, here calledthe erasing level, and can be regarded as a cell attribute for agiven set of electric parameters.

Erratic bits exhibit an abnormal behavior characterized byone or more level transitions during a single erasing curve. Atheoretical analysis has correlated these transitions to a changeof the equivalent barrier height controlling FN injection.

Future works can be addressed to investigating the actualphysical mechanisms able to produce the observed changes inthe equivalent barrier height. The slow dynamics of level transi-tions, the time randomness of the level changes, and the occur-rence of more than one transition within the same cycle requirea deeper investigation.

APPENDIX

DERIVATION

We here derive the expression for from that ofduring each erasing pulse by extending the theory developedin [10], [11]. By neglecting semiconductor band bendingand charge trapped within the tunneling oxides, can beexpressed as that, taking into account(1), becomes

(9)

where

(10)

has been used to express the ratio as a function of thetwo more measurable quantities and .

For the -pulse, with , the following expres-sions can be written.

(11)

where is the drain-to-bulk voltage that is a time variantquantity due to the existance of the capacitance coupling rep-resented by . However, the values of are so small in thepractical cases that for the rest of the treatment, we will consider

as a constant. V is the source-to-bulk voltagethat has been kept constant during each erase. Taking into ac-count that during the th pulsecan be written as

(12)


Since , by defining as in (6), always positivein our measurements, eventually becomes

(13)

Since varies during a single erasing pulse, (13) indicatesthe electric field in any time during theth erasing pulse. Itis possible, however, to calculate at the beginning and atthe end of any pulse from the corresponding and ,denoting at the beginning and at the end of an erasing pulse,respectively.

During any single erasing pulse, the source, control gate, andbulk voltages are constant and only varies. By deriving eachmember of (13), we obtain

(14)

The gate current can be expressed as the variation of thefloating gate charge and, taking into account (10), it becomes

(15)

and, by considering (14) and the FN expression (2)

(16)

By integrating each member from the beginning of a genericpulse to the end of the same pulse

(17)

and

(18)

we find that at the end of an erasing pulse, the electric field is

(19)

and that the threshold voltage at the end of theth pulse is

(20)where and are defined as in (7) and (8), respectively, while

denotes the threshold voltage at the end of the previouspulse.

When the equilibrium condition is reached, for example afterthe th pulse, and moves on a straightline so that the quantity remains constantfor any . In particular

(21)

and (20), rewritten for , provides the expression forshown in (5).

REFERENCES

[1] T. C. Onget al., “Erratic erase in ETOX flash memory array,” inSymp. VLSI Technology, 1993, pp. 83–84.

[2] C. Dunnet al., “Flash EPROM disturb mechanisms,” inProc. Int. Rel.Physics Symp., 1994, p. 299.

[3] P. Cappelletti and A. Modelli, “Flash memory reliability,” inFlash Mem-ories, P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds. Norwell,MA: Kluwer, 1999, pp. 399–442.

[4] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells: Anoverview,”Proc. IEEE, vol. 865, pp. 1248–1271, Aug. 1997.

[5] M. Lenzinger and E. H. Snow, “Fowler–Nordheim tunneling into ther-mally grown SiO ,” J. Appl. Phys., vol. 40, p. 278, 1969.

[6] P Pellati and P. Olivo, “Automated test equipment for research on non-volatile memories,”IEEE Trans. Instrum. Measur., to be published.

[7] P. S. Ku and D. K. Schroder, “Charges trapped throughout the oxide andtheir impact on the Fowler–Nordheim current in MOS devices,”IEEETrans. Electron Devices, vol. 41, p. 1669, 1994.

[8] J. Lopez-Villanueva, J. Jimenez-Tejada, P. Cartujo, J. Bausells, and J.Carceler, “Analysis of the effects of constant Fowler–Nordheim-tun-neling injection with charge trapping inside the potential,”J. Appl. Phys.,vol. 70, p. 3712, 1991.

[9] R. Kies, T. Egilsson, G. Ghibaudo, and G. Pananakakis, “A method forthe assessment of oxide charge density and centroid in metal-oxide-semiconductor structures after uniform gate stress,”Appl. Phys. Lett.,vol. 68, p. 3790, 1996.

[10] A. Bhattacharyya, “Modeling of write/erase and charge retention char-acteristics of floating gate EEPROM devices,”Solid State Electron., vol.27, pp. 899–906, Oct. 1984.

[11] A. Kolodny, S. T. K. Nieh, B. Eitan, and J. Shappir, “Analysis and mod-eling of floating-gate EEPROM cells,”IEEE Trans. Electron Devices,vol. 33, pp. 835–844, June 1986.

Andrea Chimenton graduated in electronic en-gineering from the University of Ferrara, Italy, in2000, where he is currently working toward thePh.D. degree.

His research interests are in the area of nonvolatilememory characterization and reliability, and mod-eling of physical mechanisms controlling memorywriting.

Paolo Pellatigraduated in electronic engineering from the University of Ferrara,Italy, in 1997. In 2001, he received the Ph.D. degree in information engineeringfrom the University of Modena, Italy.

Since 2001, he has held a research contract with the University of Ferrara forthe design of dedicated instrumentation. His research interests are in the area ofelectronic instrumentation design, high-performance board design, nonvolatilememory characterization, and testing.

Piero Olivo graduated in electronic engineering in 1980 from the University ofBologna, Italy, where he received the Ph.D. degree in 1987.

In 1983, he joined the Department of Electronics and Computer Systems ofthe University of Bologna, where he became Associate Professor of ElectronicInstrumentation and Measurements in 1991. In 1993 he became a Full Professorof Applied Electronics at the University of Catania, Italy. In 1995, he joinedthe University of Ferrara, Italy. During 1986–1987 and autumn 1989, he was aVisiting Scientist at the IBM T.J. Watson Research Center, Yorktown Heights,NY. His research interests are in the areas of solid-state devices and IC designand test. In the field of solid-state devices, he has worked on SiOphysics,quantum effects, charge transport through thin SiOstructures, charge trappingin SiO , oxide breakdown and reliability, MOS measurements techniques, thinoxide properties, and nonvolatile memories characterization. In the field of ICdesign and test, he has worked on signature analysis testing, design for testabilitytechniques, fault modeling and fault simulation,I testing, self-checkingcircuits, and nonvolatile memory testing.

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Analysis of erratic bits in flash memories