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Kai Huang Analysis (II) Modular Performance Analysis (Real-Time Calculus)

Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

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Page 1: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Kai Huang

Analysis (II) Modular Performance Analysis

(Real-Time Calculus)

Page 2: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Timing analysis in general

Real-Time Calculus

MPA

1/2/2014 Kai.Huang@tum 2

Outline

Page 3: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

1/2/2014 Kai.Huang@tum 3

Timing Analysis Overview

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstr om. The worst-case execution-time problem—overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008

Page 4: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Formal Analysis vs. Simulation

e.g. delay

Real System Simulation Formal analysis

Best-Case

Worst-Case upper bound

lower bound

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Page 5: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Analysis and Design

Analysis: Infer system properties from subsystem properties.

Design: Build a system from subsystems while meeting requirements.

Embedded System = Computation + Communication + Resource Interaction

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Page 6: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Modular Performance Analysis

Service Model (Resources)

Load Model (Environment)

Performance Model

Processing Model (HW/SW)

Analysis

Analysis Results

Input traces

Formal specification

System Model

Application Architecture

Mapping Scheduling

UML sequence diagrams

Task graphs UML/SysML

diagrams

Formal specification

Component simulation

Measure- ments

Data sheets

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Page 7: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Abstract Models for Performance Analysis

Concrete Instance

Abstract Representation

Processor

Task

Input Stream

Service Model

Load Model

Processing Model

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Page 8: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Modular System Composition CPU BUS DSP

RM TDMA

GPC GPC

GPC GPC

GPC GSC

TDMA

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Page 9: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Abstract Models for Performance Analysis

Concrete Instance

Abstract Representation

Processor

Task

Input Stream R(t) R’(t)

C(t)

Service Model

Load Model

Processing Model ()

()

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Page 10: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Timing analysis in general

Real-Time Calculus

MPA

1/2/2014 Kai.Huang@tum 10

Outline

Page 11: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Event Stream Model: Arrival Curves

4

2 3

time [ms]

events Event Stream

maximum / minimum arriving demand in any interval of length 2.5 ms

2.5

Arrival Curve demand

interval [ms] 2.5

number of events in in t=[0 .. 2.5] ms

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Page 12: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Service Model (Resources)

t [ms]

availability

Resource Availability

maximum/minimum available service in any interval of length 2.5 ms

available service in t=[0 .. 2.5] ms

2.5

Service Curves service

D [ms] 2.5

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Page 13: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

A common event pattern that is used in literature can be specified by the parameter triple (p, j, d), where p denotes the period, j the jitter, and d the minimum inter-arrival distance of events in the modeled stream.

Example 1: Event Arrival Model

periodic

p

periodic jitter

p j d

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Page 14: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Example 1: Periodic (with Jitter)

periodic periodic with jitter

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Page 15: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Example 1: (p, J, d) model

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Page 16: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Consider a real-time system consisting of n applications that are executed on a resource with bandwidth B that controls resource access using a TDMA policy.

Analogously, we could consider a distributed system with n communicating nodes, that communicate via a shared bus with bandwidth B, with a bus arbitrator that implements a TDMA policy.

TDMA policy: In every TDMA cycle of length , one single resource slot of length si is assigned to application i.

Example 2: TDMA Resource

c c

appl.1 appl.2 appl. n appl.1 appl.2 appl. n

sn

... ...

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Page 17: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Service curves available to the applications / node i:

Example 2: TDMA Resource

B si

c si c-si c 2

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Page 18: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Event and Resource Models

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Page 19: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Examples: o computation (event – task instance, resource –

computing resource [tasks/second]) o communication (event – data packet, resource –

bandwidth [packets/second])

Greedy Processing Component (GPC)

remaining resources

FIFO buffer input event

stream

output event

stream

available resources

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Page 20: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Behavioral Description o Component is triggered by

incoming events.

o A fully preemptable task is instantiated at every event arrival to process the incoming event.

o Active tasks are processed in a greedy fashion in FIFO order.

o Processing is restricted by the availability of resources.

Greedy Processing Component

GPC

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Page 21: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Greedy Processing Component (GPC)

Conservation Laws

GPC R(t)

C(t)

R’(t)

C’(t) t

C(t)

R(t)

R’(t)

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Page 22: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

For all times u t we have R’(u) R(u) (conservation law). We also have R’(t) R’(u)+C(t)–C(u) as the output can not

be larger than the available resources. Combining both statements yields R’(t) R(u) + C(t) –

C(u).

Let us suppose that u* is the last time before t with an empty buffer. We have R(u*) = R’(u*) at u* and also R’(t) = R’(u*) + C(t) – C(u*) as all available resources are used to produce output. Therefore, R’(t) = R(u*) + C(t) – C(u*).

As a result, we obtain

Greedy Processing

t u*

B(t)

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Page 23: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Abstract Models for Performance Analysis

Concrete Instance

Abstract Representation

Processor

Task

Input Stream R(t) R’(t)

C(t)

Service Model

Load Model

Processing Model ()

()

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Page 24: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Abstraction

time domain cumulative functions

time-interval domain variability curves

GPC GPC

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Page 25: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

is called min-plus convolution

is called min-plus de-convolution

For max-plus convolution and de-convolution:

Relation between convolution and deconvolution

»

Some Definitions and Relations

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Page 26: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

The arrival and service curves provide bounds on event and resource functions as follows:

We can determine valid variability curves from cumulative functions as follows:

One proof:

Arrival and Service Curve

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Page 27: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Abstraction

time domain cumulative functions

time-interval domain variability curves

GPC GPC

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Page 28: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

The output stream of a component satisfies:

The output upper arrival curve of a component satisfies:

The remaining lower service curve of a component satisfies:

The Most Simple Relations

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Page 29: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Two Sample Proofs

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Page 30: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

The greedy processing component transforms the variability curves as follows:

Tighter Bounds

Without proof ... .

[al, au]

[bl, bu]

[bl’, bu’]

[al’, au’]

GPC

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Page 31: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Backlog & Delay Schedulability Close-form solution Modular and composition

Performance Analysis Based on Arrival Curves

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Page 32: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Delay and Backlog

maximum delay D

maximum backlog B

l

u

[al, au]

[bl, bu]

[bl’, bu’]

[al’, au’] GPC

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Page 33: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Proof of Backlog Bound

maximum backlog B

l

u

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Page 34: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Timing analysis in general

Real-Time Calculus

Modular Performance Analysis

1/2/2014 Kai.Huang@tum 34

Outline

Page 35: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

System Composition CPU BUS DSP

GPC GPC

GPC GPC

GPC

How to inter- connect service?

RM TDMA

Scheduling!

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Page 36: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Scheduling and Arbitration

FP/RM

GPC

GPC

EDF

EDF

RR

RR

GPS

GPC

GPC

sum

share

TDMA

GPC

GPC

TDMA

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Page 37: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

New HW behavior New SW behavior New scheduling scheme ...

Extending the Framework

RTC

This is the hard part…!

Find new relations:

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Page 38: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

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Wave Field Synthesis Example

Analysis model System view

Page 39: Analysis (II) Modular Performance Analysis (Real-Time ... · ACM Trans. Embed. Comput. Syst., 7(3):1–53, 2008 . Formal Analysis vs. Simulation e.g. delay Real System Simulation

Duration of Analysis Model Generation and Calibration

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Wave Field Synthesis Example