Analysis and Modeling of Hybrid Planar-Type Electromagnetic-Bandgap Structures and Feasibility Study on Power Distribution Network Applications

178 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 1, JANUARY 2008

Analysis and Modeling of Hybrid Planar-TypeElectromagnetic-Bandgap Structures and FeasibilityStudy on Power Distribution Network Applications

Ki Hyuk Kim, Member, IEEE, and José E. Schutt-Ainé, Fellow, IEEE

Abstract—A unified 1-D analysis model of hybrid planar-typeelectromagnetic-bandgap (EBG) structures is developed. Based onthe analysis results, three types of hybrid design methods to reducethe cutoff frequency of the EBG structures are discussed, and de-sign equations for their noise suppression bandwidths are derived.In order to simulate switching noise characteristics of the hybridplanar-type EBG structures, 2-D circuit level models are devel-oped and experimentally verified. With the developed circuit-levelmodels and CMOS active switching devices, feasibility studies onthe power distribution network design using the hybrid EBG struc-tures are conducted. The hybrid EBG structure with series lumpedchip inductors shows efficient noise suppression characteristics inboth the frequency and time domains; however, it has potential lim-itations because of its generation of higher switching noise voltagesdepending on power supply connection configurations.

Index Terms—Electromagnetic bandgap (EBG), power dis-tribution network (PDN), simultaneous switching noise (SSN),system-in-package/system-on-package.

I. INTRODUCTION

DUE TO the increasing need for cost-effective and mul-tifunctional electronic components, integration schemes

using system-in-package or system-on-package technologyhave been widely researched [1]. One of the critical designissues of such high-density systems is the reduction of noisecoupling between neighboring functional blocks, e.g., noisydigital and sensitive analog/RF circuits in the same system. Inaddition, continuous device scaling results in the reduction ofsupply voltage levels and corresponding noise margins, as aresult, the intra-noise coupling in the digital block also degradesthe performances of the digital circuit.

Inductive simultaneous switching noise (SSN) generated bythe digital circuits can propagate through both the on-chip andthe package/printed circuit board (PCB) level substrates. How-ever, fundamental mechanisms of the noise propagations arequite different; the noise signal in the on-chip substrate prop-agates through resistive paths of the substrate, and the sourcesof the package/PCB level noise coupling are cavity resonantmodes of the power distribution network (PDN) on the substrate.The PDN forms the rectangular cavity resonator, which has twoparallel metal patches and four magnetic sidewalls [2]. In the

Manuscript received May 24, 2007; revised September 8, 2007.The authors are with the Department of Electrical and Computer Engineering,

University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2007.912199

vicinity of the resonant frequencies, vertical transitions of thenoisy signals such as time varying power/ground via pins andvias of high-speed signals excite the cavity resonator structureand create standing waves.

Such electromagnetically coupled noise signals can be min-imized using a gapped-/island-type PDN [3], a resistive termi-nation method [4], and efficient bypassing techniques such asshorting vias and capacitive walls [5]. However, their practicalimplementations are limited by the multiple power supply re-quirements, narrow operating bandwidths, and large number ofadditional passive components.

Several mushroom- and planar-type electromagnetic-bandgap (EBG) structures are proposed to suppress the cavityresonant modes and the noise signal propagations on thepackage/PCB substrate [6]–[9]. However, it is difficult to de-sign the EBG structures, which have low cutoff frequency andwide stopband characteristics because of the low inductancesof the vias/bridges and the low capacitances of the patches.

Recently, several planar-type EBG structures have been pro-posed to reduce the cutoff frequency, and most of the efforts arefocused on increasing bridge inductances between patches byextending the lengths of the microstrip line bridges [8], [9]. Twohybrid planar-type EBG structures were also proposed; one in-creases the patch capacitances by using lumped chip capacitors[10], and the other increases the bridge inductances by usinglumped chip inductors [11].

In this paper, a 1-D analysis of the hybrid planar-type EBGstructures is conducted, and three types of hybrid EBG structuredesign methods to reduce the cutoff frequency are discussed.Noise suppression bandwidths for various enhanced hybridplanar-type EBG structures are derived using this analysis.

In Section III, 2-D circuit-level models of the hybridplanar-type EBG structures are developed in order to includedistributed effects of the EBG structures and co-simulatewith actual digital and analog/RF circuits. Accuracies of thedeveloped simulation models are experimentally verified bycomparing the simulated -parameter responses with the mea-sured data.

A feasibility study of the application of the hybrid planar-type EBG structures to the design of the PDN is conducted inSection IV. 16-bit CMOS output drivers are co-simulated withthe hybrid cutoff frequency-enhanced EBG PDN in both the fre-quency and time domains. Not only the noise suppression char-acteristics, but also the noise generation characteristics of thePDNs are discussed in order to explore the SSN characteristicsof each hybrid EBG structure.

0018-9480/$25.00 © 2007 IEEE

KIM AND SCHUTT-AINÉ: ANALYSIS AND MODELING OF HYBRID PLANAR-TYPE EBG STRUCTURES AND FEASIBILITY STUDY ON PDN APPLICATIONS 179

Fig. 1. Schematics of 1-D hybrid planar-type EBG PDN and correspondingequivalent circuits.

II. 1-D ANALYSIS OF HYBRID PLANAR-TYPE

EBG STRUCTURES

A. Description of 1-D Hybrid Planar-Type EBG Structures

Fig. 1 shows schematics of the th unit cell of the 1-Dhybrid planar-type EBG structure and corresponding lumpedequivalent-circuit models including all hybrid components andparasitics. The lumped circuit approximation is valid for metalpatches with a width of less than one-tenth of the guided wave-length in the patches. Components within the dotted rectanglecorrespond to the th unit cell of the EBG structure, whereand are the center-to-center and gap distance between twoneighboring metal patches, respectively, is the width of therectangular metal patches, and is the height of the dielectricsubstrate. The th unit cell consists of half of the th patch,one bridge, and half of the th patch. and arethe inductance and capacitance of each metal patch, respec-tively, is the gap capacitance between metal patches, and

and are the parasitic series capacitance andthe inductance of the bridge, respectively. andare the capacitance and parasitic inductance of the lumped chipcapacitors, respectively.

The values of and are calculated using the followingquasi-static equations [12]:

(1)

(2)

where and are the permittivity and permeability of freespace, respectively, and is the relative dielectric constant ofthe substrate.

Equation (3) is used to calculate the gap capacitances betweenthe patches [8] and [13]

(3)

is equal to the inductance of the microstrip lines be-tween the patches or that of the lumped chip inductors

depending on the physical implementation of the bridges.The inductance of the microstrip lines per unit length is givenby

(4)

where is the width of the microstrip line and is equal to 0.2nH/mm.

also varies depending on the physical implemen-tation of the bridges. Typical values for , which is thelargest when implemented using the lumped chip inductors areless than 0.3 pF for inductance in the 47–560-nH range [14],while typical values for are in the range of 0.6–1.2nH including the inductances of the via [15], which is calcu-lated using (5) [16] as follows:

(5)

where is the diameter of the via in millimeters and is equalto 0.2 nH/mm.

It is important to note that the capacitance ratios ofand are very small for typical package/PCBstructures, which have large patch width and low substratethickness.

B. Frequency Response of 1-D Planar-Type EBG Structures

The image parameter method [12] is used to analyze the fre-quency responses of the 1-D hybrid planar-type EBG structure.The image impedance of the EBG structure is given by

(6a)

where

(6b)

(6c)

and

(6d)

The previous two capacitance ratios are used to derive thenoise suppression bandwidths of the hybrid planar-type EBGstructures. Noise suppression bandwidth is defined as the dif-ference between the low-pass cutoff frequency ( )and the high-frequency limitation of the EBG structures. The de-rived equations show that ’s are only dependenton the values of ( ), , and . Therefore, thereare three different hybrid design methods to reduce the cutofffrequency of the planar-type EBG structures, and the derived

and high-frequency limitations of each hybridplanar-type EBG structure are summarized in Table I.

It is important to note that the EBG structure used in method 3has an additional passband due to the parallel resonance of

and , which limits the noise suppression band-width, and that the first resonant frequency of the EBG structureused in method 4 is lower than those of other EBG structuresbecause of its high dielectric constant.

The maximum noise suppression level, , is derivedusing a periodic -stage pi-type equivalent model, which


TABLE INOISE SUPPRESSION BANDWIDTHS OF CUTOFF FREQUENCY-ENHANCED HYBRID PLANAR-TYPE EBG STRUCTURES

consists of the shunt and series and

(7)

where is the number of unit cells and . Impedancemismatches between the unit cells are not considered in thederivation.

In order to predict the dispersive behavior of the hybridplanar-type EBG structures, the unit cells of each structure areanalyzed using parameters [13], which is given by

(8)

where and are the effective phase constant of the unit celland the phase constant of the patch, respectively, and and

Fig. 2. First passband of dispersion diagram for hybrid planar-type EBG struc-tures with parameters b = 13:7 mm, g = 1:3 mm, h = 0:4 mm, " = 4:4,C = 0:103 pF , and L = 1 nH. (a) Using method 2 with variableof L . (b) Using method 3 with variable of C .

are as follows:

(9)

(10)

Fig. 2(a) and (b) shows the first passband of the disper-sion diagram for the hybrid planar-type EBG structure usingmethod 2 with a variable of and that for the hybridplanar-type EBG structure using method 3 with a variable of

, respectively. In both cases, it is shown that, by increasing, the cutoff frequency of the hybrid planar-type

EBG structure is effectively reduced and the cutoff frequenciesof each structure from the dispersion diagram are in goodagreement with the calculated values using (7b) and (7c).


Fig. 3. Schematics and corresponding equivalent-circuit models for building blocks of hybrid planar-type EBG structures. (a) Patch. (b) Gap and bridge.(c) Lumped chip inductor. (d) Lumped chip capacitor. Synthesized EBG structure: (e) using method 2 and (f) using method 3.

III. CIRCUIT-LEVEL MODELING OF HYBRID

PLANAR-TYPE EBG STRUCTURES

2-D equivalent-circuit models of the planar-type EBG struc-tures are developed in order to include their distributed effectsand co-simulate the hybrid planar-type EBG structures with thedigital and analog/RF circuits. A commercial circuit-level simu-lator, Spectre from Cadence Design Systems Inc., San Jose, CA,is used in this study.

Fig. 3(a)–(d) shows the schematics and equivalent-circuitmodels for the metal patch (width ), gap and bridge betweenpatches (distance ), lumped chip inductor, and lumped chipcapacitor, respectively. They are basic building blocks of thehybrid planar-type EBG structures. Every EBG structure usingone of the design methods shown in Table I can be synthe-sized with those building blocks, e.g., the EBG structure usingmethod 2 consists of an array of metal patches and the gap withlumped chip inductors, while the EBG structure using method3 consists of an array of metal patches with lumped chip capac-itors and the gap between the patches. Fig. 3(e) and (f) showsthe 2-D circuit level simulation models of the EBG structuresusing methods 2 and 3, respectively.

The details of the equivalent-circuit models are explained asfollows.

A. Circuit-Level Modeling of Metal Patches

Fig. 3(a) shows the circuit-level model of the metal patch.Instead of the conventional merged plane models, the distributedplane models are used for the patch in order to describe thecurrent voltage variations on the ground and power planes [17].An array of RLC cells is used to model each patch, where

is dependent of the guided wavelength in the substrate and, inthis study, is equal to 10. The dielectric constant of the substrateis 4.4, the maximum analysis frequency is 6 GHz, and the sizeof the RLC cell is an approximate 1/20 of the guided wavelengthat the maximum frequency.

B. Circuit-Level Modeling of Gap Between Patches

Fig. 3(b) shows the circuit-level model of the gap and thebridge between the patches. Nine-section distributed capacitorsand a single-section inductor are used to model the gap capac-itance and the inductance of the microstrip line bridge. In thecase where the lumped chip inductor is used as the bridge, theinductor model of the microstrip line is replaced by the lumpedchip inductor model in Fig. 3(c).

Previous studies on planar-type EBG structures use (3) to cal-culate the gap capacitances [8], [13]; (3), however, was derivedunder the assumption that there is only a pair of patches withoutthe ground plane [18]. This assumption is true for the mush-room-type EBG power plane without the ground plane becausethe metal patches are connected to the power plane through vias.However, in the case of the planar-type EBG structures, the pres-ence of the ground plane reduces the value of .

In [19], equations for the coupled microstrip lines are used tocalculate the gap capacitances with the ground plane considered,and details of design formulas are found in [20].

Fig. 4(a) and (b) shows the calculated and simulated values ofthe gap capacitances for the planar-type EBG structures with thecenter-to-center distances of 15 and 30 mm, respectively. Thethickness of the dielectric substrate vary from 0.4 to 1.6 mm with0.4-mm steps, and the gap distances are 5%, 7.5%, and 10% ofthe patch widths. Equation (3) and the equations in [20] are usedto calculate the gap capacitances, and Maxwell 2-D SV, a com-mercial 2-D quasi-static R, L, and C extractor from the AnsoftCorporation, Pittsburgh, PA, is used to numerically simulate thegap capacitances. Both of the analytic equations overestimatethe gap capacitances, as shown in Fig. 4. The calculated gapcapacitances using (3) is independent with the height of the di-electric substrate because the ground plane is not considered inthe derivation of (3) [18]. Equations for the gap capacitances in[20] were obtained empirically with limited ranges of the phys-ical dimensions that are applicable to microstrip lines. As a re-sult, the calculated gap capacitances between the large widthcoupled patches are not accurate. As expected, the calculation


Fig. 4. Calculated and simulated values of gap capacitances. (a) a = 15 mm.(b) a = 30 mm.

Fig. 5. EBG structure using method 2. (a) Fabricated PCB. (b) Simulated andmeasured jS21j responses.

errors are inversely proportional to the heights of the dielectricsubstrate. In this study, the numerically simulated gap capaci-tances are used to model .

C. Circuit-Level Modeling of Lumped Chip Inductorsand Capacitors

First-order parallel LC and first-order series LC models areused to model the lumped chip inductors and lumped chip ca-pacitors, respectively. The parasitic parallel capacitances of thelumped chip inductor and the parasitic series inductances of thelumped chip capacitor are calculated using their self resonantfrequencies (SRFs) provided by the chip components’ vendors[14], [15]. Fig. 3(c) and (d) shows the circuit level of the lumpedchip inductor and lumped chip capacitor, respectively.

TABLE IIDESIGN PARAMETERS OF HYBRID PLANAR-TYPE EBG PDNS

Fig. 6. Frequency-domain characteristics of hybrid EBG PDNs. (a) jS21j re-sponses of EBG PDN using method 2. (b) jS21j responses of EBG PDN usingmethod 3.

D. Verification of Circuit Level Models for HybridPlanar-Type EBG Structures

The accuracy of the developed 2-D circuit level simulationmodels is experimentally verified. Fig. 5(a) shows the fabricatedhybrid planar-type EBG structure using method 2 in Table I. Thewidth of the patch and the gap distance between the patches are13.7 and 1.3 mm, respectively. The thickness and dielectric con-stant of the substrate are 0.4 and 4.4 mm, respectively. Locationsof two measurement ports are also shown in Fig. 5(a). Twelve560-nH lumped chip inductors with 0.16-pF parasitic series ca-pacitance are used as the bridges.


Fig. 7. Chip-PDN co-simulations. (a) 16-bit output drivers. (b) Input voltage waveforms with 500- and 2500-ps rise times. (c) Output voltage waveforms.(d) Transient short-circuit currents. (e) 2-D solid PDN. (f) Hybrid EBG PDN using method 2/method 3.

Fig. 5(b) shows the measured and simulated frequency re-sponses of the EBG structure and a 2-D solid plane pair, whichhas the same area as that of the ground plane of the EBG struc-ture. The Agilent E8358A PNA series vector network analyzer(VNA) is used to measure the -parameters from 300 kHz to6 GHz. Solid lines and the crosses correspond to simulated andmeasured responses for the 2-D solid plane pair, respec-tively, while solid rectangles and open circles represent the samerespective quantities for the EBG structure. The 2-D circuit levelsimulations accurately predict the measured responses ofboth of the EBG structures, except for the levels of the inser-tion loss. The calculated maximum insertion loss using (7) is

130 dB, which shows a good agreement with the 2-D simula-tion results. The discrepancy in the noise suppression levels isdue to the noise floor of the VNA. The measured ,which is defined as a frequency where the responses startto decrease monotonically, is 106.1 MHz, while the calculatedand the simulated values are 99.4 and 99.5 MHz, respectively.

In Fig. 5(b), the measured peak of the EBG structure at5.14 GHz, corresponds to the resonant mode of thepatches, which have an area of 13.7 13.7 mm , while sev-eral resonant peaks of the 2-D solid plane pair correspond tothe cavity resonant modes of the 45 45 mm area patch.Basically, the hybrid planar-type EBG structures enhance thenoise suppression bandwidth by reducing the width of the unitcells and, consequently, by moving the first resonant frequencyhigher [11] and [21].

IV. FEASIBILITY STUDY ON POWER DISTRIBUTION

NETWORK DESIGN APPLICATION

Previous studies on PDN design using EBG structures haveconsidered only the noise signal suppression characteristicsof the EBG structures by measuring insertion losses such as

responses. Here, three different cutoff frequency-enhancedhybrid planar-type EBG structures using methods 2–4 aredesigned, and their feasibility for PDN application are studiedusing both the frequency- and time-domain simulations withthe noise generation characteristics of the EBG structuresconsidered by including CMOS active switching devices in thetime-domain simulations.

A. Noise Suppression Characteristics and EBGPDN—Frequency-Domain Analysis

We arbitrarily set the target cutoff frequency of the EBGPDNs to be 300 MHz, and the calculated circuit-level parame-ters of each EBG PDN using the derived equations in Section IIare summarized in Table II.

It is important to note that the dielectric constant of 269 inTable II is not a realistic value, moreover, the high dielectricconstant with the same patch width of the patch results in low-ered , which limits the noise suppression band-width of the EBG PDN. The first resonant frequency of thatstructure is only 668 MHz, and for such reasons, the EBG PDNusing method 4 is excluded in this study. High dielectric con-stant embedded capacitors also have limited noise suppressionbandwidths due to the same reason.

The schematics and the 2-D circuit-level simulation modelsof each EBG PDN are shown in Fig. 3(e) and (f), and the loca-tions of ports 1 and 2 are (5 mm, 5 mm) and (40 mm, 40 mm),respectively.

Fig. 6(a) and (b) shows the simulated responses of thehybrid EBG PDNs using the 1-D and 2-D circuit-level models.The simulated ’s of the EBG PDN using method2 are 269 MHz (1-D models) and 358 MHz (2-D models), re-spectively, while the simulated ’s of the EBGPDN using method 3 are 300 MHz (1-D models) and 270 MHz


(2-D models), respectively. They show good correlations withthe calculated value of 300 MHz using (7b) and (7c).

The noise suppression bandwidth of the EBG PDN usingmethod 2 is limited by the first resonant frequency of thepatches, which is equal to 5.14 GHz. However, that of theEBG PDN using method 3 is limited by the parallel resonantfrequency of and , which is equal to 1.18 GHz.The bandwidth of the passband is determined by the couplingfactor between the parallel resonators, which is equal toplus .

B. PDN Applications of Each EBGStructure—Time-Domain Analysis

In order to study the feasibilities of the PDN applications,the developed 2-D circuit level simulation models of the EBGPDNs are incorporated with 16-bit output drivers, which aredesigned using United Microelectronics Corporation (UMC)0.13- m digital CMOS technology, and are supposed to gen-erate the SSN. Including the active circuits results in morerealistic switching noise characteristics of the EBG PDNsbecause the noise generation characteristics are considered.Packaging related parasitic components such as pad capacitanceand bond-wire or lead-frame inductance are not included in thesimulations. Only parasitics of the PDN are considered.

Fig. 7 shows the schematics of the chip-PDN co-simu-lation environments including: (a) the CMOS 16-bit outputdrivers, (b) the input voltage waveforms with 500- and 2500-psrise times, (c) the output voltage waveforms, and (d) theshort-circuit transient current waveforms, respectively. Theinput voltages with 500- and 2500-ps rise times result inthe short-circuit transient currents with 106- and 735-ps risetimes, which correspond to signal bandwidths of 3.3 GHz and476 MHz, respectively. The output drivers are designed usingCMOS inverters, which have dimensions of 80 m/0.13 mfor pMOS and 40 m/0.13 m for NMOS. VDD_SUPPLYand GND_SUPPLY stand for the locations of the VDD andGND connections between the dc power supply and the PDN,respectively, while VDD_CHIP and GND_CHIP are the lo-cations of the VDD and GND connections between the PDNand the chip, which embed the CMOS 16-bit output drivers.By co-simulating the PDNs with the output drivers, the noisegeneration characteristics, as well as the noise suppressioncharacteristics, can be analyzed.

Three different types of PDNs are considered. Fig. 7(e) showsthe schematics of the 2-D solid plane pair PDN and Fig. 7(f)shows the EBG PDN with the series lumped chip inductors(method 2) or the shunt lumped chip capacitors (method 3). Thelocations of all ports are also shown in Fig. 7(e).

Fig. 8(a)–(c) shows the generated (port 1) and propa-gated (port 4) noise voltages on the 2-D solid PDN, EBGPDN using method 2, and EBG PDN using method 3,respectively for 2500-ps rise time of the input voltages.The VDD_/GND_SUPPLY and VDD_/GND_CHIP con-nections are located in the same patch; specifically theVDD_/GND_CHIP connections are located at port 1 and theVDD_/GND_SUPPLY connections are located at (0 mm,5 mm). The generated noise voltages during the transient timesare similar to each other; however, the waveforms of the excited

Fig. 8. Generated and propagated noise voltages with rise time of 2500 ps.VDD_/GND_CHIP and VDD_/GND_SUPPLY connections are located at thesame patch. (a) 2-D solid PDN. (b) EBG PDN using method 2. (c) EBG PDNusing method 3.

noise voltages are quite different. Due to the wide bandwidthof the transient current, several resonant frequencies are ex-cited, e.g., the excited frequencies of 416 MHz, 1.76 GHz,and 299 MHz correspond to the series resonant frequencies ofthe VDD_SUPPLY to GND_SUPPLY loop for the 2-D solidPDN, the EBG PDN using method 2, and the EBG PDN usingmethod 3, respectively. In consequence, the wide stopbandcharacteristics of the EBG PDNs are essential to suppress thepropagation of the generated switching noise. The EBG PDNusing method 2 generates the largest amplitude of switchingnoise voltage due to its inductive boundary conditions. Theamplitudes of the excited noise voltage are dependent on thefrequency components of the short-circuit currents and theinput impedance at the VDD_/GND_SUPPLY connections.

For brevity, only the propagated noise voltages at port 4 oneach PDN are plotted. The noise voltage suppression ratios,which are defined as the ratio of the propagated noise voltage ofthe EBG PDN using method 2 or 3 to that of the 2-D solid planePDN, are 11% for the EBG PDN using method 2 and 33.3%for the EBG PDN using method 3. The frequencies of the prop-agated noise voltages correspond to the passband frequenciesof the EBG PDNs shown in Fig. 6(a) and (b). Notice that the


Fig. 9. Generated and propagated noise voltages with rise time of 500 ps.VDD_/GND_CHIP and VDD_/GND_SUPPLY connections are located at thesame patch. (a) 2-D solid PDN. (b) EBG PDN using method 2. (c) EBG PDNusing method 3.

frequencies of the generated noise voltages at port 1 and thepropagated noise voltages at port 4 are not identical because thefrequencies of the generated noise voltages are dependent on theinput impedances at the VDD_/GND_SUPPLY connections.

Fig. 9(a)–(c) shows the generated (port 1) and propagated(port 4) noise voltages on the 2-D solid PDN, EBG PDN usingmethod 2, and EBG PDN using method 3, respectively for500-ps rise time of the input voltages. Due to the narrow noisesuppression bandwidth of the EBG PDN using method 3, thesuppression noise voltage ratio is degraded to 76%.

C. Drawback for Hybrid EBG PDN Using LumpedChip Inductors

It is important to note that if the VDD_/GND_SUPPLY andVDD_/GND_CHIP connections are not located in the samepatch, then the increased inductance of the VDD_SUPPLY toVDD_CHIP path results in a large amount of switching noise.As shown in Fig. 7(d), the switching current waveforms havewide bandwidth of the frequency components, however, theEBG PDNs block not only the propagation of the switchingnoise voltages to other patches, but also the sourcing/sinkingof the currents from the VDD_/GND_SUPPLY connections,

TABLE IIISUMMARY OF NOISE GENERATION AND SUPPRESSION CHARACTERISTICS

OF EBG STRUCTURES USING METHODS 2 AND 3

which are connected at other patches. This increases the ef-fective inductance of the VDD_SUPPLY to VDD_CHIP pathof the EBG PDN and corresponding switching noise voltage,which is given by

(11)

where is the number of the switching gates, is the timederivative of the switching current, and , , andare the effective inductance of the VDD plane, that of the groundplane, and mutual inductance between them of the EBG PDN,respectively. The increased inductance of the VDD_SUPPLY toVDD_CHIP path is a potential limitation of the EBG applicationto the PDN designs and the hybrid EBG PDN using the lumpedchip inductors are only applicable to package designs. Previ-ously published planar-type EBG structures [8], [9] have thesame limitations due to the bridge inductances. Table III sum-marize the switching noise generation and suppression charac-teristics of EBG structures using method 2 and method 3.

V. CONCLUSION

In this paper, a 1-D analysis model of the hybrid planar-typeEBG structures is developed. Based-on the analysis results, de-sign equations, which define the noise suppression bandwidthof EBG structures, are derived and three different hybrid designmethods to reduce the cutoff frequency of the EBG structuresare discussed. 2-D circuit-level simulation models are also de-veloped and experimentally verified. Using the developed 2-Dcircuit-level simulation models, two types of cutoff frequency-enhanced EBG structures are co-simulated with CMOS 16-bitoutput drivers to study on the feasibilities of the PDN appli-cations. The hybrid EBG PDN using the lumped chip induc-tors shows efficient noise suppression characteristics in both thefrequency and time domains. However, the increased effectiveinductance between the power supply and active circuits whenthey are not connected in the same plane results in considerableswitching noise voltages, which are potential limitations for theapplication of PDN design.

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Ki Hyuk Kim (M’05) received the Ph.D. degreein electronics engineering from Korea University,Seoul, Korea, in 2005.

From 2001 to 2005, he was with Solid Technolo-gies Inc., Seoul, where he was involved in researchand development on mobile communication equip-ments for (W)CDMA and Wibro, as a member of theresearch and development staff. He is currently withthe Department of Electrical and Computer Engi-neering, University of Illinois at Urbana-Champaign,where he is a Post-Doctoral Researcher. His research

interests are in the design of mixed-signal/RF integrated circuit and board-levelhigh-frequency systems using system-in-package (SiP)/system-on-packagae(SoP) technology.

José E. Schutt-Ainé (S’86–M’86–SM’98–F’07) re-ceived the B.S. degree in electrical engineering fromthe Massachusetts Institute of Technology (MIT),Cambridge, in 1981, and the M.S. and Ph.D. degreesfrom the University of Illinois at Urbana-Champaign(UIUC), in 1984 and 1988, respectively.

Upon graduation, he joined the Hewlett-PackardTechnology Center, Santa Rosa, CA, as an Applica-tion Engineer involved with microwave transistorsand high-frequency circuits. In 1983, he joinedUIUC, and then joined the Electrical and Computer

Engineering Department as a member of the Electromagnetics and CoordinatedScience Laboratories where he currently specializes in the study of signalintegrity for high-speed digital and high-frequency applications. He has beena consultant for several corporations. His interests span the spectrum frommicrowave measurements to the generation of computer-aided design (CAD)tools for electronic systems.

Dr. Schutt-Aine was the recipient of several research awards including the1991 National Science Foundation (NSF) MRI Award, the 1992 National Aero-nautics and Space Administration (NASA) Faculty Award for Research, the1996 NSF MCAA Award, and the 2000 UIUC–National Center for Supercon-ducting Applications (NCSA) Faculty Fellow Award. He currently serving asEditor-in-Chief of the IEEE Transactions on Advanced Packaging.

Documents

Analysis and Modeling of Hybrid Planar-Type Electromagnetic-Bandgap Structures and Feasibility Study on Power Distribution Network Applications