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Analysis and Implementation of LLC Burst Mode for Light Load Efficiency Improvement
Bin Wang, Xiaoni Xin, Stone Wu, Hongyang Wu, Jianping Ying
Delta Power Electronics Center 238 Minxia Road, Caolu Industry Zone, Pudong, Shanghai, 201209, China
Tel: 86-21-68723988, Fax: 86-21-68723996, Email: [email protected] Abstract—Burst mode control is applied to improve light load efficiency of LLC converter in this paper. Detailed analysis on characteristic and operation processes of LLC burst mode control with SR is presented. Based on the analysis, some important rules of LLC burst mode control are proposed, which is the key to achieve high light load efficiency. The rules include: the suitable primary and secondary driving timing, design guild line of output filter, reasonable control strategy etc. To verify the analysis, a prototype with 12V/100A output has been built. Thanks to the proposed control strategy and optimum design, light load efficiency of LLC converter can be improved significantly, such as efficiency at 10% load can be improved from 92.5% to 94.8%.
I. INTRODUCTION
Efficiency requirement of power supply is going higher and higher recently, and the efficiency demand is not only focused on heavy load but also on light load. And several companies and organizations have presented their own requirements for light load efficiency.
a) LLC series resonant converter with SR
LLC series resonant converter draws much attention nowadays because high efficiency can be achieved with proper SR control methods. But its light load efficiency is not comparative with its high efficiency at heavy load.
Fig.1 shows the circuit diagram of full bridge LLC series resonant converter. This topology can achieve ZVS turn on and low turn off current of Q1~Q4 and ZCS of Q5~Q6 from zero to full load range [1], but this brings some constant loss because of its operation principle. Fig.2 shows LLC converter key waveforms at light load. Zero-cross SR control method [2] is applied. SR MOSFETs Q5, Q6 are turned on at the same time when corresponding primary MOSFETs are turned on, and turned off at zero-cross point of synchronous current. This control method results in that switching frequency varies a
Q1 Q2
Q3 Q4
Q6
Q5
Lr
Cr
Lm
ipo
iLr
iLm
T
Vo
Figure 1. Circuit diagram of LLC series converter
VQ1,VQ4
VQ2,VQ3
VQ5
VQ6
A
A
iLr
iLm
Figure 2. Key waveform of LLC converter at light load
little from zero load to full load, and it can prevent frequency from going too higher at light load. But it also results in that magnetizing current iLm at light load is the same as heavy load, and output current flows reversely from secondary to primary in area A at light load. That will cause large switching loss; core loss and conduction loss at light load.
Table.1 shows LLC loss breakdown at 10 A load. The loss mainly includes switching loss, core loss and conduction loss. The efficiency of power stage is only 92.5%, and if driver loss and control loss are considered, the conversion efficiency is only about 89.8%. The loss of lower load is almost the same as that at 10A, so the efficiency will be much lower at load lower than 10A.
TABLE I Loss breakdown of LLC converter at 10% load
Switching loss 5.3W
Core loss 2.4W
Conduction loss 2 W
Driver loss 2.7W
Control loss 1W
b) Burst mode control
Burst mode control is widely applied to improve light load efficiency, usually in portable devices. This control method blocks original switching driver signals periodically, and power conversion only happens during the time having driver signals, so it can reduce driver loss and switching loss a lot [3]. But this method is used to reducing loss at extreme light load in order to consume less power at standby mode [4]. If this control
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method is applied for light load efficiency improvement of high power LLC converter with SR, several aspects need to be studied carefully.
So, this paper focuses on the characteristic of burst operation of LLC converter with SR, and detailed analysis on operation processes and power loss is presented in the first section. The design consideration of output filter is discussed in secondary section. Besides, this paper proposes a piecewise control method to ensure that the highest efficiency can be achieved at different load point. The experiment results of a 1200W/12V prototype demonstrate that efficiency can be improved at load range from 0%-15% by optimum design.
II. BURST OPERATION ANALYSIS
Burst operation processes are shown in Fig.3, t0 to t3 is a whole burst operation period Tburst, and burst frequency fburst=1/Tburst is defined. The whole period can be divided into three stages.
VQ2,VQ3
VQ1,VQ4
burst duty
VQ5
VQ6
Vo
t0 t1 t2 t2' t3
Vds
iLr
iLm
Vt
Figure 3. Waveform of burst operation
a) Burst operation process (1) Stage 1 of burst operation
The first stage (t0-t1) is the resonant energy established time. The driver signals are blocked before this stage. The initial condition at t0 is assumed that:
Voltage of switch Q1 is VQ1(t0), Resonant current iLm(t0) is zero, Voltage of resonant capacitor Cr is VCr(t0). Then at t0, driver signals are recovered, switch Q1, Q4 and
Q2, Q3 are turned on alternately. Suppose that the first switch turned on is Q1 in this stage, so parasitic capacitor of Q1 is discharged to zero and that of Q2 is charged to Vin. This hard switching process will cause power loss:
CosstVVinP Qh ⋅⋅=∆ )0(2 1 (1)
After this hard switching, input voltage Vin is cross the
resonant tank: Lr, Cr and Lm. So resonant current iLr begins to circulate, primary transformer voltage Vt begins to rise and
secondary diodes keep reverse biased until Vt rising to )( FDVVoN +⋅ , if diode rectifying is applied.
Q1 Q2
Q3 Q4
Q6
Q5
Lr
Cr
Lm
ipo
iLr
iLm
T
Vo
+ -
Figure 4. Equivalent working circuit in stage 1
Fig.4 shows the equivalent working circuit in this stage, and Vt(t), iLr(t), VCr(t) during this stage can be deduced:
)/()0(cos))0(()( mrrCr LLrLttwtVVintVt +⋅−−= (2)
rrCrLr ZttwtVVinti /)0(sin))0(()( −−= (3)
)0(cos))0(()( ttwtVVinVintVcr rCr −−−= (4)
where CrLLrw mr ⋅+= )(/1 , CrLLrZ mr /)( += .
From the (2), it can be seen that Vt(t) can not rise higher than )( FDVVoN +⋅ in first half cycle, because
VinVVoN FD 1.1)( ≈+⋅ is designed and VCr(t0) is positive which can be deduced later, secondary diodes will not conduct with diode rectifying. But if secondary synchronous MOSFET is turned on with SR control scheme mentioned above, the output voltage will be cross the transformer and magnetizing inductance Lm instantly, which will produce reverse current flowing from secondary to primary side and cause large power loss, so discarding SR driving signal is the optimum operation in this stage. Resonant current iLr(t) increases from zero to iLr(t1) and VCr(t) is charged to VCr(t1) higher than VCr(t0). Resonant energy is established during this stage to ensure power transmission in next stage.
Power loss of this period includes the hard switching loss hP∆ and conduction loss , core loss 1conP∆ 1coreP∆ and
switching loss 1swP∆ which can be assumed as half cycle loss of normal operation at light load.
burstswcorecon
h fPPP
PP )2
(1++
+∆=∆ (5)
where: , , are conduction loss, core loss and switch loss of each cycle without burst control at light load.
conP coreP swP
(2) Stage 2 of burst operation
The second stage (t1-t2) is power conversion time. Q1, Q4 are turned off at t1, and after a short deadtime, Q2 and Q3 are turned on. Generally, this switching is soft or partial soft because of iLr(t1) established. After this switching, Vin is added to the resonant tank. Vt(t) of this time can be deduced:
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)1sin()1()1(cos))1(()(
tttIZttwtVVintVt
Lrr
rCr
−−−−−=
(6)
where CrLrwr ⋅= /1 , CrLrZr /= .
Through carefully design, Vt(t) will be higher than at this time, and diodes of secondary side will
conduct because V)( FDVVoN +⋅
Cr(t1) is positive and resonant capacitor has been charged for a half switching cycle. SR control can be used in this stage, and operation process is just the same as normal.
Power transmits from primary side to secondary side during this period, and high efficiency is pursued. So, working cycles during this period should be designed to work at as load with high conversion efficiency. That determines the length of this stage which can be defined as burst duty.
Lh
Lburst I
iD = (7)
where: iL is the load current currently, ILh is the load current with high efficiency.
From (7), Dburst should be regulated with load to maintain same operation condition of each working cycle with various load condition. But resonant current will vary in each operation cycle due to increasing Vo in each cycle. Before this stage, load is supplied by output capacitor Co, and Vo falls to Vo(t1)—the lowest voltage value during the whole burst period. After t1, Co is charged in each switching cycle, and Vo increases gradually in this stage, then Vo reaches the highest point at t2. iLr(t)’s variety is opposite to Vo, the resonant current decreases gradually in this period, the highest value is produced at the first switching cycle. So efficiency of each cycle is not the same, and the efficiency of whole period is the mean value of all cycles.
The loss of this period is distributed just as the normal operation, including switching loss, core loss and conduction loss. So the power loss can be estimated approximately as:
∑=
⋅+++=∆N
ibursticapicoreiconisw fPPPPP
1____2 )( (8)
where: , and are corresponding conduction loss, core loss and switching loss of each cycle with normal operation at heavy load. is output capacitor loss of each cycle mainly caused by ESR and is large in this stage because of large pulse charging current. This loss will be discussed in next section in detail.
iconP _ icoreP _ iswP _
icapP _
If it is assumed that resonant current of each cycle is the same and has the same efficiency, the loss can be calculated as:
swburstcapcoreconsw fDPPPPP ⋅+++=∆ )(2 (9)
where: , and are conduction loss, core loss and switching loss of each cycle with normal operation at
heavy load. is capacitor loss of each cycle, and is switching frequency of heavy load at normal control.
conP coreP swP
capP swf
(3) Stage 3 of burst operation
The last stage (t2-t3) is idle time, and driving signals are blocked during this stage. This stage can be subdivided into two stages. The first one is time from t2 to t2’ and the other is from t2’ to t3.
Figure 5. Equivalent working circuit from t2 to t2’
At time t2, Q1 and Q4 have been turned off, so resonant current discharges parasitic capacitor of Q2 and charges parasitic capacitor of Q1, and same thing happens to Q3 and Q4. Fig.5 shows the equivalent working circuit in this sub-stage. The parasitic capacitors of Q2 and Q3 will be discharged to zero and that of Q1 and Q4 will be to Vin, then this current will charge the primary capacitor through body diodes of Q2, Q3 until iLr(t) decreases to zero. Meanwhile, secondary diodes will conduct, and iLr(t) will charge output capacitor through transformer until iLr(t) is lower than iLm(t). iLr(t) and VCr(t) can be deduced in this period:
)2(sin)2()2(cos)2()(
ttwZr
tVcrVoVinttwrtiLrtiLr
r −−−−
+−= (10)
)2(sin)2()2(cos))2(()(
ttwtzriLrVoVinttwtVcrVoVintVcr
r
r
−+−−−−−−−=
(11)
where CrLrwr ⋅= /1 , CrLrZr /= .
At the end of this period, VCr(t) will be charged higher than VCr(t2) which is the highest value at normal operation, and iLr(t) will be discharged to zero. Then, body diodes of Q2 and Q3 are reverse biased, resonant components including parasitic capacitors of primary and secondary switches, resonant inductor, resonant capacitor and magnetizing inductor begin free oscillation. The equivalent circuit is shown in Fig.6. Cp1 is the parasitic capacitors of Q1 and Q3, Cp2 is that of Q2 and Q4, and Cs is the parasitic capacitors of secondary switches.
Figure 6. Equivalent working circuit from t2’ to t3
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This oscillating energy will attenuate step by step for consumption by ESR of inductors and EPR of capacitors. At the end of oscillation, the resonant current will attenuate to zero, and the voltage of capacitors after oscillation can be calculated:
))'2((2
)3(1
tVVinCpCr
CrtV CrC p+
+= (12)
where: is paralleled capacitance of two primary switches. pC
Because Cp is much smaller than Cr, almost one tenth of Cr; and VCr(t2’) is comparable with Vin, VCp1(t3) will be larger than Vin/2. So, if Q1 and Q4 are chosen to turn on firstly in next burst period, less hard switching loss in stage 1 will be achieved.
The power loss in this stage mainly includes conduction loss and core loss. Loss produced in first sub-stage can be calculated as one quarter of conduction loss and core loss of normal operation. Energy remained in resonant tank is little, so loss produced by oscillation can be neglected. So power loss in this stage is:
burstcorecon f
PPP
43+
=∆ (13)
where: and are conduction loss and core loss of each cycle with normal operation at light load.
conP coreP
b) Loss analysis of burst operation
From analysis above, we can get whole power loss of the burst operation as:
321 PPPP ∆+∆+∆=∆ (14)
According to (14), burst frequency and duty affect the
efficiency a lot. Loss produced during stage 1 and 3 will be larger with higher burst frequency and lower frequency will cause audible noise and affect a lot on operation in stage 2 because low burst frequency will produce large output ripple, resonant current in each working cycle will be much different, so high efficiency in each cycle can not be realized. But this influence on stage 2 is not reflected in this equation, and same operation condition of each cycle of stage 2 is assumed.
Fig.7 shows the loss calculated with various load. The burst frequency selected is 10K, 50K and 100K, and the dashed line show the loss at light load with normal control. It can be seen that the loss increases with load under burst control, and will be larger than loss of normal control at some load point. Fig.8 shows the loss curve varying with different burst frequency, and load condition is 5A, 10A, 15A and 20A. Low loss can be achieved with low frequency.
The influence of burst duty is clear. If Dburst calculated is not applied, each cycle of stage 2 will not work at load with high efficiency, so high efficiency of burst control can not be ensured.
0 5 10 15 200
5
10
Io
100K
Loss
(W)
50K
10K
A
iL
Figure 7. Loss calculated with various loads
1 .100
3
6
9
12
20A
15A
Loss
(W)
10A
Figure
Fig.9 showloss shown inloads, and itefficiency. If applied, the ldashed line an
0
5
10
Loss
(W)
F
c) Summary
Based on operation, seachieve the hi
The fpreve
Burstcurrencurren
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3 1 .104 1 .105
fburst
5A
(Hz)
8. Loss calculated with various burst frequencies
s loss comparison with various burst duty. The solid line has minimum value under various
is calculated by (7) using with highest other burst duty without optimum design is
oss produced will be larger, as loss shown in d dot line.
LhI
30
80
50
LBurst
LBurst
LBurst
iD
iD
iD
=
=
=
0 5 10 15 20iL
igure 9. Loss comparison with various Dburst
(A)
analysis of operation processes and loss of burst veral operation rules should be applied to ghest efficiency with burst operation: irst SR driving signal should be discarded to nt from energy flowing reversely. duty should be regulated according to load t by (7), and ILh selected should be the load t with the highest efficiency.
Burst frequency should be selected as low as possible by consideration of output ripple requirement, output capacitor selection, etc.
The switch turned on first in this burst period should be the switch last turned off in last burst period in order to reduce first hard switching loss.
III. OUTPUT FILTER DESIGN
Output capacitor plays a very important role in burst control. This capacitor will influence not only the output voltage ripple but also the loss in burst control.
0.0
0.
0.015
)
)
Figure 1
Becausdiscontinuerelated to bcapacitanceis:
where: U∆Fig.10
requiremenwith normavoltage ripponly 250 uFis considerhigher. To can be seleCf are adde
The defrequency senough atteto satisfy reis one turn,
If CLC filter is applied, output capacitor selection can only focus on two aspects: output voltage ripple will not be higher than the maximum voltage stress of SR MOSFETs, and ESR loss of capacitor caused by large charging current in stage 2 can satisfy requirement.
Equation (16) can be used to calculate the ESR loss of each cycle, and the difference between burst control and normal control is that is the mean value of in normal control, but in burst control, is much smaller. As shown in Fig.12, with same rectified current , Io in solid line is output current in normal control which equals the mean value of , and the dashed line is output current under burst control which is much lower. The difference between and Io is the AC current flowing through ESR of output capacitor, which is much larger under burst control than under normal control which will cause large loss.
Io )(tioIo
)(tio
)(tio)(tio
1
C(F
)
dtESRIotioPT
burst ∫ ⋅⋅−= 2))(( (16)
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0.05 0.10
0. Capacitance need
e power trans under burst murst frequency. needed without
C =
is the voltage reshows the capact, and the dashl control. 10mFle requirement w is needed in no
ed, the demanddecrease the dected. Fig.11 shod to filter output
C
Figure 11.
sign rule of thhould be lowernuation at burst quirement. For and saturate at l
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0K
0
50Kwhere: is rectified current in secondary side, and is )(tio Io
00K0.15 ed different ripple requirements
smitted to output capacitor is ode control, there is output voltage To satisfy ripple requirement, the consideration of ESR of capacitors
burstfUIo⋅∆
(15)
quirement. itance needed with different ripple ed line is the capacitance needed capacitance is needed for 100mV ith 10 KHz fburst; correspondingly,
rmal operation. If influence of ESR for this capacitor will be much mand of this capacitor, CLC filter ws the CLC filter structure, Lf and voltage ripple. Lf
Cf
CLC filter structure
ese two components is: the cross then burst frequency, and ensure frequency in order to depress ripple loss and dynamic consideration, Lf oad not using burst mode.
the mean value of output current. ∆
i
Figur
Fig.13 showsolid line repreand dashed line50% load. Thapproximately extreme low ESloss with burst
00
2
4
6
8
Loss
(/10-5
W)
Fig
Based on aby load curren
0 ©2009 IEEE 62
o(t)
I
e 12. Current waveforms of output capacitor
s the loss of each cycle varying with ESR. The sents the loss under burst control at 10% load, represents the loss under normal operation at e loss of each cycle with burst control is twice of normal control with same ESR, so R capacitor should be selected to reduce this
control.
B
ure
IV
nat
0.001 0.002 0.003 0.004
13. ESR loss
. CONTR
lysis abovto ensure
esrESR(Ω)
∆
withU(V)
of capacitor of each cycle
OL STRATEGY
e, burst duty should high efficiency. Bur
o
urst control
Normal control
be regulated st frequency
should be fixed by tradeoff between output capacitance of output capacitor, audio noise and efficiency.
Fig.14 is the proposed control diagram of burst mode control. The current sense module sense load current, and this load signal is sent to microprocessor to generate corresponding burst duty with fixed frequency. To prevent from burst duty switching so frequently, piecewise control is applied. As shown in Fig.15, burst duty is divided into several pieces, and around each switching point, there is a hysteresis loop.
CFP
EA-
+
CFS
RF
R1
RD1
RD2
VO
VCO
Logiccontrol
S1,S4
S2,S3
SR1
SR2
fs
MCUDburstcurrent
senseA/D
Figure 14. Control diagram of burst mode
According to description above, the burst duty is regulated by output current with fixed burst frequency and open loop control; output voltage is regulated by switching frequency as normal control. So this kind control can obtain stable working operation and output regulation. But also because of the fixed burst fixed duty and frequency, the high efficiency of extreme light load, such as lower than 2% load, can not be achieved. But that from 5A to 15A is under optimum design.
5A 10A 15A
Dburst
Io00
100%
Figure 15. Control strategy of burst duty
V. EXPERIMENTAL RESULTS
The proposed burst mode control is implemented on a built prototype. The switching frequency of LLC under normal control is 380 KHz, output is 12V/100A, and the highest efficiency 97.4% is produced at 50A load. The designed parameters of burst control are listed in table.2.
TABLE II Key parameters of burst mode
Burst frequency 10K Output capacitance 8mF ESR of C 2.3mΩ Lf 1uH Cf 2mF
Burst mode control is applied at load under 15A, namely
15% load. Fig.16 shows the experimental waveforms of
primary current ip, output voltage ∆Vo and DS voltage of Q2 at 15A load. Fig.17 shows the efficiency tested with various load condition, and Fig.18 shows the tested loss.
∆Vo
ip
Vds
Figure 16. Waveforms of ∆Vo, Vds, ip at 15A
78%
80%
82%
84%
86%
88%
90%
92%
94%
96%
98%
0 5 10 15 20
Burst control
Efficiency
Normal control
Load (A)
Figure 17. Efficiency comparison with various loads
0
2
4
6
8
10
12
0
Normal control
Loss(W
)
Dburst
Fig
From Fighard switching,half switching power conversiVo increases gtank flows revebegins. Vds of Vin/2, and the than 100 mV. FFig.18, it can b
To achievburst mode coanalysis, Burstinto three procdiscussed carepower loss as
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u
. corrQor
e
en efulo
Burst control
5 10 15 20
Load (A)
re 18. Loss comparison with various loads
16, it can be seen that the first switching is and there is no power transmission in the first ycle. After that, there are several cycles for n, resonant current decreases gradually, and adually. Then, power remained in resonant sely in about one quarter cycle and oscillation
2 oscillates around voltage level lower than utput voltage ripple after LC filter is lower om the comparison data shown in Fig.17 and seen that efficiency can be improved a lot.
VI. CONCLUSION
high light load efficiency of LLC converter, trol is applied in this paper. With detailed mode operation of LLC with SR is divided sses, and loss distribution of each process is lly in order to find the rules of reducing w as possible. Output filter for burst mode
controlled LLC is also studied to meet voltage ripple requirement and reducing ESR loss. As a total solution, corresponding control strategy is also proposed. To verify the analysis and control method, a prototype with 12V/100A was built, and efficiency at light load can be improved significantly, such as efficiency at 10% load can be improved from 92.5% to 94.8%.
Based on the analysis and experimental results, some conclusions can be obtained:
Burst mode control can be applied to improve light load efficiency of LLC converter with SR.
The suitable primary and secondary driving timing and low burst frequency should be selected, to achieve the high efficiency.
Low ESR output capacitor should be selected to reduce ESR loss, and LC filter can be added to meet output ripple requirement.
Suitable control strategy realizes burst duty varied with output current to achieve the high efficiency.
REFERENCE [1] Bo Yang, Fred Lee, Alpha J. Zhang, Guisong Huang, “LLC Resonant Converter for Front End DC/DC Conversion,” IEEE Applied Power Electronics Conference and Exposition (APEC’02), 2002. [2] Ocean Wu, Curtis Wang, John Zeng, Jianping Ying, “A Method of Synchronous Rectification for LLC Converter,” Proceeding of DPEC Seminar, 2007 [3] Jin-ho Choi, Dong-young Huh, Young-seok Kim, “The Improved Burst Mode in the Stand-by Operation of Power Supply,” IEEE Applied Power Electronics Conference and Exposition (APEC’04), 2004. [4] Yu Fang, Dehong Xu, Yanjun Zhang, Fengchuan Gao, Lihong Zhu, Yi Chen, “Standby Mode Control Circuit Design of LLC Resonant Converter,” IEEE Power Electronics Specialists Conference (PESC’07), pp.726-730, 2007.
.
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