Analysis and Design Considerations of an Improved Zero-Voltage and Zero-Current-Switching Full-Bridge DC-DC Converter

International Journal of Advanced Computer Science, Vol. 3, No. 3, Pp. 108-112, Mar., 2013.

Manuscript Received:

15, Sep., 2011

Revised:

7, Oct., 2011

Accepted:

11, Jan., 2013

Published:

15, Feb., 2013

Keywords

soft-switching;

ZVZCS;

full-bridge;

passive

clamping

circuit

Abstract This paper presents an

improved zero-voltage and zero-current

switching full-bridge DC-DC converter.

The proposed passive clamping circuit

consists of an inductor, two capacitor

and four diodes. With this auxiliary

circuit phase-shifted full-bridge

converter can achieve ZVZCS

independent of various line and load

conditions. The features of this

converter are discussed in detail, and

the design considerations are illustrated

in this paper. Simulation analysis and

experimental result on a 7.5KW

prototype using this passive clamping

circuit are presented to verify the study.

1

1. Introduction The phase-shift full-bridge (PSFB) converter is widely

known as a popular topology for DC-DC high power

conversion. In this conventional converter,

zero-voltage-switching (ZVS) technique for two legs called

a lagging-leg and a leading-leg can be realized using circuit

parasitics such as transformer leakage inductor and device

junction capacitor without additional resonant components.

Therefore, the efficiency of PSFB ZVS DC-DC converter is

high, which is deemed most desirable for high-frequency

and high-power applications. However, it has several

drawbacks such as limited ZVS load range for lagging leg

switches, reduction of effective duty cycle and severe

voltage ringing in the secondary rectifier side.

In order to improve the PSFB ZVS converter, a number

of zero-voltage and zero-current-switching (ZVZCS)

full-bridge converters have been proposed for the last

several years. The ZVZCS technique realizes ZVS for

leading leg switches and ZCS for lagging leg switches. It

utilizes auxiliary circuits composed of inductance or

capacitance, which stores energy during power conversion

1, Dai Mei is with School of Electrical and Automation Engineering

Changshu Institute of Technology, Changshu, China (Email:

[email protected]), 2, Shen Ping is with Academy of Frontier Science Nanjing University of

Aeronautics and Astronautics Nanjing, China (Email:

[email protected]).

period and reduces the primary side circulating current

during the freewheeling period.

According to the location in main circuit, there are two

sorts of auxiliary circuits: 1) References [1]-[2] show the

topologies with dc blocking capacitor in primary side,

which is used as a voltage source to compel the current of

leakage inductance to zero. A small saturable inductor is

applied in [1] to block reverse current when the primary

current is reset and sustained to zero. But it is difficult to

design a saturable inductor, and the thermal loss of saturable

inductor is considerable which restricts the power of

converter. Two diodes connected with lagging led switches

in series are introduced to block reverse current instead of

saturable inductor in [2]. However, the conduction loss of

diodes is very large; 2) [3]-[12] introduce topologies with

secondary auxiliary circuits which is reflected to the

primary and applied on the leakage inductance to reset the

primacy circulating. An active clamp circuit with clamping

MOSFET is applied in [3][4], but it is more complex to

control. A transformer auxiliary winding is employed in [5].

A coupled wingding of the output filter inductor is utilized

in [6]. A series of passive clamping circuits comprised with

capacitors and diodes are proposed in [7]-[12].

Compared with other circuits, there are several

advantages such as simple structure, easy to design and

lower loss in passive clamping circuits. However, the spike

of primary current and rectifier diodes are high due to the

resonance of transformer leakage inductance and parasitic

capacitances of rectifier diodes. In order to ensure the

converter operation in safety, the transformer should be

designed to have large leakage inductance or an external

inductor should be connected with the transformer in series.

But the large leakage inductance or the external inductor

result in severe conduction loss and the duty ratio loss of the

secondary side gets much serious.

This paper presents an improved secondary passive

clamping circuit which can overcome the drawbacks

mentioned above. By using the proposed circuit, the output

current which is reflected from the secondary side to the

primary side can be eliminated during the freewheeling

mode. The PSFB converter with the improved secondary

auxiliary circuit ensures zero current switching of lagging

leg switches and zero voltage switching of legging leg

switches. Therefore, it can maximize the power density and

enhance the effective duty ratio. In this paper, the features

of the proposed ZVZCS full-bridge converter are discussed

in section 2. Design considerations are studied in detail in

Analysis and Design Considerations of an Improved

Zero-Voltage and Zero-Current-Switching

Full-Bridge DC-DC Converter Dai Mei

1, , & Shen Ping 2

Mei et al.: Analysis and Design Considerations of an Improved Zero-Voltage and Zero-Current-Switching Full-Bridge DC-DC Converter.

International Journal Publishers Group (IJPG) ©

109

section 3. Simulation analysis and experimental results of a

7.5KW prototype are presented in section 4. Finally,

conclusions are summarized in section 5.

2. Improved ZVZCS FB Converter

with Secondary Passive Clamping

Circuit

A. Proposed Topology

The ZVZCS FB converter with secondary passive

clamping circuit is shown in Fig.1. The auxiliary circuit is

simply consisted by the only passive elements such as

clamping capacitors (CBC1B, CBC2B), fast recoverary diodes

(DBC1B, DBC2B, DBC3B), clamping diode (DBC4B) and inductor

(LBCB).The magnitude of leakage inductance is very small

compared with that of conventional one.

Fig.1 Proposed circuit.

B. Operation Principles

The operation waveforms are shown in Fig 2. During the

freewheeling period, there are two modes according to the

remain voltage of clamping capacitors, which are illustrated

separately in Fig2(a) and Fig2(b). Only key operation

modes are discussed as follow.

1) Mode A: In Fig.2(a), If the volume of clamping capacitor

is not enough, the remain voltage of clamping capacitors

decrease to zero.

[t1, t2]: The clamping capacitors CBC1B, CBC2B and inductor LBCB

are in series Tresonance. CBC1B and CBC2B are charged. The

primary side current is

(Equ. 1)

The voltage of clamping capacitor is

(Equ. 2)

The rectifier voltage is

(Equ. 3)

where

[t2, t3]: The of CBC2B achieves Vo, and clamping diode DBC4B

turns on. The voltage of CBC2B is clamped at Vo, therefore,

CBC1B exits the resonance at tB2B. The series resonance circuit

contains CBC1B and LBCB. The charge current of CBC1B declines to

zero at tB3B.

[t4, t8]: After tB4B, the rectifier voltage Vrec declines,

therefore CBC1B and CBC2B discharge to convert the storage

energy to the load though DBC1B and DBC2B. The clamping

voltage reflected to primary side compels the circulating

current to decline. When the circulating reduces to zero, the

lagging switch QB4B can be turned off with ZCS.

(a)

(b)

Fig.2 Key waveforms. (a) Mode A. (B) Mode B.

[t8, t9]: When the storage energy in clamping capacitor is

exhausted and the next half operation period does work at

tB8B, the four rectifier diodes are forced to turn on to

freewheel.

2) Mode B: In Fig.2(b), if the volume of clamping capacitor

is large enough, the voltage of clamping capacitors will not

be zero at the end of freewheeling mode.

[t1,t2]: The series Tresonance process is similar with that

as mentioned above. The primary side current is

(Equ. 4)

[t8, t9]: At tB8B, the energy stored in CBC1B and CBC2B is not

exhausted, and the four rectifier diodes keep off until QB2B

turns on entirely.

As discussed above, Mode B is obviously superior than

Mode A.

The secondary rectifier diodes turn on only once in

half period, so the switching loss is down.



110

The dv/dt on power switch is smaller, so the

switching noise can be reduced.

When the circuit operates in Mode B, it can realize

the ZCS of lagging leg switches during full load

range.

C. Effective Duty Ratio

TFig.3 shows the simplified operation waveforms. The

secondary effective duty ratio can be calculate by

(Equ. 5)

where

(Equ. 6)

(Equ. 7)

(Equ. 8)

As analyzed above, the secondary effective duty ratio is

rarely lost.

Fig.3 SimTplified operation waveformsT

3. Design Considerations

A. ZVS Conditions for the Leading Leg Switches

1) In order to achieve ZVS when the leading leg

switched turn on, there should be enough energy to draw the

electric charge on the parasitic capacitance of switches. It

must satisfy

(Equ. 9)

2) Furthermore, the charge or discharge time of the

parasitic capacitance must longer than the shut-down time

of switches to achieve zero voltage off. It must satisfy

(Equ. 10)

where toff is the shut-down time of switches, tdead is

the dead time of one bridge.

B. ZCS Conditions for the Lagging Leg Switches

In order to achieve zero current off, the primary

current must be reset to zero during the time from

leading leg switch off to lagging leg off. It must

satisfy

(Equ. 11)

the inductor LBC Bshould satisfy

(Equ. 12)

Before the voltage of clamping reduces to zero, the

primary current must be zero on the impact of

reflected voltage.

By the end of charge process, the charge of clamping

capacitor is

(Equ. 13)

the discharge time of clamping capacitor is

(Equ. 14)

So the clamping capacitor must satisfy

(Equ. 15)

The parameters of secondary passive clamping circuit

must satisfy (12) and (15) to achieve the ZCS of lagging leg

switches.

C. Rectifier Stress and Primary Current Spike

From (1) and (4), it is TilluminateTd that the voltage spike

is connected with the volume of clamping capacitor. If the

capacitor is small, the resonance period of LBCB and CBC1B, CBC2B

is so short that the LBCB would resonate with Tparasitic

capacitance of rectifier diodes. Therefore, the spike would

be very high, and the stresses of rectifiers are high. However,

if the capacitor is large, there would high current spike.

According to (1) and (4), it is a linear relationship

between the peak value of primary current iBp-peakB and the

ratio of CBCB/LBCB between wide range, which is shown in Fig.4.

To choose proper inductor and capacitor, it must be in

view of such as soft-switching conditions, rectifier diode

stress and current spike.

4. Simulation Analysis and

Experimentations

A. Simulation Analysis

The simulation software used in this paper is Saber. Key

parameters are as follow:

Input voltage 225-315Vdc

Output voltage ±180Vdc

Output current 20A

TTurns ratio of transformer 5:3:3

Clamping capacitor 22nF

Inductor LBCB 26uH

Fig.5 shows the drive waveform vBgsB, the voltage

waveform vBdsB and current waveform iBdB of leading leg switch

QB1B and lagging leg switch QB2B under light load. Fig.6 shows

the key waveform under heavy load. Fig.5 and Fig.6

illustrate that the leading leg switches can realize zero

voltage switching and zero current on easily under light and

heavy load and the lagging leg achieve zero current

Mei et al.: Analysis and Design Considerations of an Improved Zero-Voltage and Zero-Current-Switching Full-Bridge DC-DC Converter.


111

switching. The heavier load, the harder to achieve ZCS for

lagging leg switches.

Fig.4 Curve of relationship between iBp-peak Band CBCB/LBCB

(a)

(b)

Fig.5 Simulation waveforms of soft switch under light load. (a) Waveforms

of QB1B. (b) Waveforms of QB2B.

B. Experimentation

The parameters for the converter prototype are the same

as that of simulation. Fig.7 shows the voltage waveform

between the middle of two legs vBabB and primary current

waveform iBpB under light (Io=6A) and heavy load (Io=18A).

Fig.8 shows the rectifier voltage waveform vBrecB and

secondary current waveform iBsB under light and heavy load.

Fig.9 shows the rectifier diode voltage waveform vBdr1B and

current waveform iBdr1B.

These waveforms verify that the proposed improved

ZVZCS FB converter can realize soft-switching.

C. System Efficiency

Fig.10 shows the efficiency curves of the improved

converter in diamond spot and the circuit introduced in [12].

The highest efficiency of converter with secondary passive

clamping circuit can reach 97.3%.

(a)

(b)

Fig.6 Simulation waveforms of soft switch under heavy load. (a)

Waveforms of QB1B. (b) Waveforms of QB2B.

(a) (b)

Fig.7 Waveforms of vBabB and iBpB. (a) Under light load. (b) Under heavy load.

(a) (b)

Fig.8 Waveforms of vBrecB and iBsB. (a) Under light load. (b) Under heavy load.

(a) (b)

Fig.9 Waveforms of vBdr1B and iBdr1B. (a) Under light load. (b) Under heavy

load.



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5. Conclusion An improved ZVZCS FB converter has been proposed

in this paper. Conclusions are summarized as follow.

1) Compared with other ZVZCS FB converter with

clamping circuit, this converter can realized ZVS for

leading leg easily and ZCS for lagging leg under full load

range.

2) There is rarely duty ratio loss in this converter, and

the regulation rang of input voltage is wide.

3) The proposed auxiliary circuit contains only passive,

therefore it is easy to apply and has low conduction loss,

which helps to improve the conversion efficiency and power

density.

Fig.10 Overall efficiency of the proposed converter and compared

converter.

Acknowledgment This project was supported by NSF grant 09KJD470001

from Education Department of Jiangsu Province.

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Analysis and Design Considerations of an Improved Zero-Voltage and Zero-Current-Switching Full-Bridge DC-DC Converter