Analog to Digital Converter

ANALOG TO DIGITAL CONVERTER (ADC)

Data taken from a physical system normally appear in electrical analog form. The need arises for a device that converts analog information into digital form. Analog to digital converters perform the task of converting the naturally occurring analog signals into digital form.

unknown analog voltage

full scale voltageInput/output relation of an ADC may be given by

Or

An ADC receives an analog voltage signal and converts it into a digital signal by

comparing it to a reference voltage, . The digital at the output of the ADC’s represent a positive

decimal fraction,

Or

Considering natural binary code and finite no. of bits (say n), then

Here, the full scale range, of the ADC is partitioned into segments, each of width (where n is the no. of bits) called quantization step (q)

i.e.

Any analog voltage is replaced by a discrete voltage which is an integral multiple of

the quantization step i.e. . The maximum possible quantized value of the

input voltage is .Replacement of an analog voltage by a discrete value can be carried out either by truncation or

by rounding-off.

000001

010

011

100

101

110

111

1

81

4

3

81

2

5

83

4

7

81

x

fs

V

V(Normalized

AnalogInput)

Actual

Ideal

fs

q

V

DigitalOutputCode

3-bit Truncation Type ADC

Here output changes state at the end of each quantization step (except last step).

A/DCONVERTER

VXAnalog Input

+_

+_Vfs

a1a2a3

an-1an

....DigitalOutput


Quantization Error(e) = quantized value – Actual value

Magnitude of can be reduced to if an offset voltage of is added to prior to quantization using truncation.

A large number of Analog to Digital circuits are available. The most commonly used ADCs are1. Successive approximation type2. Integration type (single and dual slope)3. Counter or servo type4. Parallel type

SUCCESSIVE APPROXIMATION TYPE ADC Block Diagram:

n-bit DAC Clockn-bit Successive

Approximation LogicRegister

Vx

EOC StartConversion

f

DigitalOutput

Vrefreference

voltage

Comparator

V0

FF3 FF2 FF1

3-bit D/A Converter

FFC FFD FFEFFA FFB

åS/H

Vx V0

Offset Voltage =12LSB

GA

GB

GC

MSB

LSB

G1G2G3

S C R S C R S C R

C C C C C

Q3 Q2 Q1Rd Rd

QA QB QDQC QE

DB DC DEDDDA

00

0

1

0x

x

V VC

V V

Clock

AnalogInput

3 - bit Successive Approximation A/D Convertor

_+

A 3-bit successive approximation A/D convertor is shown above.

The convertor shown above is designed to convert an analog waveform into binary code (neglecting sign bit).

The convertor consists of:

ADC/NNS Page 2 2010


1. Five D-type flip flops FFA to FFE. These flip flops are connected are connected to form modulo-5 ring counter. This counters outputs are QA to QE, only one of which is at logic 1 at any time. With each successive clock cycle, the logical level 1 is transferred from A to B to C etc.

2. Flip flops – FF1, FF2 and FF3: these are used to register the digital bits, with FF1 corresponds to LSB and FF3 to MSB.

3. Sample and Hold (S/H) amplifier: The sampled value of the analog signal should be held constant during the sequence of operations. Hence sample & hold amplifier is used whose switch is operated by QE.

4. Comparator: Compares the analog input Vx and output of the D/A convertor. Its output is 1

when and when , comparator output is 0.5. 3-bit D/A convertor: Digital to analog convertor, whose output is used to compare with the

analog input.

6. Summer: To add an offset voltage to reduce the quantization error to .

OperationThe conversion of an analog input voltage into digital value uses a high speed DAC. The analog

output of a high-speed DAC is compared against the analog input signal. The digital result of the comparison is used to control the contents of a digital buffer that both drives the DAC and provides the digital output word. The successive-approximation ADC uses fast control logic which requires only n comparisons for an n-bit binary result.

The conversion of an analog input voltage into its corresponding digital value by using a 3-bit successive approximation ADC requires five clock intervals. During the first four clock intervals

analog output of the 3-bit D/A converter is compared with the analog input and depending upon the comparator’s output, the flip flop FF1, FF2 & FF3 are made set or reset. During the fifth clock interval, digital outputs are read from FF1, FF2 & FF3 where FF1 gives the LSB and FF3 gives MSB.

Sampling of the unknown voltage is performed by sample & holds circuit during this fifth clock periods and the sampled input is held by sample & hold circuit for the next four clock intervals.

The conversion cycle begins when the output of FFA, i.e. . FFA to FFE forms a modulo-5

ring counter and thus when , then . FF3 will set to logic 1 and FF1 &

FF2 will be reset to logic 0. This will produce . This is available

as input of the internal D/A converter which produce a analog voltage as its output. If is the full

scale output voltage then, . The comparator compares and comparator’s output.

will be

Thus, at the end of first clock interval, comparators output depends upon the comparison of

.

During the next clock interval, while .

With , gate G3 is enabled. If , then FF3 is reset (logic 0) and if

, then FF3 is left in the set state (logic 1). Thus the assigned logic 1 to the most significant position has been retained or changed to logic 0 will depend

upon the result of comparison of i.e. the output of comparator ,

ADC/NNS Page 3 2010

1st comparisonMSB TEST

XXX

0XX 1XX

Figure 1.


during the beginning of the second clock interval. Thus the MSB of the digital word has been determined to 1 or 0 and the digital word may be ‘1XX’ or ‘0XX’ as shown in figure 1.

As , FF2 will set to logic 1 and during the later half of the clock interval, is

presented to the 3-bit D/A converter which gives corresponding analog voltage . The comparator

compares and the comparators output will be

Thus, at the end of the 2nd clock interval, comparators output depends upon the comparison of

.

During the first half of the 3rd clock interval, depending upon the comparator’s output , FF2 i.e. MSB-1 bit retains the set value digital 1 or reset to digital 0 and the digital word may be ‘01X’ or

‘00X’ when MSB=0 or ‘11X’ or ‘10X’ for MSB=1. During the later half of the clock interval, (= ‘011’ or ‘001’ or ‘111’ or ‘110’) has been presented at the DAC’s input which converts it into analog

voltage . This voltage is compared with the input analog voltage and the comparator’s output will be

Thus, at the end of the 3rd clock interval, comparators output depends upon the comparison of

.

During the fourth clock interval, depending upon the comparator’s output , FF3 i.e. MSB-2 bit retains the set value digital ‘1’ or reset to digital ‘0’ and the digital word may be ‘000’ or ‘001’ when MSB=0 and MSB-1=0 or ‘010’ or ‘011’ for MSB=0 and MSB-1=1 etc.

These sequences of bit testing of successive approximation type ADC is shown in figure 2.

1st comparisonMSB TEST

XXX

0XX 1XX

2nd comparisonMSB-1 TEST

2nd comparisonMSB-1 TEST

3rd comparisonMSB-2 TEST


00X 01X



10X 11X

000 001 010 011 100 101 110 111

figure 2. The bit-testing sequence used in the successive approximation method.

During the fifth clock interval, with and , gates

are enabled and the digital output is available.

ADC/NNS Page 4 2010


Also, during this clock interval, sample and hold circuit is made enabled by to sample

the input analog voltage. When , sampled analog input voltage is held by sample and hold circuit.

Sample and Hold Circuit:

OP1OP2xV yV

s

Both the opamp OP1 and OP2 are unity gain non-inverting voltage amplifier. Switch S

is operated i.e. remains closed when .

Example:

Encode an analog voltage into a 3-bit digital word having a full scale range of

and offset voltage of .

For full scale voltage , quantization step, (3-bit converter). The maximum possible quantized value of the input voltage is

. Therefore, converter’s output ‘000’ corresponds to and ‘111’

corresponds to and . Offset voltage is .1 st clock interval

Here and

Therefore,

And D/A input =

D/A output =

2nd clock interval

Here and

Therefore,

As and

And D/A input =

D/A output =

3rd clock interval

Here and

Therefore,

As and

ADC/NNS Page 5 2010


And D/A input =

D/A output =

4th clock interval

Here and

As and

D/A output =

5th clock interval

Here and

Therefore, are enable and digital output is available.

ADC/NNS Page 6 2010


DUAL SLOPE CONVERTER (ADC)

. . .

QN QN-1 Q1 Q0 J0

K0

J1

K1

JN-1

KN-1KN

JN

Comparator

S2

CR0

0

1 0

0 0C

VV

V

V

0

FF0FF1FFN-1FFN

MSB LSB

-VX

VR

n-bit binary up counter

G1Clock

C C C C

Dual-slope ADC

11 1 1

TC

This technique involves comparison of an unknown voltage with a reference voltage. The

unknown voltage and reference voltage applied in this circuit must be of opposite polarity.

This process utilized the voltage to time conversion technique twice, first by connecting the

unknown voltage to a function of time and then it is compared with that generated by the precision reference voltage.

In integrator the unknown voltage or known precision voltage are applied successively (controlled by digital control circuit). The output of the integrator is the linearly rising

ramp when is applied and linearly decreasing ramp when is applied after is applied.

Comparator compares the output of the integrator with the ground voltage and thus its output goes high as the conversion process started.

Binary up counter counts the no. of clock pulses when the output of the comparator is is high.

Digital control circuit gives two types of commands (i) Reset and (ii) Convert.

Working Principlei) Before conversion begins, the capacitor is discharged and the counter is reset to zero count.ii) The conversion process is initiated by connecting the input switch through the analog input.

Analog input voltage is then integrated by the integrator. If the input to the converter is taken from a sample & hold circuit then it can be assumed to be constant and in addition if it is ensured to be negative then the output of the integrator will be linearly rising ramp.

iii) Immediately after the conversion process starts, the comparator output goes high which in

turn starts up the up counter. When the of flip flop FFN becomes ‘1’, say at time , it

switches the input of the integrator to a fixed reference voltage by a control circuit. The output of the integrator is then given by

ADC/NNS Page 7 2010


Thus the output of the integration is decreasing linearly and at time , becomes zero. This in turn changes the output of the comparator to low state.

If frequency of the clock pulse which is fixed, the time required for the counter to set

the MSB ( ) to logical ‘1’, is given by . Here, is constant which depends upon the

clock frequency . clock pulses corresponds to .

If ‘M’ be the no. of pulses counted by the time period , then

Or

Or

Or

Or

Or

Therefore, the contents of the counter is directly proportional to the input voltage .Conversion accuracy is not dependent upon resistor and capacitor values and hence the clock frequency.

ADC/NNS Page 8 2010

ta tbt0

XV tRC

RV tRC

(2 ) 1.N

RVRC f

2 Na Ct T

Vx

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Analog to Digital Converter