Analog Layout

Emad Semicon Co. (Ali Daneshfar)

Analog CMOS IC Design – Sharif UniversitySayyed Mojtaba Atarodi

ANALOG LAYOUT

ByAli Daneshfar

1383 - Azar



Outline

•Layout Overview and Design Rules

•Devices

•Matching

•Noise considerations

•LatchUp

•Antenna

• ESD

•PADs and Packaging



Layout Overview and Design Rules

N-WELL and P-WELL

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ACTIVE or DIFFUSION

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Bird’s beak



GATE(POLY1)

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PPLUS

Lateral diffusion

wafer layout



NPLUS

Well contact

wafer layout



CONTACT

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•Contacts must be as separate squares not a continuous rectangle.•Use maximum possible contacts.•Do not contact over gate.



METAL1

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VIA

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METAL2

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For Analog design, do not route over gate.



Isolated NMOS in a P-Substrate(useful in RF applications)

Implementing a retrograde well(R-well) or P-type well inthe N-well.



Silicidation

source/drain polysilicon metal spacer silicide

silicide process polycide process

molybdenum process salicide(self aligned polycide)process



Devices

•PMOS•NMOS•BJT•DIODE•RESISTOR•CAPACITOR•INDUCTOR



PMOSDIFFNWELLCONTACTPOLY1

PPLUS

METAL1

POLY2

NPLUS



NMOSDIFFNWELLCONTACTPOLY1

PPLUS

METAL1

POLY2

NPLUS



Split large W transistors into smaller W transistors

•Even splitting is preferred.•Splitting results in :

Smaller area.Optimizing gate resistance.Reducing S/D junction parasitic capacitance.



(a) Drain area = 0.67X

(b) Drain area = 0.50X

drain

drain

Structure (b) is preferred(even splitting).



Reducing gate resistance and Noise

Necessary for very large transistors.



Series transistors



Vertical PNPDIFFNWELLCONTACTPOLY1

PPLUS

METAL1

POLY2

NPLUS



RESISTORS

POLY

Silicide

Nonsilicide

N+ (5 ± 4 Ω/ )

P+ (5 ± 4 Ω/ )

N+ (180 ± 10 Ω/ )

P+ (160 ± 15 Ω/ )

“N+ Poly Nonsilicide” is the most precise resistor.



RESISTORS(continue…)

DIFF

Silicide

Nonsilicide

N+ (5 ± 4 Ω/ )

P+ (5 ± 4 Ω/ )

N+ (61 ± 7.5 Ω/ )

P+ (145 ± 20 Ω/ )

(0.07 Ω/ )NWELL (1100 ± 400 Ω/ ) METAL



RESISTORS(continue…)DIFFNWELL

POLY1

PPLUS

METAL1

POLY2

NPLUS

CONTACTPoly resistor

NWELL resistor

R = Rs × ( L / W )



•Better for precise resistors.•Use large width(≥2 um).•Use large length(Min. 3 )



RESISTORS in RF applications

VDD



CAPACITORS

• Poly – Poly ~ 1fF/um2

• Metal – Metal ~ 1fF/um2

• MOS gate capacitance

C = Carea × Area + Cperimeter × Perimeter



Precise capacitor



poly

MET1

MET2

MET3

C1

C2

C3

Ceq = C1 + C2 + C3

Between all conductor and semiconductor layers there are small capacitors called parasitic capacitors : surface to surface, edge to surface and edge to edge.



INDUCTOR



Matching : MOS

• Equal W

• Same orientation

• Symmetry in X&Y (common centroid configuration)

• Dummy gates for outside transistors



Common Centroid Configuration

15 A

A

B

B

C

C

C

C

A : 30/2 B : 30/2 C:60/2 dummy dummy



DIFFNWELLCONTACTPOLY1

PPLUS

METAL1

POLY2

NPLUS

A A B B A A

B B A A B B



Matching : Resistors

A B A B A B A B



Matching : Capacitors




Analog CMOS IC Design – Sharif UniversitySayyed Mojtaba Atarodi A Sample OPAMP Layout



Where does noise coupling occur?• Capacitive and Inductive coupling between wires.

• Direct ohmic connections(power supply line).

• Substrate coupling.



Cross Talk Noise• Use shields connected to power and ground.



Supply & Ground Bounce (Noise)



Supply & Ground Bounce (Noise)• Use of different power supply lines(star topology).



Substrate Coupling



Substrate Coupling (continue…)• Layout analog and digital circuitry in different sections of the chip.• Protect analog(sensitive) layout by guard rings.



Substrate Coupling (continue…)



Substrate Coupling (continue…)



Design Techniques



Design Techniques


Analog CMOS IC Design – Sharif UniversitySayyed Mojtaba Atarodi Design Techniques



Antenna Effect

(problem)

(solution 1 )

(solution 2 )

- - - - - - - - - - - - - - - - - - - - - - - - - - -



Latch UpVDD

GND

Q1

Q2

rn

rp

Q1Q2

rn rp



Latchup starts if :

• Large parasitic resistances(rn, rp).• Large leakage current.

Latchup prevention rules :

• Place substrate and well contacts between transistors ofdifferent types

• Maximize the number of substrate and well contacts.• Minimize the distance between substrate contacts andtransistors within a well.

• Minimize the spacing between substrate and well contacts.



ESDESD damages:

• gate oxide break down.• S/D junction melting.

Effects of ESD protection diodes:• Parasitic capacitance :

• Causing latchup if bad designed.

degrading the speed.Coupling noise on VDD.



PADs and Packaging

die

package

circuit core

bond wire

lead

PAD

cavity

trace



PAD structure : Overlaying all conductive layers .

For possible bonding :

• PAD dimensions ?

•PAD spacing ?

•PAD placement ?

Parasitic effects :• bond wire and trace self inductance.• trace to trace mutual inductance.• trace to trace capacitance.



Reduction of mutual coupling

Prependicular lines Additional ground lines





A Sample Full Chip Layout

ANALOG

DIGITAL

Analog VDD

DigitalVDD



Design Flow

Design, Simulation Layout DRC LVS

ExtractionIncludingParasitics

SimulationOK?GDSIIFabrication

No

Yes

Documents

Analog Layout