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Aim:-CMOS circuit design using spice for
1)NAND 2)NOR
Circuit Diagram:-
CMOS NAND
Theory:-
The circuit above has two inputs and one output. Whenever at least one of the inputs is low, the corresponding P-type transistor
will be conducting while the N-type transistor will be closed. Consequently, the output voltage will be high. Conversely, if both inputs are high, then both P-type transistors at the top will
be open circuits and both N-type transistors will be conducting. Hence, the output voltage is low. The function of this gate can be summarized by the following table:
V1 V2 Output
Low Low High
Low High High
High Low High
High High Low
If logical 1's are associated with high voltages then the function of this gate is called NAND for negated AND.
Observation & Result
.model nmos nmos Level=1
+ Vto=1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
.model pmos pmos Level=1
+ Vto=-1.0 Kp=3.0E-5 Gamma=0.35
+ Phi=0.65 Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00 Uo=700.0 Af=1.2
+ Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8
+ Pb=0.75 Cj=2.0E-4 Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0 Rs=10.0 Rsh=30.0
When both input are switching at vdd/2=2.5
m1 d1 g1 vdd vdd pmos w=10u l=10u
m2 d1 g1 vdd vdd pmos w=10u l=10u
m3 d1 g1 s2 0 nmos w=41u l=10u
m4 s2 g1 0 0 nmos w=41u l=10u
vgs g1 0 2.5
vdd vdd 0 5
.dc vgs 0 5 .1
.plot v(d1) v(g1)
.end
Nand Gate output when same input given
T spice code when B switching and A off
m1 d1 g1 vdd vdd pmos w=10u l=10u
m2 d2 g2 d1 vdd pmos w=10u l=10u
m3 d2 g1 0 0 nmos w=10u l=10u
m4 d2 g2 0 0 nmos w=10u l=10u
vgs1 g1 0
vgs2 g2 0
vdd vdd 0 5
.dc vgs2 0 5 .1
.plot v(d2) v(g2)
.end
Output vs Iput plot when B switching
T spice code when B switching and A off
m1 d1 g1 vdd vdd pmos w=10u l=10u
m2 d2 g2 d1 vdd pmos w=10u l=10u
m3 d2 g1 0 0 nmos w=10u l=10u
m4 d2 g2 0 0 nmos w=10u l=10u
vgs1 g1 0
vgs2 g2 0
vdd vdd 0 5
.dc vgs1 0 5 .1
.plot v(d2) v(g1)
.end
