Analog Circuit Sizing Using Adaptive Worst-case Parameters Sets

8/3/2019 Analog Circuit Sizing Using Adaptive Worst-case Parameters Sets

1/5

Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets

R. Schwencker1,2

, F. Schenkel1

, M. Pronath1

, H. Graeb1

1Institute for Electronic Design Automation 2Infineon TechnologiesTechnical University of Munich P.O. Box 80 09 49

80290 Munich, Germany 81609 Munich, Germany

Abstract

In this paper, a method for nominal design of analog in-tegrated circuits is presented that includes process varia-tions and operating ranges by worst-case parameter sets.These sets are calculated adaptively during the sizing pro-cess based on sensitivity analyses. The method leads to ro-

bust designs with high parametric yield, while being muchmore efficient than design centering methods.

1 Introduction

In integrated circuit technologies with ever shrinkingfeature sizes and growing performance requirements, theinfluence of process variations on the behavior and yieldof analog circuits cannot be neglected. In order to be ableto design robust circuits, random process fluctuations andalso variations of the operating conditions (e.g. temperatureand supply voltage) must be taken into account as early aspossible in the design cycle. Furthermore a high degree ofautomation is needed for analog circuit design in order tocope with the demand of an ever shorter time-to-market [9].

Powerful tools for nominal design, e.g. [5, 14, 15], weredeveloped and some are commercially available. Nominaldesign usually does not consider process fluctuations andvariations of the operating conditions. Therefore, nominaldesign can only guarantee that the given specifications arefulfilled for the typical process and nominal operating con-ditions. Due to the growing influence of process fluctuationand changes in the operating conditions, design centering isnecessary in addition to nominal design in order to ensure ahigh production yield.

Many approaches to design centering, based on statisti-cal, e.g. [2, 11], and deterministic methods, e.g. [1, 6, 12],were presented. Usually design centering algorithms are

computationally very expensive. Hence the design center-ing process should be started from a good nominal designin order to keep the computational cost small. This can beachieved by introducing worst-case parameter sets for pro-cess and operating conditions into nominal design [4,6].

In the digital domain, process fluctuations are being con-sidered by means of slow and fast worst-case parametersets. These are calculated for a given process and typicalcircuit performance like delay, but independent from a spe-cific circuit. For digital cell libraries, these parameter sets

give a good estimation of the influence of random fluctua-tions on the relevant digital circuit performances, delay andpower. However it is well known that such digital cornerscases are not sufficient for analog design [6, 13].

Using digital corner cases for analog circuit design bearsa high risk of leaving yield problems undetected until pro-duction. For analog design, worst-case parameter sets there-

fore need to be calculated for each circuit topology and eachcircuit performance individually.

Using such performance-specific worst-case parametersets for circuit sizing faces the problem that they depend onthe nominal design parameter set and hence vary during thesizing process.

In this paper, a new efficient sizing algorithm is pre-sented that simultaneously considers process fluctuationand operating conditions. It features:

calculation of individual worst-case parameter sets foreach performance,

adaptive calculation of worst-case parameter sets in each

iteration step of the sizing process based on simple andfast sensitivity analyses.

efficient trust region optimization algorithm using sizingrules [10].

The paper is structured as follows: The next section for-mulates worst-case parameter sets. The new sizing algo-rithm is discussed in Section 3, and the results are presentedin Section 4.

2 Worst-case parameter sets and yield

For a given topology, a circuit can be described by itsparameters and performances. Three types of parameters

can be distinguished: Design parameters d Rnd (e.g. nominal transistor

widths and lengths) can be adjusted by the circuit de-signer.

Process fluctuations for instance at oxide thickness,threshold voltage, or transistor width variation, are mod-eled by statistical parameters s Rns and their dis-tribution function. As shown in [7], all practically im-portant parameter distributions can be transformed into a


2/5

Gaussian distribution with zero mean value and covari-ance matrix C: s N(0,C). The probability densityfunction pdf(s) is then given by:

pdf(s) = (2)ns2 (detC)

12 exp

2(s)

2

(1)

2(s) = sTC1s . (2)

In integrated circuit design, most statistical parame-ters appear as transistor model parameters (e.g. tox, orvth0) and cannot be adjusted by the circuit designer if afrozen, fully qualified production process is assumed.

Operating parameters Rn (e.g. supply voltage,temperature) describe the circuits operating conditions.The circuit must satisfy its performance specification fora given range T of the operating parameters, defined bytheir lower bounds L and upper bounds U:

T = { |L U} . (3)

The circuits performance values f (e.g. gain, delay) canbe calculated for a given parameter set using an analogcircuit simulator: (d, s,) f. Depending on the per-formance, a circuit simulation means solving a system ofnonlinear equations (DC- and AC-analysis) or integrating asystem of nonlinear algebro-differential equations (transientanalysis).

For the circuit performances, lower and/or upper speci-fication bounds fb,i, i = 1, . . . , nb are defined that have tobe met for a correctly operating circuit:

i=1,...,nb

fi(d, s,) fb,i f(d, s,) fb . (4)

Here, upper bounds are included by fi fb,i wherefb,i < 0. Considering variations in the operating condi-tions, the specification bounds have to be met for the whole

operating range:

T

f(d, s,) fb . (5)

The parametric yield Y is the percentage of circuits thatsatisfy (5):

Y(d) =

{s|

T

f(d,s,)fb}

pdf(s) ds . (6)

During sizing, process and operating variations can beconsidered by means ofworst-case parameter sets that rep-resent a certain standard deviation max of process varia-tions [3]: For each performance specification bound fb,i, a

worst-case parameter deviation is determined according to

(swc,i,wc,i) = argmins,

fi(d, s,)

subject to 2(s) 2max and T .(7)

For instance, max = 3 corresponds to a 3 design. Satis-fying (5) at the worst-case parameter sets guarantees a min-imum parametric yield

Y Yl1 (ns) = Fns(2max) , (8)

Performance nominal 3 slow/fast 3 worst-case

Delay [ns] 1.35 1.91 (+42%) 1.92 (+42%)

Delay [ns] 1.43 1.90 (+33%) 1.90 (+33%)

Hysteresis [mV] 612 563 (8.0%) 441 (28%)

Table 1: Performance values for a Schmitt trigger compared atslow/fast parameter sets and at worst-case parameter sets

according to Eq. (7).

where Fns is the probability function of a 2-distribution

with ns degrees of freedom. Iff is monotonous with regardto s, then another loose lower bound can be given by

Y Yl2 (nf) = 1 (max) nb , (9)

where is the probability function of the normal distribu-tion. For example, ifmax = 3 then

Yl2 (nf) 100% 0.135% nb . (10)

Since Yl1 depends on the number ns of statistical parame-

ters, and Yl2 depends on the number nb of bounds, eitherlower bound can be the greater one.

For digital circuits, it turned out that the swc,i of delayand power consumption are practically independent fromsizing and topology. Therefore it is common practice to cal-culate a set of slow/fast worst-case parameter sets once fora manufacturing process and then use it for all digital cells.The worst-case operating points wc,i are also practicallyindependent from sizing and topology, but T is part of thecircuit specification, not of the process. Therefore, the wc,iof delay and power are to be determined once for T.

For analog circuits, slow/fast sets are insufficient. Firstthey do not incorporate non-digital performances. Tab. 1compares the performance values of the Schmitt triggerbuffer of Fig. 2 at the slow/fast corners of a 0.18m-processwith the performance values at the actual worst-case pa-rameter sets calculated directly for this topology and sizingaccording to Eq. (7). As can be seen, the slow/fast perfor-mance values of the delays conform to the actual worst-caseperformance values. In contrast to that, the 3 worst-casevalue of the third performance hysteresis is in fact muchworse than indicated by a simulation at the slow or fast pa-rameter set. Using these parameter sets to verify a specifi-cation regarding hysteresis will therefore pretend an unreal-istically high robustness.

Secondly, worst-case parameter sets depend on the ana-log circuits topology. Assume for instance a process con-

sisting of only two random variables, sn that influencessolely NMOS transistors and sp for the PMOS transis-tors. Further given are a current mirror completely builtof NMOS transistors and another one completely built ofPMOS transistors. It is then obvious, that the first circuitis only affected by sn, whereas the second one is affectedonly by sp. Hence the 3 worst-case parameter sets will beorthogonal.

Third, worst-case parameter sets depend on sizing, seeSec. 4.


3/5

3 Sizing and adaption of worst-case parame-ter sets

Worst-case sizing is the task of finding a design param-eter vector d that guarantees a minimum yield according toEqs. (8, 9). Since the worst-case parameter sets depend onthe sizing in a non-linear manner, we propose an iterative

numerical optimization. Since the exact calculation of theworst-case parameter sets (swc,i,wc,i) is computationallyexpensive, we introduce an approach to relaxed calculationof worst-case parameter sets based on linear approxima-tions. An update of the approximated worst-case parametersets is performed at each iteration step.

Beginning with = 0, the following actions are per-formed in each iteration step () of the algorithm, The steps1 through 6 are performed for each specification fb,i (seeFig. 1).

1. the corresponding performance fi is linearized with re-spect to the operating parameters at its respective

worst-case parameter set (s(1)wc,i ,

(1)wc,i ) and design pa-

rameter set d(1) of the previous step :

g()i = fi

d(1),s

(1)wc,i

,(1)wc,i

. (11)

2. Then, the components j of the worst-case operating pa-

rameter set ()wc,i are calculated:

()wc,i

j

=

(L)j if

g()i

j

0

(U)j else. (12)

3. Performance fi is linearized with respect to the statisti-cal parameters s at the worst-case parameter set from theprevious iteration step (s

(1)wc,i ) and at the worst-case op-

erating parameter set of the current iteration step (()wc,i):

h()i = sfi

d(1),s

(1)wc,i

,()wc,i

. (13)

4. Thereafter, s()wc,i is defined by

s()wc,i =

2maxh()i

T C h

()i

C h()i . (14)

5. Performance fi is then linearized with respect to designparameters d at the worst-case parameter set of the cur-

rent iteration step (s()wc,i,

()wc,i)

1:

k()i = dfid(1),s()wc,i,()wc,i

(15)

1Please note that each iteration step is divided into 3 update steps ac-

cording to the 3 parameter types. First, the worst-case operating parameter

set is updated: (1)wc

()wc . Thereafter this updated worst-case op-

erating parameter set ()wc is already used for the sensitivity calculation

that leads to an updated worst-case parameter set s(1)wc

s()wc . The

updated worst-case parameter set is then used for the sensitivity calcula-

tion leading to an updated design parameter set d(1) d(). Using

the latest available parameter sets for each update step contributes to the

efficiency of the algorithm.

:= 0, d := d(0)

:= + 1

For each specification fb,i

Determine g()i ,

()wc,i

Determine h()i , s()wc,i

Determine k()i

Minimize ()(d) subject to d F()

d()

Until i fi(d(), s

()wc,i,

()wc,i) > fb,i

Figure 1: Structure of optimization algorithm.

f()wc,i(d) = fi(d

(1), s()wc,i,

()wc,i)

+k()i

T (d d()) . (16)

6. The parameter distance function ()i (d) [15] is then de-

fined as

()i (d) =

f()wc,i(d) fb,ik()i . (17)

The objective function ()(d) is calculated based on

the parameter distances ()i for the specifications fb,i,

i = 1, . . . , nb:

()(d) =

nbi=1

exp

a ()i (d)

, a > 0 . (18)

The positive constant factor a is a weighting factor. High

values ofa make the optimizer focus stronger on violatedspecifications.

7. The objective function ()(d) is then minimized bymeans of a trust region method presented in [15]:

d() = argmind

()(d) subject to d F()

, (19)

where F is the feasibility region that guarantees the basicfunctionality and robustness of a circuit [10]. The con-straint d F ensures that functional constraints like alltransistors must be in saturation are fulfilled during thesizing.

The feasibility region F is the subset of the design space

where all functional constraints are fulfilled. ConsideringF is crucial for automated sizing of circuits:

The result of the sizing has to be feasible in order to rep-resent a technically correct circuit. Only parameter vec-tors d F are technically valid solutions.

Most performances are only weakly nonlinear in the fea-sibility region. Therefore, the reduction of the designspace to the feasibility region significantly improves theprecision of the used linearized performance models.


4/5


5/5

Documents

Analog Circuit Sizing Using Adaptive Worst-case Parameters Sets