ANALOGBEHAVIORAL MODELING

WITH THE VERILOG-A LANGUAGE

ANALOGBEHAVIORAL MODELING

WITH THE VERILOG-A LANGUAGE

by

Dan FitzPatrickApteq Design Systems, Inc.

and

Ira MillerMotorola

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47918-4Print ISBN: 0-7923-8044-4

©2003 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, Moscow

Print ©1998 Kluwer Academic Publishers

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.comand Kluwer's eBookstore at: http://ebooks.kluweronline.com

Dordrecht

Disk only available in print edition

Contents

1 Introduction

1.2

1.3

MotivationProduct Design MethodologiesThe Role of Standards1.3.1 Verilog-A as an Extension of Spice

1.4 The Role of Verilog-A1.4.1 Looking Ahead to Verilog-AMS

2 Analog System Description and Simulation

2.1

2.2

Introduction

Representation of Systems2.2.12.2.22.2.3

Anatomy of a ModuleStructural DescriptionsBehavioral Descriptions

2.3 Mixed-Level DescriptionsRefining the Module

2.4 Types of Analog SystemsConservative SystemsBranches

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910

11

1112131416

1922

252526

2.3.1

2.4.12.4.2

1.1

Analog Behavioral Modeling With the Verilog-A Language

2.4.3 Conservation Laws In System Descriptions2.4.4 Signal-Flow Systems

2.5 Signals in Analog Systems2.5.1

2.5.2

2.5.3

Access Functions

Implicit BranchesSummary of Signal Access

2.6 Probes, Sources, and Signal Assignment2.6.1

2.6.22.6.3

ProbesSourcesIllustrated Examples

2.7 Analog System Simulation

2.7.1 Convergence

3 Behavioral Descriptions3.13.2

3.3

IntroductionBehavioral Descriptions3.2.1 Analog Model Properties

Statements for Behavioral Descriptions3.3.13.3.23.3.33.3.43.3.5

Analog StatementContribution StatementsProcedural or Variable AssignmentsConditional Statements and ExpressionsMulti-way Branching

3.4 Analog Operators3.4.1

3.4.23.4.3

Time Derivative OperatorTime Integral OperatorDelay Operator

3.4.43.4.53.4.6

3.4.73.4.8

Transition Operator.Slew OperatorLaplace Transform OperatorsZ-Transform Operators

Considerations on the Usage of Analog Operators

3.5 Analog Events3.5.13.5.2

Cross Event Analog OperatorTimer Event Analog Operator

3.6 Additional Constructs3.6.1 Access to Simulation Environment

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41

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454547484951

535355575862646874

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8080

Contents

3.6.23.6.33.6.4

Indirect Contribution StatementsCase StatementsIterative Statements

3.7 Developing Behavioral Models3.7.13.7.23.7.3

Development MethodologySystem and Use ConsiderationsStyle

4 Declarations and Structural Descriptions

4.1

4.2

4.3

Introduction

Module Overview4.2.14.2.24.2.3

Introduction to Interface DeclarationsIntroduction to Local DeclarationsIntroduction to Structural Instantiations

Module Interface Declarations4.3.1 Port Signal Types and Directions4.3.2 Parameter Declarations

4.4 Local Declarations4.5 Module Instantiations

4.5.14.5.24.5.3

Positional and Named Association ExampleAssignment of ParametersConnection of Ports

5 Applications5.15.2

IntroductionBehavioral Modeling of a Common Emitter Amplifier5.2.15.2.25.2.35.2.4

Functional ModelModeling Higher-Order EffectsStructural Model of BehaviorBehavioral Model

5.3 A Basic Operational Amplifier5.3.15.3.2

Model DevelopmentSettling Time Measurement

5.4 Voltage Regulator5.4.1 Test Bench and Results

818383

84848586

87

87

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939396

9899

100102104

107107108112114116118

122122127

129133

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Analog Behavioral Modeling With the Verilog-A Language

5.5 QPSK Modulator/Demodulator5.5.15.5.2

ModulatorDemodulator

5.6 Fractional N-Loop Frequency Synthesizer5.6.15.6.25.6.35.6.4

Digital VCOPulse RemoverPhase-Error AdjustmentTest Bench and Results

5.7 Antenna Position Control System5.7.1

5.7.2

5.7.35.7.45.7.5

Potentiometer

DC Motor

GearboxAntennaTest Bench and Results

Appendix A Lexical Conventions and CompilerDirectives

A.1 Verilog-A Language TokensA.1.1 White SpaceA.1.2 CommentsA.1.3 OperatorsA.1.4 NumbersA.1.5 ConversionA.1.6 Identifiers, Keywords and System NamesA.1.7 Escaped IdentifiersA.1.8 KeywordsA.1.9 Verilog-A KeywordsA.1.10Math Function KeywordsA.1.11Analog Operator KeywordsA.1.12System Tasks and Functions

A.2 Compiler DirectivesA.2.1 ‘define and ‘undefA.2.2 ‘ifdef, ‘else, ‘endif A.2.3 ‘includeA.2.4 ‘resetall

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143145147149150

153154

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159

159159160160161162162162162163163164165

165165166167168

Contents

Appendix B System Tasks and Functions

B.1B.2

B.3

B.4B.5

B.6

B.7

Introduction

Strobe TaskB.2.1 Examples

File Output

Simulation TimeProbabilistic Distribution

Random

Simulation Environment

Appendix C Laplace and Discrete Filters

C.1

C.2

Introduction

Laplace FiltersC.2.1 laplace_zpC.2.2 laplace_zdC.2.3 laplace_npC.2.4 laplace_nd

C.3 Discrete FiltersC.3.1 zi_zpC.3.2 zi_zdC.3.3 zi_npC.3.4 zi_nd

C.4 Verilog-A MATLAB Filter Specification Scripts

Appendix D Verilog-A Explorer IDE

D.1

D.2

IntroductionInstallation and SetupD.2.1 Overview of the DistributionD.2.2 Executable and Include Path SetupD.2.3 Overview of the IDE Organization

D.3 Using the Explorer IDED.3.1 Opening and Running an Existing DesignD.3.2 Creating a New Designs

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173

175

175175175176177177

178178179179180

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185

185

187187188189

191192198

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Analog Behavioral Modeling With the Verilog-A Language

Appendix E Spice Quick Reference

E.1E.2

E.3

Introduction

Circuit Netlist Description

ComponentsE.3.1E.3.2

ElementsSemiconductor Devices and Models

E.4 Analysis TypesE.4.1E.4.2

E.4.3E.4.4

Operating Point AnalysisDC Transfer Curve AnalysisTransient AnalysisAC Small-signal Analysis

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x

Foreword

Verilog-A is a new hardware design language (HDL) for analog circuit and systemsdesign. Since the mid-eighties, Verilog HDL has been used extensively in the designand verification of digital systems. However, there have been no analogous high-levellanguages available for analog and mixed-signal circuits and systems.

xi

Verilog-A provides a new dimension of design and simulation capability for analogelectronic systems. Previously, analog simulation has been based upon the SPICE cir-cuit simulator or some derivative of it. Digital simulation is primarily performed witha hardware description language such as Verilog, which is popular since it is easy tolearn and use. Making Verilog more worthwhile is the fact that several tools exist inthe industry that complement and extend Verilog’s capabilities.

Although SPICE is very effective in the simulation of analog and digital integratedcircuits, it is limited to the use of primitives such as transistors, resistors, and capaci-tors. Hence, SPICE lacks the ease that Verilog HDL possesses of describing and sim-ulating higher-levels of abstraction of the design. In the past, this gap has been filledwith such programs as Mathcad and Matlab that allow description of electronic func-tions based upon numeric computation and data analysis. Although these programsare useful for studying electronic and non-electronic systems at higher levels ofabstraction, they do not tie into other tools such as SPICE and Verilog. The Verilog-Alanguage enables description directly using mathematical relationships, thus easilyallowing system descriptions other than electrical. Additionally, Verilog-A interfacesto numeric computation programs, such as SPICE and Verilog.

Verilog-A HDL

Analog Behavioral Modeling with the Verilog-A Language provides a good introduc-tion and starting place for students and practicing engineers with interest in under-standing this new level of simulation technology. This book contains numerousexamples that enhance the text material and provide a helpful learning tool for thereader. The text and the simulation program included can be used for individual studyor in a classroom environment.

High level languages such as Verilog-A are evolving to enable simulation of complexmixed analog and digital for both electrical and non-electrical systems. This book willget you started now.

Dr. Thomas A. DeMassaProfessor of EngineeringArizona State University

xii

Preface

The Verilog HDL was introduced in 1984 as a means for specifying digital systems atmany levels of abstraction, from behavioral to the structural. Accepted for standard-ization in 1995 by the IEEE, Verilog HDL continues to grow in acceptance and playan increasing role in the specification and design of digital systems. For analog sys-tems analysis and design, Spice, developed by the University of California at Berke-ley in 1971, became the defacto standard used to simulate the performance ofelectronic circuits. While Spice provides a high-level of accuracy as a simulation tool,designs can only be represented on a structural level. As such, the ability to handlelarge analog and mixed-signal systems, as well as explore design ideas at the behav-ioral level, is fairly limited.

The Verilog-A language is derived from Verilog HDL for the description of high-levelanalog behaviors. Used in conjunction with a Spice simulator, The Verilog-A lan-guage expands the simulation capabilities for analog and mixed-signal systems to top-down and bottom-up methodologies. The proposed Verilog-A language is describedin the Language Reference Manual (LRM) draft prepared by a standards workinggroup of the Open Verilog International (OVI) organization. The LRM Version 1.0,August 1, 1996 is not yet fully defined and is subject to change. As such, the materialin this book focuses on the core aspects of the Verilog-A language as presented in theLRM and the work within the OVI Verilog-A Technical Subcommittee.

The goal of this book is to provide the designer a brief introduction into the methodol-ogies and uses of analog behavioral modeling with the Verilog-A language. In doingso, an overview of Verilog-A language constructs as well as applications using the

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Verilog-A HDL

language are presented. In addition, the book is accompanied by the Verilog-AExplorer IDE (Integrated Development Environment), a limited capability Verilog-Aenhanced Spice simulator for further learning and experimentation with the Verilog-Alanguage. This book assumes a basic level of understanding of the usage of Spice-based analog simulation and the Verilog HDL language, although any programminglanguage background and a little determination should suffice.

Certain typographical conventions are used to emphasize different kinds of text usedin this book. Both Spice and Verilog-A code fragments are in Courier font, keywordsin the respective languages are also in bold. This is an example of Cou-rier font with a keyword in bold.

The organization of the book is such that it hopefully presents a connection betweenthe motivation behind the development of the Verilog-A language and the capabilitiesit provides. Chapter 1 provides an introduction on motivations and benefits for stan-dard analog HDLs such as the Verilog-A language. Chapter 2 is designed to providean outline of the Verilog-A language in terms of structural and behavioral definitions.In Chapter 3 we investigate more thoroughly the behavioral aspects of the Verilog-Alanguage, while Chapter 4 does the same for the structural constructs within the lan-guage. Chapter 5 brings these concepts together in a variety of applications presentedin their entirety. The appendices provide detailed reference for those that wish toprobe further into the usage and capabilities of the language.

Examples, when they are presented, are done so in terms of the Verilog-A ExplorerIDE input format. The Verilog-A Explorer uses standard Spice design netlist descrip-tion and simulation control constructs. A summary of Spice input file descriptions isprovided for reference in Appendix E.

The Verilog-A Explorer IDE, is a Windows ‘95 / NT application designed to providesufficient capabilities to the designer and/or model developer with enough capabilityto learn analog behavioral modelling with the Verilog-A language. The Verilog-AExplorer IDE incorporates context sensitive editors, waveform display, and simulatorbased on Spice3 from the University of California Berkeley along with Apteq DesignSystems’s Spice Analog HDL Extension Kernel and Verilog-A compiler integrated.In addition, the package is accompanied with examples to provide starting points forexperimenting with the Verilog-A language.

The Verilog-A Explorer IDE is provided for educational purposes only. As such,there is no direct software warrantee or support provided either by Apteq Design Sys-tems or Kluwer Academic Publishers and its dealers. It is our hope that the benefits ofusing the tools provided will greatly outweigh any inconvenience you may have in

xiv

Preface

using them. Detailed information regarding installation, setup, and usage of the Ver-ilog-A Explorer IDE is presented in Appendix D. For bug reports, availability ofupdates, additional modeling information and/or modeling examples in the Verilog-Alanguage, contact:

Apteq Design Systems, Inc.652 Bair Island Rd. Suite 300Redwood City, CA 94063-2704support @ apteq.com

Or visit the company website at:

http://www.apteq.com

Analog and mixed-signal extensions are currently being developed under Open Ver-ilog International via the Verilog-AMS Technical Subcommittee. You can find infor-mation regarding the Verilog-A standard, such as the Language Reference Manualvia:

Open Verilog International15466 Los Gatos Boulevard, Suite 109071Los Gatos, CA 95032(408) 358-9510http://www.ovi.org.

You can participate in the Verilog-AMS Technical Subcommittee by joining the mailreflector. To join in the discussion, send a request to:

Verilog-ms@galaxy.nsc.com

Giving credit to all who contributed to the development of the Verilog-A language isdifficult and we apologize to anyone we have neglected to mention. We gratefullyacknowledge support from the members of board of directors and the of the OVI andespecially the support of Vasilious Gerouisis of Motorola, Chairman of TechnicalCoordinating Committees. The Verilog-AMS Committee is chaired by Ira Miller ofMotorola, and co-chairman is James Spoto of Enablix Design. The participatingmembers of the Verilog-AMS committee included (in alphabetical order): RamanaAisola of Motorola, Graham Bell of Viewlogic, William Bell of Veribest, Kevin Cam-eron of Antrim Design Systems, Raphael Dorado of Apteq Design Systems, John

xv

Verilog-A HDL

Downey of Viewlogic, Dan FitzPatrick of Apteq Design Systems, Vassilious Gerousisof Motorola, Ian Getreu of Analogy, Kim Hailey of Santolina, William Hobson ofCadence Design Systems, Ken Kundert of Cadence Design Systems, Oskar Leutholdof GEC Plessy, S. Peter Liebmann of Antrim Design Systems, Ira Miller of Motorola,Tom Reeder of Viewlogic, Steffen Rochel of Simplex, James Spoto of EnablixDesign, Richard Trihy of Cadence Design Systems, Yatin Trivedi of Seva Technolo-gies, and Alex Zamfirescu of Veribest.

Special thanks in review of this book go to Dr. Richard Shi from the University ofIowa, Clem Meas of QuickStart, Peter Hunt from Portability, Dr. Robert Fox from theUniversity of Florida, and Dr. Thomas A. DeMassa from Arizona State University fortheir special efforts. The following people also provided reviews of the initial draftsof this book and participated in the beta evaluation of Verilog-A Explorer (in the ordertheir reviews were received): Ed Cheng, Xian Meng of Littlefuse, George Corrigan ofHewlett Packard, and Norman Dancer of Gigatronics, Dale Witt of Createch, andJohn Wynen of Research In Motion.

xvi