Analog Applications Journal 2Q05 - TI.com · op amp input (assuming the noise contributor is located downstream on the signal path). The next step is now to refer the totalinput-referred

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Analog and Mixed-Signal Products

Analog ApplicationsJournal

Second Quarter, 2005

© Copyright 2005 Texas Instruments


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Analog Applications JournalAnalog and Mixed-Signal Products www.ti.com/aaj 2Q 2005

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Analog Applications Journal 2Q 2005 www.ti.com/aaj Analog and Mixed-Signal Products

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Power ManagementUnderstanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

The effects of noise and ripple in a regulator are often erroneously lumped together. This articleevaluates various LDO regulator components as potential noise sources and describes methods used toanalyze and implement noise reduction.

Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . 8There are many ways to improve PSRR in LDO applications. This article analyzes ripple rejection byseparating a typical PSRR response into three basic frequency regions and describing how key LDOcomponents can be adjusted to improve ripple rejection in each region.

Interface (Data Transmission)Maximizing signal integrity with M-LVDS backplanes. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

This article identifies issues associated with high-speed multipoint backplane design and presents testresults from using M-LVDS across a custom-designed backplane. Also included are developmentguidelines for aiding the design of a high-performance system.

Amplifiers: Op AmpsAuto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . 19

System-level auto-calibration is often achieved by adding costly hardware and software. In many cases,the auto-zero amplifier (AZA) can offer the low-offset and low-drift performance typically associatedwith chopper-stabilized amplifiers. This article provides an in-depth look at how AZAs function and howtheir enhancements make them as easy to use as standard op amps in dc and wideband applications.

Index of Articles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Contents

To view past issues of theAnalog Applications Journal, visit the Web site

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4


Analog Applications Journal is a collection of analog application articlesdesigned to give readers a basic understanding of TI products and to providesimple but practical examples for typical applications. Written not only fordesign engineers but also for engineering managers, technicians, systemdesigners and marketing and sales personnel, the book emphasizes generalapplication concepts over lengthy mathematical analyses.

These applications are not intended as “how-to” instructions for specificcircuits but as examples of how devices could be used to solve specific designrequirements. Readers will find tutorial information as well as practicalengineering solutions on components from the following categories:

• Power Management

• Interface (Data Transmission)

• Amplifiers: Op Amps

Where applicable, readers will also find software routines and programstructures. Finally, Analog Applications Journal includes helpful hints andrules of thumb to guide readers in preparing for their design.

Introduction

Introduction


5

Analog Applications Journal

Texas Instruments Incorporated Power Management

2Q 2005 www.ti.com/aaj Analog and Mixed-Signal Products

Understanding noise in linear regulators

Types of noise in analog circuits may include thermal,flicker, and shot noise, among others. In an LDO application,noise is sometimes confused with power supply ripplerejection (PSRR). Many times the two are lumped togetherand loosely called “noise” just because both cause unwant-ed signals on the output. This is incorrect. PSRR refers tothe amount of ripple on the output coming from ripple onthe input. Noise, on the other hand, is purely a physicalphenomenon that occurs with transistors and resistors(capacitors are noise-free) on a very fundamental level.

Noise in an LDO is indicated in two fashions. One isspectral noise density, a curve that shows noise (µV/√

—–Hz)

versus frequency. The other is integrated output noise,also commonly called output noise voltage (in µVrms); it issimply the spectral noise density integrated over a certainfrequency range and can therefore be thought of as thetotal noise in a specified frequency range. Since the outputnoise voltage is represented by a single number, it is veryuseful for comparison purposes.

Typically, noise in an LDO is specified as output-referrednoise (noise occurs throughout the LDO but eventuallymust be referred to the output). The typical approach tofinding the output-referred noise of an LDO is first to referall noise contributors to the input of the LDO differentialamplifier. To refer means to divide each individual noisecontributor by the gain that exists between it and the op amp input (assuming the noise contributor is locateddownstream on the signal path). The next step is now to

refer the total input-referred noise to the output by multi-plying by the closed-loop gain of the feedback network.The closed-loop gain of an LDO is simply

where VBG is the internal bandgap reference. In many casesVBG is about 1.2 V (although some LDOs have sub-bandgapreferences and thus a VBG of less than 1.2 V). An LDO withan output voltage of 3.0 V will have almost twice the outputnoise voltage of a 1.5-V LDO; therefore it’s very importantwhen comparing noise on various LDOs always to comparethose with identical output voltages. When this isn’t possi-ble, an approximation can be made by simply taking intoaccount the ratio of the two output voltages. For example,when comparing the noise voltage of a 3.0-V LDO to thatof a 1.5-V LDO, either multiply the noise voltage of the1.5-V LDO by 2 or divide the noise voltage of the 3.0-VLDO by 2.

The simplified block diagram in Figure 1 shows the primary noise sources in an LDO-the bandgap, the resistordivider, and the input stage of the op amp. The effects ofsome of these noise sources can be reduced if the latterare properly understood.

The dominant source of noise in an LDO is usually thebandgap. In most cases this is solved by adding a largelow-pass filter (LPF) to the bandgap output so that noneof the noise makes it into the gain stage. (This same filter

AV

VCL DCOUT

BG( ) ,=

By John C. Teel (Email: [email protected])Analog IC Designer, Member Group Technical Staff

Input

CIN

CNR

NR

RLoad

R1

R2

Output

COUT

PassFET

ErrorAmplifier

+

–

Reference

Figure 1. Simplified LDO block diagram


Texas Instruments IncorporatedPower Management

6


is also used to improve PSRR.) Typically thisLPF is formed with a large internal resistorand an external capacitor. In most cases thecutoff frequency of this filter is set some-where between 1 and 500 Hz, thereforefiltering out nearly all of the noise comingfrom the bandgap. In many cases the downside of using too large an RC filter is that thetime to charge the filtered bandgap increasesdrastically, which significantly slows downthe output startup. This can be solved byusing a low-noise, high-PSRR LDO with afast-charge circuit such as the TPS793/4/5/6xxor one from the TPS799xx family. Even witha fairly large noise reduction capacitor of0.01 µF, these LDOs are still able to start upin only 50 to 100 µs.

Another source of noise in an LDO is theresistor divider network. This noise is knownas thermal noise and is equal to 4kTR(sometimes called 4kTR noise), where k isBoltzmann’s constant, T is temperature inKelvin, and R is the resistance. The resistor divider is tiedto the input of the LDO differential amplifier, so this noiseis amplified by the closed-loop gain of the LDO. When cal-culating this noise source, you can simply use the parallelcombination of R1 and R2 since the op amp input seesthem as being virtually in parallel. Therefore, to reducethis noise source, the most important thing to rememberis that smaller feedback resistors create less thermalnoise. Of course, the disadvantage of using smaller resis-tors is that they burn more current through the feedbackdivider; but if noise is of prime importance, then thissacrifice must be made.

The other source of noise is the internal LDO differen-tial amplifier, which is usually designed in such a way thatthe input stage has a large amount of gain—more specifi-cally, transconductance (gm). This is done so that anynoise coming from devices in the signal path located afterthe input stage have their noise attenuated by the gain ofthe input stage when they are referred back to the input.There is nothing outside of the internal circuitry that canbe done to reduce this noise source.

Many people are surprised that the huge power passFET, which usually takes up at least half of the total diearea in an LDO, isn’t a primary noise contributor. The reasonfor this is the lack of gain. All of the primary noise sources(bandgap, resistor divider, and op amp input stage) areconnected to the input of the differential amplifier andthus are not attenuated by any internal gain. Rememberthat the procedure for finding output noise is first to refereach noise contributor to the op amp input; so to find thenoise from the pass FET you would first divide its noisecontribution by the open-loop gain that exists between itand the op amp input. This gain is typically quite large;therefore, the noise contribution from the pass FET isusually negligible.

Also somewhat surprising is that neither the outputcapacitor, the load current, nor even the input voltage hasany direct effect on the output noise, at least to a firstorder. However, load current and output capacitance dohave an indirect second-order effect. As mentioned previ-ously, output noise is calculated by multiplying the input-referred noise by the closed-loop gain. The closed-loopgain isn’t constant at VOUT/VBG over the entire frequencyrange, and of course it eventually rolls off at high frequen-cies. A fundamental rule of feedback analysis is that lowphase margin will cause peaking in the closed-loop gainnear the unity-gain frequency. Since the closed-loop gainamplifies the noise, this peaking increases the noise in thatfrequency range even more, thus increasing the total out-put noise. This effect can often be seen in spectral noisedensity plots like the one in Figure 2.

High load currents and low output capacitance contrib-ute to output noise because they both make the LDO lessstable, which reduces the phase margin. This phase marginreduction increases the closed-loop gain peaking, which inturn increases the output noise. Another significant effectis that many times a higher equivalent series resistance(ESR) capacitor will actually reduce noise. This is becausea larger ESR creates a lower-frequency zero, which manytimes may improve the LDO stability. Finally, note that thepeaking effect explains why, as previously mentioned, theoutput noise voltage of a 3.0-V regulator usually isn’t quitetwice as much as that of a 1.5-V regulator. A 3.0-V regulatortends to be a bit more stable than a 1.5-V regulator due toits lower feedback factor. This improved stability increasesthe phase margin, reducing the closed-loop peaking andthus the output noise voltage.

One final trick sometimes used to reduce noise is to adda capacitor across the top resistor in the resistor feedback

0.001

0.01

0.1

1

10

10 100 1 k 10 k 100 k

Frequency (Hz)

e( µ

V/

Hz)

N

—–

√

Figure 2. Spectral noise density example



7


divider. This works because at high frequencies the capac-itor begins to reduce the closed-loop gain and thus thenoise, so that the system begins to look like a unity-gainfeedback configuration providing no noise gain. The trade-off is that this could potentially slow down start-up timesignificantly, since the capacitor would have to be chargedby the current in the resistor divider. The TPS799xximplements this technique via an internal capacitor andalso includes a fast-charge circuit.

In summary, there are many ways to reduce noise in anLDO application. The most important is to start with alow-noise, high-PSRR LDO optimized for low-noise applica-tions such as one from the TPS793/4/5/6xx family or thelow-Iq TPS799xx family. The second way is to use as largea noise-reduction capacitor as is feasible for startup while

keeping in mind that there’s a point where increasing thiscapacitance will offer no further improvement. Finally, usesmall resistances for the resistor divider network (if theLDO is an adjustable version) and a small capacitor acrossthe top resistor, if possible. Some less obvious improve-ments are to optimize the output capacitor along with theload current for the highest phase margin to reduce closed-loop peaking. Many times, stability can be optimized byusing the stability plots provided in some LDO data sheets.

Related Web sitespower.ti.com

www.ti.com/sc/device/partnumber

Replace partnumber with TPS79301, TPS79401,TPS79501, TPS79601, or TPS79901


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http://www.ti.com/sc/device/TPS79301





8


Understanding power supply ripple rejection in linear regulators

Power supply ripple rejection ratio (PSRR) is a measure ofhow well a circuit rejects ripple coming from the inputpower supply at various frequencies and is very critical inmany RF and wireless applications. In the case of an LDO,it is a measure of the output ripple compared to the inputripple over a wide frequency range (10 Hz to 10 MHz iscommon) and is expressed in decibels (dB). The basicequation for PSRR is

More specifically, PSRR for an LDO can be written as

where AV is the open-loop gain of the regulator feedbackloop, and AVO is the gain from VIN to VOUT with the regula-tor feedback loop open. From this equation it can be seen

PSRRA

AV

VO= 20 log ,

PSRRRipple

RippleInput

Output= 20 log .

that to increase the PSRR it is beneficial to increase theopen-loop gain and decrease the gain from VIN to VOUT.Typically, AVO is significantly less than 0 dB, with –10 to–15 dB being typical; this is entirely driven by internal andexternal parasitics from input to output and at the gate ofthe pass FET. Figure 1 shows a simplified regulator blockdiagram with a PMOS pass device.

Another parameter that is closely related to PSRR is linetransient response. PSRR is specified at specific frequencies,whereas a line transient essentially contains all frequenciesdue to the Fourier components of a step function. However,the primary difference is that PSRR is based on small signals, whereas line transients are large signals and thustheoretically much more complicated in nature. Sinceimproving PSRR typically improves line transient responseand vice versa, all of the effects on PSRR discussed in thisarticle will usually have a similar effect on the line tran-sient response.


By John C. Teel (Email: [email protected])Analog IC Designer, Member Group Technical Staff

Input

CIN

CNR

NR

RLoad

R1

R2

Output

COUT

PassFET

ErrorAmplifier

+

–

Reference

Figure 1. Simplified LDO block diagram



9


A curve showing PSRR over a wide frequency range isshown in Figure 2.

As mentioned previously, the open-loop gain of the LDOfeedback circuit is the dominant factor in PSRR (at leastin a limited frequency range); therefore, LDOs requiringgood PSRR typically have high gain with a high unity-gainfrequency (large gain-bandwidth product). However, thismakes the loop more difficult to stabilize, which limits howmuch the gain-bandwidth product can be increased toimprove PSRR. It is important to have a high unity-gainfrequency so that the amplifier does not lose open-loopgain at relatively low frequencies, causing PSRR to roll off also.

The curve in Figure 2 shows that PSRR for an LDO canbe broken down into three basic frequency regions.Region 1 is from dc to the roll-off frequency of thebandgap filter and is dominated by both open-loop gainand bandgap PSRR. Region 2 extends from the bandgapfilter roll-off frequency up to the unity-gain frequencywhere PSRR is dominated mainly by the open-loop gain ofthe regulator. Region 3 is above the unity-gain frequency,where the feedback loop has very little effect, so the out-put capacitor dominates along with any parasitics from VINto VOUT. The gate driver’s ability to drive the pass-FET gateat high frequencies also has an effect in Region 3. A largeroutput capacitor with less equivalent series resistance(ESR) will typically improve PSRR in this region, but itcan also actually decrease the PSRR at some frequencies.This is because increasing the output capacitor lowers theunity-gain frequency, causing the open-loop gain to roll off

earlier and thus lowering PSRR. Nevertheless, the minimumPSRR that occurs at the unity-gain frequency will typicallybe improved.

Anything affecting the gain of the feedback loop alsoaffects PSRR in Region 2. One example is load current. Asload current increases, the open-loop output impedance ofthe LDO decreases (since a MOSFET’s output impedanceis inversely proportional to the drain current), thus lower-ing the gain. Increasing the load current also pushes theoutput pole to higher frequencies, which increases thefeedback loop bandwidth.The net effect of increasing theload is therefore reduced PSRR at lower frequencies(because of the reduced gain) along with increased PSRRat higher frequencies.

The differential dc voltage between input and output isanother example of how a change in the feedback loopgain also affects PSRR. As VIN–VOUT is lowered to less thanabout 1 V, the internal pass FET (which provides gain in aPMOS design) starts to be pushed out of the active (satura-tion) region of operation and into the triode/linear region,which causes the feedback loop to lose gain. The dividingline between the active region and the triode region is proportional to the square root of the drain (load) current.So as the load current is increased, the voltage across thedevice (VIN–VOUT) necessary to keep it in the active regionincreases as a function of the square root of the load cur-rent. For example, having VIN–VOUT at only 0.5 V may haveno negative effect on PSRR at light load currents becausethe pass FET device doesn’t need much headroom to stayin the active region and to preserve gain. At heavier loads,

30

35

40

45

50

55

60

Rip

ple

Reje

cti

on

(dB

) 65

70

75

80

10 100 1 k 10 k 100 k 1M

Frequency (Hz)

Region 1 Region 2 Region 3

Figure 2. PSRR curve



10


however, 0.5 V may no longer be sufficient and the passFET device may enter the triode region, causing the circuitto lose gain, thus reducing PSRR. When PSRR is comparedamong various LDOs, it’s important always to compareLDOs with identical VIN–VOUT and ILoad conditions. It’s alsoimportant to compare LDOs with identical output voltages,since PSRR is usually better at lower output voltages.

One of the dominant internal sources of PSRR in anLDO is the bandgap reference. Any ripple that makes itsway onto the reference will be amplified and sent to theoutput, so it’s important to have a bandgap reference withhigh PSRR. Typically, the solution is simply to filter thebandgap with a low-pass filter (LPF). This LPF is almostalways accomplished with a large internal resistor and anexternal capacitor. The effect of the LPF can be seen inRegion 1 of Figure 2, where the PSRR is somewhatreduced because the LPF passes bandgap ripple in thisfrequency range.

As has been shown, there are many ways to improve thePSRR in an LDO application. The most important is tostart with a low-noise, high-PSRR LDO designed for high-PSRR applications such as one from the TPS793/4/5/6xxfamily or the low-Iq TPS799xx family. The next mostimportant way is to choose a low-ESR ceramic outputcapacitor and to determine the capacitance value based onthe frequencies at which PSRR is most important. Finally,board layout must be carefully done to reduce thefeedthrough from input to output via board parasitics.

Related Web sitespower.ti.com


Replace partnumber with TPS79301, TPS79401,TPS79501, TPS79601, or TPS79901


http://power.ti.com






11


Texas Instruments Incorporated Interface (Data Transmission)


Maximizing signal integrity with M-LVDS backplanes

As the demand for higher clock and data transfer ratesacross backplane systems continues to grow, fundamentalelements of high-speed printed circuit board design becomeessential. This article identifies issues associated with high-speed multipoint backplane design and provides recom-mendations that include the use of multipoint low-voltagedifferential signaling (M-LVDS) (TIA/EIA-899) technology.M-LVDS provides multipoint communication with up to 32M-LVDS circuits connected to the same media. Test resultsdemonstrating the use of M-LVDS across a custom-designedbackplane will be presented along with development guide-lines for aiding the design of a high-performance system.

Backplane signaling technologiesThe good news is that there are many choices available fortransferring information within a backplane environment,but this can also make it difficult to decide which technol-ogy should be used in a particular application. The key toselecting the right signaling technology for a backplane ishaving a good understanding of the system requirementssuch as signaling rate, power, topology, EMI, transmissiondistance, and loading conditions.

Some of the single-ended signaling technologies avail-able include transistor-transistor logic (TTL), low-voltageTTL (LVTTL), backplane transceiver logic (BTL), gunningtransceiver logic (GTL), and GTL plus (GTLP) (see Table 1).Single-ended transmission occurs when information is sentover a single line referenced to ground, helping to keepthe costs lower for cabling or connectors. However, single-ended signal transmission is also more susceptible to noise,crosstalk, and ground offsets, all of which can result inreceiving false data.

TTL and LVTTL standard logic devices abound, provid-ing not only many choices for signal transmission acrossthe backplane but also the cost advantage of single-ended

transmission. However, TTL standard logic devices havelarge voltage swings that typically translate into EMI.Maintaining these large voltage swings becomes a problemin heavily loaded systems, and TTL is susceptible to signalintegrity issues associated with single-ended data trans-mission (noise, crosstalk, and ground offsets).

BTL also uses single-ended transmission but lowers thevoltage swing to 1.1 V, which can lead to higher transmis-sion rates and reduced EMI radiation relative to TTL. Thisreduced voltage swing is achieved by an open-collectoroutput with the bus terminated through a resistor to 2.1 V.When the driver is activated, the bus is pulled down to thesaturation point of the driver plus the voltage drop acrossa series diode, resulting in a 1-V low. The value of the ter-mination resistor should match the characteristic impedanceof the signal path.

GTL uses an open drain but, unlike BTL, does not use aseries diode. This results in an active-low condition of only0.4 V. The bus termination voltage is reduced to 1.2 V, providing a total voltage swing of 0.8 V. This lower voltageswing can further reduce EMI and provide for higher trans-mission rates relative to BTL. However, the sink current isreduced to 40 mA, which is acceptable for onboard chip-to-chip applications but limits the capabilities for driving aheavily loaded backplane. GTL is primarily recommendedfor point-to-point technologies. GTLP is much better suitedfor multipoint (backplane) environments than GTL.

GTLP is similar to GTL, with slight variations in outputvoltage and termination levels (see Table 1) that wereintroduced to improve the noise margin relative to ground.More significantly, GTLP offers two drive options (50 mAor 100 mA) that can accommodate a more heavily loadedbackplane. GTLP also features output edge control andinternal precharge circuitry enabling live insertion, furtherimproving performance within the backplane environment.

By Michael McCormick, DLP™ TV System Design Engineer (Email: [email protected]),and David Graham, Engineering Supervisor, Interface Products New Product Development (Email: [email protected])

PARAMETER TTL (LVTTL) BTL GTL GTLPVIN, high (V) 2.0 1.62 0.85 1.05

VIN, low (V) 0.8 1.47 0.75 0.95

Vt, VREF (V) 1.4 1.55 0.8 1.0

VOUT, high (V) 2.4 2.1 1.2 1.5

VOUT, low (V) 0.4 1 0.4 0.55

Standard driver load (Ω) — 11 11 11

Drive sink current (mA) — 100 40 50 or 100

Standard JESD8-1 IEEE 1194.1 JESD8-3 —

Table 1. Single-ended signaling technologies


Texas Instruments IncorporatedInterface (Data Transmission)

12


When information is transmitted within a system, it ispossible for the ground reference on the transmission endto be offset relative to the ground reference on the receiv-ing end. For single-ended transmission, the signal is refer-enced to ground; so this ground offset could result inreceiving the wrong information. Also, noise within thebackplane environment can couple onto the signal path,which again can lead to receiving corrupt information.

Differential signaling provides several benefits over single-ended transmission. For instance, the issue of ground offsetwithin the application is diminished since the signals arereferenced to each other rather than to ground. Further,noise within a backplane environment can be alleviated ifcareful consideration is given to the board layout. If thesignal path of the differential pair is routed closely together,noise coupled onto one signal will likely couple onto theother signal of the differential pair. Since these signal pairsare referenced to each other, the noise is effectively can-celed out. It is important to note that the magnitude of theresulting offset voltage cannot exceed the input signalrange of the receiver. If it does, the information will becorrupt, even with differential signaling.

Of course, with differential signaling, two signal paths perchannel will increase the number of cables or connectorpins in the system. This must be weighed against the ben-efits associated with differential signaling and the needs ofthe applications. Some of the differential signaling technol-

ogies available include RS-485, positive emitter-coupledlogic (PECL), low-voltage PECL (LVPECL), low-voltagedifferential signaling (LVDS), BusLVDS, and multipointLVDS (M-LVDS) (see Table 2).

RS-485 employs the advantages associated with differ-ential signaling and is ideally suited for transmitting dataover long distances (up to 1200 m) or noisy environments.Multiple drivers and receivers can share the same trans-mission pair (see Figure 1), which is accomplished byproperly terminating each end of the signal path. RS-485is widely accepted in industrial applications, providing aneconomic and robust solution.

PECL and LVPECL provide reduced voltage swings andfaster transition times than RS-485, making them capableof much higher speeds. PECL transmission may require aseparate supply terminating the load resistor to VCC – 2 V.

LVDS, with reduced voltage swings and faster transitiontimes, is also capable of much higher speeds than RS-485.LVDS has an added benefit of using less power than PECLand does not require a separate supply for terminating theload resistor at the end of the transmission line. However,LVDS is not intended to support multipoint configurations.

BusLVDS has characteristics similar to those of LVDS,except that it is intended to support multipoint configura-tions. Since the multipoint configuration requires termina-tion at both ends of the transmission path, the equivalentresistance is half that of a point-to-point configuration.

PARAMETER RS-485 PECL (LVPECL) LVDS BusLVDS M-LVDSVIN, high VDIFF > 200 mV VDIFF > 100 mV VDIFF > 100 mV VDIFF > 100 mV VDIFF > 50 mV*

VIN, low VDIFF < –200 mV VDIFF < –100 mV VDIFF < –100 mV VDIFF < –100 mV VDIFF < –50 mV*

VIN range (V) –7 to 12 Varies 0 to 2.4 0 to 2.4 –1.4 to 3.8

VOUT, high** 1.5 V < VDIFF 800 mV 350 mV 300 mV 550 mV

VOUT, low** –1.5 V > VDIFF –800 mV –350 mV –300 mV –550 mV

Common-mode output –1 V < VOS < 3 V 3.6 V (1.95 V) 1.125 V < VOS < 1.375 V 1.1 V < VOS < 1.5 V 0.3 V < VOS < 2.1 V

Standard driver load (Ω) 60 50 100 27 50

Drive current (mA) > 25 16 3.5 11 11

Standard TIA/EIA-485-A — TIA/EIA-644-A — TIA/EIA-899

Table 2. Differential signaling technologies

* Type 1 receiver threshold is –50 mV < VID < 50 mV. Type 2 receiver threshold is 50 mV < VID < 150 mV.** These are nominal differential output voltage levels relative to the common-mode voltage and may vary with the vendor. Each line is terminated with 50 Ω or a Thevenin equivalent.

Figure 1. Multipoint configuration



13


BusLVDS addresses this issue by increasing the drive cur-rent so that, even though the equivalent resistance is cutin half, the desired differential signal level is still maintained.

M-LVDS is a technology designed specifically for heavilyloaded backplanes to transfer clock or data signals. The PCIIndustrial Computer Manufacturers Group (PICMG®) 3.0AdvancedTCATM specification identifies M-LVDS for clocksignaling sources across the backplane. M-LVDS providesthe following features and benefits (refer to TIA/EIA-899):

• Lower voltage swings relative to RS-485, which cantranslate into reduced EMI

• Controlled transition times (>1 ns) that help to hidestubs and also reduce EMI

• Receivers that can typically withstand up to ±2 V ofground offset and have common-mode noise immunity

• Support for multipoint configuration

• No need for a separate supply voltage for termination

The standards and corresponding signaling technologiesare designed to accommodate certain speeds, transmissionlengths, and loading conditions. However, actual perform-ance is highly dependent on how well the overall system isdesigned. Board layout, effective impedance, proper termi-nation, and stub effects can all degrade signal integrity.Careful system-level design is necessary to optimize performance of the chosen signaling technology. Theseconsiderations will be discussed next.

M-LVDS backplane design considerationsAccording to TIA/EIA-899, M-LVDS is intended for use inpoint-to-point applications, multidrop clock or data distri-bution applications, and multipoint data bus applicationswith multiple drivers sharing the same bus. The receiverinput thresholds that are tighter than standard LVDS andthe controlled edge rates are added qualities of M-LVDSthat can contribute to the success of a high-performancesystem design.

A backplane test system was constructed with 8-, 19-,and 30-slot bus lengths to demonstrate the capabilities ofM-LVDS in several backplane loading scenarios. The guide-lines presented here describe high-performance systemdesign practices for success with using M-LVDS in a back-plane environment.

The backplane design was a collaborative effort betweenTexas Instruments (TI) and North East Systems Associates(NESA). The system is based on the CompactPCI® 6Ustandard with an 0.8″ slot pitch, standard 6U cards, and a21-slot backplane (2 slots are reserved for power and 19are used for test cards) that fits into a standard chassis fora 19″ rack. NESA built several multipoint backplane modelsfor the purpose of simulating 8-, 19-, and 30-slot buses.Different edge rates, card and connector stub lengths,backplane differential impedance, termination resistance,and number of slots loaded for each bus length were alsovariables included in the simulations. IBIS and H-SPICEmodels of TI M-LVDS devices were provided to NESA andincorporated into the modeling and simulation stage of thebackplane system to ensure the accuracy of the final system.

The physical system was constructed based on the sim-ulation results NESA provided. Measurements of active M-LVDS devices operating on the multidrop buses wereperformed for verification of those simulation results. NESAalso simulated and measured the passive backplane tracesto ensure that the impedance and other signal integrityparameters specified in the backplane design rules weremet. The result of this effort was a controlled impedancedesign consisting of 10 FR-4 layers, including 4 controlledimpedance layers, 2 power layers, and continuous groundlayers. Each slot on the backplane uses differentially fed,standard 2-mm HM connectors. This optimized M-LVDSbackplane system operates at a data rate of >200 Mbpsand a clock rate of >100 MHz across the 8-, 19-, and 30-slot designed bus systems.

The differential M-LVDS bus paths on the backplanewere designed to meet a 130-Ω differential impedance, asthis was the recommended backplane impedance suggestedby the simulation results. A 100-Ω differential impedanceis normally used in standard differential bus and backplanedesign, but the higher impedance helps to alleviate the effectof low effective path impedance created from the close slotpitch and large card load. In simulation, the raw backplaneimpedance and connector stub lengths were varied to aidin optimizing the former. As connector stub lengths increase,so does the overall capacitance of the loaded backplane bus,lowering the system differential impedance. Keeping con-nector stub lengths to a minimum will maximize the loadedimpedance of the system bus. Results of the time domainreflectometry (TDR) and time domain transmission (TDT)simulations performed by NESA are shown in Table 3 andTable 4, respectively. The PICMG 3.0 AdvancedTCA basespecification also recommends using a 130-Ω differentialtrace impedance to help increase the effective impedanceof the clock bus in a heavily loaded backplane.

APPROXIMATERAW MINIMUM MAXIMUM AVERAGE

BACKPLANE IMPEDANCE IMPEDANCE IMPEDANCEIMPEDANCE LOADED LOADED LOADED

(Ω) (Ω) (Ω) (Ω)100 45.1 50.2 46130 52.7 58.8 54150 57.3 63.9 58

Table 3. Simulated TDR results from fully loaded 30-slot backplane*

*1″ stubs; TDR rise time = 1 ns.

RAWBACKPLANE RISE TIME RISE TIME PROPAGATION PER UNITIMPEDANCE INPUT OUTPUT DELAY DELAY

(Ω) (ns) (ns) (ns) (ps/in)100 1.07 3.07 9.63 388130 1.07 2.98 10.6 427150 1.07 3.01 11.2 452

Table 4. Simulated TDT results from fully loaded 30-slot backplane



14


With a raw impedance of 130 Ω, the effective differentialimpedance of the fully loaded 30-slot backplane is raisedto 54 Ω from the 46 Ω provided by a standard 100-Ω rawimpedance. This reduces the load on the device drivingthe bus and increases the differential voltage of the bus.The drawback of the 130-Ω differential impedance is thatit increases the delay from 388 ps/in to 427 ps/in. Basedon the results in Table 3, using a 150-Ω differential imped-ance would further increase the effective impedance ofthe backplane. However, a 150-Ω differential impedance isnot easily manufactured, which increases the difficulty ofproviding a reliable and repeatable printed circuit board.

A trade-off between slot pitch and daughtercard stublength had to be accounted for during the backplanedesign. As pitch between slots is decreased, the “per unit”distributed loading on the backplane increases and theeffective backplane impedance is reduced. The plug-incard stubs can significantly lower the effective impedancedue to their capacitive effect on the backplane traces. Asthe card stub lengths increase, their capacitance increasesand the effective impedance of the backplane is reduced,signal rise times are slowed, and propagation delaythrough the backplane is increased. If slot pitch isincreased, the card stubs can be longer for a particulareffective backplane impedance and vice versa. Table 5 andTable 6 show simulation results of TDR and TDT, respec-tively, on a 130-Ω raw impedance differential trace with0.8″ slot pitch and different daughtercard stub lengths.Based on the correlated simulation and empirical results, a 1″ or shorter stub length is recommended to prevent theeffective backplane impedance from falling below 54 Ω.

Except for delay differences, the 8-, 19-, and 30-slotbackplane buses look very similar in passive testing. Thisis because they all share the same parameters, including0.8″ slot spacing, identical connectors, and identical cardstub lengths. The impedance and transmission profiles aresimilar to the 30-slot case presented.

Passive and active simulations along with empirical measurements were completed for the various backplanecases with 8-, 19-, and 30-slot buses. As mentioned earlier,the distributed load is similar for all the backplane buses,

but actual driver and receiver waveforms can look quitedifferent due to the distance to the terminations and theslot driving the bus. The resistor value used to terminateeither end of the multipoint bus was chosen as a good com-promise between the heavily and lightly loaded backplaneconfigurations. Through analysis of the passive simulationsand empirical results, 80 Ω was chosen to terminate thebus at either end; and all active simulation and empiricalresults were gathered with the 80-Ω terminations. Ringing,overshoot, and undershoot can be improved by using ter-mination resistors closer to the effective bus impedancefor the loading condition being tested.

APPROXIMATE MINIMUM MAXIMUM AVERAGE

STUB IMPEDANCE IMPEDANCE IMPEDANCELENGTH LOADED LOADED LOADED

(in) (Ω) (Ω) (Ω)0.5 57.5 62 581.0 52.8 58.8 541.5 45.9 56.6 502.0 40.3 55 482.5 35.9 53.6 453.0 32.3 52.3 43

Table 5. Simulated TDR results from fully loaded 30-slot backplane*

STUB RISE TIME RISE TIME PROPAGATION PER UNITLENGTH INPUT OUTPUT DELAY DELAY

(in) (ns) (ns) (ns) (ps/in)0.5 1.07 2.60 9.68 3901.0 1.07 2.98 10.6 4271.5 1.07 3.40 11.5 4642.0 1.07 3.84 12.3 4962.5 1.07 4.28 13.1 5283.0 1.07 4.78 13.8 556

Table 6. Simulated TDT results from fully loaded 30-slot backplane

*Raw impedance = 130 Ω; TDR rise time = 1 ns.



15


Figure 2 shows simulated 200-Mbps eye patterns at thedriver output pins of slot 1 and the receiver inputs of slots10 and 19 when slot 1 is driving a fully loaded 19-slotbackplane bus. The differential voltage drops at slot 10

because it is in the middle of the bus, far away from thetermination resistors, but it is still at acceptable levels.Slot 19 shows an improvement in differential voltagebecause the termination resistor is nearby.

Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

Am

plitu

de (V

)

Figure 2. Simulated 200-Mbps eye patterns when slot 1 drives 19-load bus

(b) At slot 10 receiver input

(c) At slot 19 receiver input

(a) At slot 1 driver output

Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

Am

plitu

de (V

)

–0.2

–0.4

–0.6

–0.8

Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

Am

plitu

de (V

)

–0.2

–0.4

–0.6

–0.8



16


Figure 3 shows simulated 200-Mbps eye patterns at thedriver output pins of slot 10 and the receiver inputs of slots15 and 1 when slot 10 is driving a fully loaded 19-slot back-plane bus. The effects of driving into the middle of a heavilyloaded bus are evident in the jitter displayed in Figure 3a.

However, by the time the signals reach slots 15 and 1, theinitial amount of jitter at the driver output pins is maskedby the increased rise and fall times. This effect is due tothe capacitance encountered at each connector along thebackplane by the signals from the driver at slot 10.

Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

Am

plitu

de (V

)

–0.2

–0.4

–0.6

–0.8

Figure 3. Simulated 200-Mbps eye patterns when slot 10 drives 19-load bus




Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

Am

plitu

de (V

)

–0.2

–0.4

–0.6

–0.8

Time (ns)0 51 63 82 74 9 10

0.8

0.6

0.4

0.2

0

Am

plitu

de (V

)

–0.2

–0.4

–0.6

–0.8



17


Figure 4. Measured 200-Mbps eye patternswhen slot 1 drives 19-load bus




Figure 5. Measured 200-Mbps eye patternswhen slot 10 drives 19-load bus



Figures 4 and 5 depict the measured results of the simu-lated waveforms in Figures 2 and 3. Comparing the simula-tion data to the measured data reveals that the modelingand simulation efforts in predicting the actual signalbehavior on the bus are fairly accurate. For instance, theactual 200-Mbps eye pattern at the slot 1 driver output inFigure 4a has a lower amount of overshoot and more jitterthan the simulation of the same case in Figure 2a. Becausethe voltage overshoot in the actual system is more damp-ened than that in the simulations, the signals in the actual



18


system fall sooner than those in the simulated system. Thiscauses the simulated results to predict a lower amount ofjitter than that measured in the actual results. The simu-lated results, however, do accurately predict the minimumdifferential voltage in the measured eye pattern. Similarcomparisons of overshoot, jitter, and differential voltagecan be made between all of the simulated and actual results.

In conclusion, it is important to consider all aspects ofbackplane system design. As pitch between slots isdecreased, the “per unit” distributed loading on the back-plane increases and the effective backplane impedance isreduced. This can be mitigated by using a 130-Ω differen-tial trace impedance, which helps increase the effectiveimpedance in a heavily loaded backplane. Stub lengthsshould be kept short to minimize associated capacitance. Thedifferential signal path should be carefully considered to helppreserve data transmission within a noisy environment.

Each of the signaling technologies mentioned will satisfycertain needs. M-LVDS incorporates a controlled edgerate with LVDS-compatible signal levels. With the designguidelines previously discussed, implementing M-LVDS ina point-to-point, multidrop, or multipoint system can besuccessfully achieved. The 30-slot system demonstratesthe robustness of M-LVDS drivers and the low capaci-tance of M-LVDS receivers supporting large bus systemsup to and beyond 200-Mbps data rates (100-MHz clock

rates). The PICMG 3.0 AdvancedTCA base specificationcalls for the use of M-LVDS for synchronization clocksacross the backplane.

ReferencesFor more information related to this article, you can down-load an Acrobat Reader file at www-s.ti.com/sc/techlit/litnumber and replace “litnumber” with the TI Lit. # forthe materials listed below.

Document Title TI Lit. #

1. Georg Becke, Christian Borgert, Steve Corrigan, Frank Dehmelt, Matthias Feulner, Carmen Gonzalez, Michael Groenebaum, Firoj Kabir, Arek Kacprzak, Clark Kinnaird, and Johann Zipperer, “Comparing Bus Solutions,”Application Report . . . . . . . . . . . . . . . . . . . . . . . .slla067

2. TIA/EIA-644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” (ANSI/TIA/EIA-644-A 2001). —

3. TIA/EIA-899, “Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M-LVDS) Interface Circuits for Multipoint Data Interchange” (ANSI/TIA/EIA-899-2002). —

Related Web siteinterface.ti.com


http://www-s.ti.com/sc/techlit/slla067

http://interface.ti.com

19


Texas Instruments Incorporated Amplifiers: Op Amps


Auto-zero amplifiers ease the design ofhigh-precision circuits

A wide variety of electronic applications deal with the conditioning of small input signals. These systems requiresignal paths with very low offset voltage and low offsetvoltage drift over time and temperature. With standard linear components, the only way to achieve this is to usesystem-level auto-calibration. However, adding auto-calibration requires more complicated hardware and soft-ware and can slow down time to market for new products.

The alternative is to use components with low offset andlow drift. The amplifiers with by far the lowest offset anddrift available are the auto-zero amplifiers (AZAs). Theseamplifiers achieve high dc precision through a continuouslyrunning calibration mechanism that is implemented on-chip.With a typical input offset of 1 µV, a temperature-relateddrift of 20 nV/ºC, and a long-term drift of 20 nV/month,these amplifiers satisfy even the highest requirements ofdc accuracy.

Today’s AZAs differ neither in form nor in the applicationfrom standard operational amplifiers. There is, however,some hesitation when it comes to using AZAs, as mostengineers associate them with the older chopper ampli-fiers and chopper-stabilized amplifier designs. This stigma

has been perpetuated either by engineers who workedwith the older chopper amplifiers and remember the diffi-culties they had with them, or younger engineers wholearned about chopper amplifiers in school but probablydid not understand them very well.

The original chopper amplifier heralded the beginning ofthe new era of self-calibrating amplifiers more than 50 yearsago. This amplifier provided extreme low values for offsetand drift, but its design was complicated and expensive. Inaddition, ac performance was limited to a few hertz of inputbandwidth accompanied by a high level of output noise.Over the years, unfortunately, the term “chopper amplifier”became a synonym for any amplifier with internal calibra-tion capability. Therefore, AZAs, often wrongly designatedas chopper or chopper-stabilized amplifiers, are associatedwith the stigma of the older chopper technique.

This article shows that the auto-zero calibration tech-nique is very different from the chopper technique and isone that, when implemented through modern processtechnology, allows the economical manufacturing of wide-band, high-precision amplifiers with low output noise. Thefollowing discussion presents the functional principles of

the chopper amplifier, thechopper-stabilized amplifier,and the AZA. It then com-pares the efficiencies oflow-frequency filteringwhen applied to AZAs and standard operationalamplifiers. Finally, threeapplication examplesdemonstrate the use of anAZA as a signal amplifierand as a calibrating ampli-fier in dc—and widebandac—applications.

The chopper amplifierFigure 1 shows a simpli-fied block diagram of achopper amplifier.

A dc input signal ischopped into an ac voltageand amplified by an ac-coupled amplifier. A phase-sensitive demodulator converts the output of A1

By Thomas Kugelstadt (Email: [email protected])Senior Systems Engineer, Industrial Systems

VIN

VOUT

S1

S2

R1

VIN, VOUT β V1 V2 V3 with Offset V4 V5 VOUT

0

0 0 0

t

t t t

V1 V2 V3 V4

V5

WidebandAmplifier

Low-Pass Filter

Integrator

R2

0 t

VIN

VOUT β

0 0t t

A1

Oscillator

A2

+

–

Figure 1. Chopping principle in the time domain

Note: Labels for amplifiers such as AIN, GB, and AM are used to identify amplifiers in figures and to representamplifier gain in equations.


Texas Instruments IncorporatedAmplifiers: Op Amps

20


back to dc. The demodulator consists of a switch S2 that issynchronously driven to S1. An integrator then smoothsthe switch output and presents the final dc output.

The circuit benefits from high overall dc gain and lowbaseband noise. The dc gain, being the product of the acstage and the dc gain of the integrator, easily reaches anopen-loop gain of 160 dB and reduces the gain error,

to almost zero.The baseband is defined as the maximum usable input

bandwidth. Baseband noise consists of the input offsetvoltage (also known as dc noise), the 1/f noise, and low-frequency white noise. The reduction of baseband noisehappens in several steps:

• Offset and drift in the output integrator stage are nulledby the dc gain of the preceding ac stage.

• dc drifts in the ac stage are also irrelevant because they are isolated from the rest of the amplifier by thecoupling capacitors.

• The 1/f noise of the ac amplifier is modulated to higherfrequencies via the demodulator.

Figure 2 clarifies the process of noise reduction by demon-strating the effects of chopping in the frequency domain.

The chopping of the input signal constitutes an ampli-tude modulation (AM), with the chopping frequency, fCH,being the carrier, and the input voltage representing themodulating signal. Both switches, S1 and S2, are replacedby the modulators, M1 and M2.

VM1(f) in Figure 2 shows that the modulation of a squarewave causes sidebands of the input signal to appear on

V

A AOUT

1 2,

both sides of the odd harmonics of the chopper frequency.The amplitudes of the harmonics and their sidebandsdecrease following a 1/n function, with n indicating theorder of the harmonic.

The 1/f noise of A1 present in the baseband adds to themodulated input signal after the first modulation stage,M1. The combined signal is amplified by A1 and fed intothe demodulator, M2. The 1/f noise, experiencing its firstmodulation through M2, introduces sidebands on bothsides of the odd harmonics of fCH. For the modulatedinput signal, however, M2 represents the second modulat-ing stage. VM1 is now demodulated, causing sidebands ofthe input signal to occur around the even harmonics offCH. The input signal reappears in the baseband, and theroll-off of the subsequent low-pass filter limits the base-band to frequencies far below the chopper frequency.

Note that the AM does not change the spectral densityof the white noise. The residual baseband noise is there-fore limited, low-frequency white noise.

Despite the small values for offset, drift and basebandnoise, this approach has some drawbacks. First, the ampli-fier has a single-ended, noninverting input and cannotaccept differential signals without additional circuitry at thefront end. Second, the carrier-based approach constitutesa sampled data system, and overall amplifier bandwidth islimited to a small fraction of the chopper frequency. Thechopper frequency, in turn, is restricted by ac amplifiergain-phase limitations and errors induced by switchresponse time. Maintaining good dc performance involveskeeping the effects of these considerations small. Chopperfrequencies are therefore in the low-kilohertz range, dictat-ing low overall bandwidth.

f

N(f)

fCH fCH

VM1 VM2VIN

VOUT(f)VM2(f)VIN(f) VM1(f)

VOUT

000 0 11 2 33 4 55 6f/fCHf/fCHf/fCH f/fCH

M1 M2

VNoise

A1

Figure 2. Chopping principle in the frequency domain



21


The chopper-stabilized amplifierThe classic chopper-stabilized amplifiersolves the chopper amplifier’s low-bandwidthproblem. It uses a parallel path approach(Figure 3) to provide wider bandwidth whilemaintaining good dc characteristics. The stabilizing amplifier, a chopper type, biasesthe fast amplifier’s positive terminal to forcethe summing point to zero.

Fast signals directly drive the ac amplifier,while slow ones are handled by the stabilizingchopper amplifier. The low-frequency cutoffof the fast amplifier must coincide with thehigh-frequency roll-off of the stabilizingamplifier to achieve smooth overall gain-frequency characteristics. With proper design,the chopper-stabilized approach yields band-widths of several megahertz with the low-driftcharacteristic of the chopper amplifier.Unfortunately, because the stabilizing amplifiercontrols the fast amplifier’s positive terminal,the classic chopper-stabilized approach isrestricted to inverting operation only.

In addition, the high residual output noiseof the chopper amplifier is amplified by thefast amplifier’s noise gain. Keeping outputnoise small dictates additional filter effort,thus increasing complexity and cost of thechopper-stabilized design.

The auto-zero amplifier (AZA)Similar to the chopper-stabilized approach,the AZA uses a main amplifier for widebandsignal amplification and a nulling amplifier foroffset correction. Figure 4 shows a block diagram of the TLC2654, an AZA developedby Texas Instruments in the mid-80s.

With the calibration path lying in parallelwith the signal path, both inputs of the mainamplifier are available for differential inputoperation.

The main amplifier, AM, and the nulling amplifier, AN,each have an associated input offset voltage (VOSM andVOSN, respectively) modeled as a dc offset voltage in serieswith the noninverting input. The open-loop gain of the signal inputs is given as AM and AN. Both amplifiers alsohave additional voltage inputs with the associated open-loop gains of +BM and –BN.

Offset correction of the overall amplifier occurs withinone cycle, fAZ, of the auto-zero clock and is split into twomodes of operation: an auto-zero phase and an amplificationphase. The oscillator, generating fAZ, initiates the auto-zerophase by driving both switches into position 1. The inputsof the nulling amplifier are shorted together, while its out-put is connected to capacitor C1. In this configuration AN

measures its input offset voltage and stores it via C1.Mathematically we can express the voltage at C1 as

which, by simple rearrangement, is

(1)

This shows that the offset voltage of the nulling amplifiertimes a gain factor appears at the output of AN and thuson the C1 capacitor.

In the amplification phase, when both switches are inposition 2, this offset voltage remains on C1 and essentiallycorrects any error from the nulling amplifier. AN amplifies

V VA

BC OSNN

N1 1

=+

.

V A V B VC N OSN N C1 1= − ,

VIN

VOUT

R2R1

*Similar to the chopper amplifier in Figure 1

SummingPoint

StabilizingAmplifier*

WidebandAmplifier

+

–

Figure 3. Chopper-stabilized amplifier

VIN

Oscillator

S1

VOSM

S2

VOUT

1

2

2

1

C1 C2

–BN

+BM

VC1

VC2

AM

VOSN

AN

+

–

+

–

Figure 4. Simplified TLC2654 block diagram

Note: Labels for amplifiers such as AIN, GB, and AM are used to identify amplifiers in figuresand to represent amplifier gain in equations.



22


VC1 by the factor BN and subtracts it from the amplifiedinput signal,

At the same time, the output of AN charges capacitor C2 to

Replacing VC1 with Equation 1 results in

(2)

Equation 2 shows that VOSN has been reduced by a factor1 + BN, indicating how the nulling amplifier reduces itsown offset voltage error even before correcting the mainamplifier. The potential, VC2, now serves the main amplifieras an offset correcting voltage, forcing its output, and thusthe output of the complete AZA, to

Replacing VC2 with Equation 2 and combining terms gives us

(3)

The auto-zero architecture is optimized in such a waythat AM = AN, BM = BN, and BN >> 1. This allows Equation 3to be simplified to

(4)

Most obvious is the gain product of both the main andnulling amplifiers. The ANBN term in Equation 3 explainswhy AZAs have extremely high open-loop gain. To under-stand how VOSM and VOSN relate to the overall effective

V V A B A V VOUT IN N N N OSM OSN= + +( ).

V V A A B V A VA B

BOUT IN M N N OSM M OSNN M

N= + + +

+

( ) .1

V A V V B VOUT M IN OSM M C= + +( ) .2

V A VV

BC N INOSN

N2 1

= ++

.

V V A V V B VON C N IN OSN N C= = + −2 1( ) .

A V VN IN OSN( ).+

input offset voltage of the complete amplifier, we shouldset up the equation for the generic amplifier in Figure 5:

(5)

where k is the open-loop gain of the amplifier and VOS_Effis its effective offset voltage.

Putting Equation 4 into the form of Equation 5 gives us

From here it is easy to see that k = ANBN and

Thus, the offset voltages of both the main and thenulling amplifiers are reduced by the gain factor BN. If weconsider the open-loop gains of the local amplifiers, ANand AM, to be in the region of 10,000 or higher, it quicklybecomes evident that even an inherent offset voltage ofmillivolts is reduced to an effective input offset voltage ofmicrovolts for the complete AZA.

The AZA constitutes a sampled data system. The processof sampling therefore generates frequencies consisting ofthe sum and difference of the input signal frequency, fS,and the auto-zero clock frequency, fAZ. The summing frequency, fAZ + fS, can be filtered easily and is thereforeof little importance. However, the difference frequency, fAZ – fS, can alias into the baseband if fS ≥ fAZ/2. Older AZAdesigns therefore required the limitation of the inputbandwidth to less than half of the auto-zero frequency.Most of the amplifiers available in the mid-80s had typicalclock frequencies in the range of only 400 to 500 Hz, thusnarrowing the signal bandwidth down to 250 Hz. TheTLC2654 was one of the first amplifiers that allowed high-frequency auto-zeroing at 10 kHz, thus extending theinput bandwidth up to 5 kHz.

The breakthrough to real wideband operation happenedonly with the recent introduction of AZAs such as theOPA335. Modern process technology, with gate structuresin the submicron region, made the economical integrationof complex anti-aliasing circuitry possible. The strongattenuation of alias frequencies enabled wideband opera-tion across the entire amplifier bandwidth.

VV V

BOS EffOSM OSN

N_ .=

+

V A B VV V

BOUT N N INOSM OSN

N= +

+

.

V k V VOUT IN OS Eff= +( ),_

VIN

VOS_Eff

VOUTk

+

–

Figure 5. Generic amplifier with effective offset



23


Figure 6 shows the inner structure of the OPA335. Thetwo nulling amplifiers, AN1 and AN2, operate in an alter-nate mode in parallel with the main amplifier, AM. WhileAN1 nulls its offset during the auto-zero phase, AN2 is inthe amplification phase, correcting the main amplifier’soffset voltage and vice versa.

The alternating operation of the nulling amplifiers mini-mizes output voltage ripple and intermodulation distortion(IMD) by keeping the amplifier’s gain bandwidth constantduring operation. Proprietary circuit design has made further improvements to the nulling amplifiers. Eachamplifier consists of a multistage composite amplifier. Thisconfiguration drastically reduces the quiescent currentdown to 300 µA (versus the 1.5 mA of the TLC2654) whilemaintaining a high open-loop gain of 130 dB. In addition,the previous external capacitors have been made redun-dant by achieving the same effective capacity valuesthrough Miller equivalence.

Let’s return to the process of auto-zeroing. The nullingamplifier, whose switches are in position 1, is in the auto-zero phase, thus charging its capacitor to

(6)

During the amplification phase (with switches in posi-tion 2), the output voltage of the nulling amplifier, VN,adds to the output voltage of the main amplifier, VM. With

we can replace VC with Equation 6 to obtain

(7)V G A VV

G AN B IN INOSN

B Z= +

+

1

.

V G A V V A VN B IN IN OSN Z C= + − ( ) ,

V G A V A V VG A

G AC B IN OSN Z C OSNB IN

B Z= − =

+

( ) .1

OPA335

Oscillator

1

1 = 2

VOUTVIN GO

VOSM

VOSN

VOSN

AMVM

VN

AN2

AN1

AIN

AIN

GB

GB

AZ

AZ

VC

VC

1

12

2+

+

+

+

+

+

+

–

–

–

–

–

–

–

Figure 6. Simplified OPA335 block diagram

Note: Labels for amplifiers such as AIN, GB, and AM are used to identify amplifiers in figures and to represent amplifier gain in equations.



24


The output of the main amplifier is simply

(8)

The following output stage amplifies the summing signalby the factor GO to

(9)

Inserting Equations 7 and 8 into Equation 9 yields

(10)

During the design process, the auto-zero structure is sooptimized that AM = AN and GB >> 1. This simplifiesEquation 10 to

with GOGBAIN as the overall open-loop gain and

as the effective input offset voltage of the complete AZA.

Output noise filteringHigh dc accuracy often requires additional noise filtering.How low a filter’s 3-dB frequency can be to provide effec-tive noise filtering is all too often ignored. A comparisonbetween a standard CMOS op amp and an AZA providesvaluable insight.

Figure 7 shows that the spectral noise density of a standard op amp consists of two noise characteristics: the1/f region where noise density decreases with increasing

VV

A

G

OSMOSN

Z

B

+

V G G A V

VV

A

GOUT O B IN IN

OSMOSN

Z

B= +

+

,

V G A V V G A VV

G AOUT O M OSM OSN B IN INOSN

B Z= + + +

+

( ) .1

V G V VOUT O N M= +( ) .

V A V VM M IN OSM= +( ) .

frequency, and the white noise region with constant spec-tral density. At corner frequency fC, the magnitude of 1/fnoise equals the magnitude of white noise density.

For signal-to-noise ratio calculations we require the rmsvalue of the noise within a defined frequency band. Apply-ing a first-order low-pass filter with a –3-dB cutoff at frequency fH yields an rms noise voltage of

where vnw is the white noise spectral density, fC is the corner frequency of the 1/f- and white-noise transition, fHis the upper frequency of the noise frequency band and filter cutoff, and fL is the lower frequency of the noise frequency band (here assumed to be 10–30 Hz).

Various rms voltages have been calculated with the pre-ceding equation by varying the –3-dB frequency of a first-order low-pass filter. The resulting plot is shown in Figure 8.It is important to notice that lowering the filter’s cutoff below10fC seems inefficient, since the rms noise hardly decreases.

In contrast to a standard op amp, the continuous offsetcancellation of an AZA removes the typical 1/f characteris-tic and creates the white noise spectral density in Figure 7instead. Applying the same low-pass filter provides an rmsnoise of

Plotting the rms values for various cutoff frequenciesresults in the positive slope in Figure 8. It can be seen thatreducing the filter cutoff down to low frequencies is effec-tive in establishing high dc accuracy.

One contributor to high-frequency output noise is clockfeedthrough. This term is broadly used to indicate visibilityof the auto-zero clock frequency in the amplifier outputspectrum. There are typically two types of clock feed-through. The first is caused by the settling time of the

V v frms nw H= 1 57. .

V v ff

ff frms nw C

H

LH L= + −ln . ,1 57

10 100 1 k 10 k 100 k

Frequency (Hz)

StandardOp Amp

Auto-ZeroAmplifier

1

1

10

100

1k

10k

Nois

e(n

V/

Hz)

Figure 7. Spectral noise density

10 100 1 k 10 k 100 k

Frequency (Hz)

10.1

1.0

10

100

1k

Auto-ZeroAmplifier

StandardOp Amp

rms

No

ise

(µV

)

Figure 8. rms noise voltage



25


internal sampling capacitors and is input-referred. Thesecond is caused by the small amount of charge injectionoccurring during the sampling and holding of the amplifier’sinput offset voltage.

The OPA335, however, has remarkably little noise.Although zero correction occurs at a 10-kHz rate, there isvirtually no fundamental noise energy present at that fre-quency. For all practical purposes, any glitches have energyat 20 MHz or higher and are easily filtered if required.Most applications are not sensitive to such high-frequencynoise, and no filtering is required.

ApplicationsThe temperature measurement circuit in Figure 9 is a low-frequency application that allows the OPA335 to beswitched directly into the signal path.

A precision voltage reference provides the 4.096-V bridgesupply. The forward voltage of diode D1 has a negative

temperature coefficient of –2 mV/ºC and provides cold-junction compensation via the resistor network R1 to R3.The zero adjustment for a defined minimum temperatureis achieved via R6, while R7 and R8 set the gain for theoutput amplifier. The single-supply amplifier providing anopen-loop gain of 130 dB allows 16-bit or better accuracyat high gain in low-voltage applications. Auto-zeroingremoves 1/f noise and provides typical values of 1 µV ofinput offset and 20 nV/ºC of offset drift over temperature.Thus, AZAs ideally suit single-supply precision applicationswhere high accuracy, low drift, and low noise are imperative.

The third-order low-pass filter in Figure 10 has a cornerfrequency of 20 kHz, which is twice as high as the auto-zeroclock frequency. Aliasing and intermodulation noise arehighly attenuated, which permits input signal operationacross its entire gain bandwidth. In addition, the amplifier’soutput provides rail-to-rail drive capability, allowing for ahigh signal-to-noise ratio at low supply voltages.

REF3040

R53.57 kΩ

R8150 kΩ

R7549 Ω

R16.04 kΩ

R22.94 kΩ

R360.4 Ω

R46.04 kΩ

R6200 Ω

D1

+5 V

0.1 µF

0.1 µF

4.096 V+5 V

VOUT

K-TypeThermocouple

40.7 µV/°C

OPA335

+

–

Figure 9. Temperature measurement via thermocouple

VOUT

VIN 11.8 kΩ21 kΩ2.74 kΩ

680 pF

3.3 nF

330 pFOPA335

+

–

Figure 10. A 20-kHz, third-order low-pass filter



26


In wideband applications with bandwidths in the tens ofmegahertz, the AZA provides dc accuracy to a widebandamplifier. Figure 11 shows the required circuit configura-tion in the form of a composite amplifier design.

The AZA functions as an integrator operating in the“bias path” of the wideband amplifier. The signal path stillruns from VIN via RG and RF to VOUT. The integrator hastwo functions. At low frequencies, it provides high gain tothe offset-cancellation loop, reducing the input offset ofthe wideband amplifier down to the input offset of theAZA. At high frequencies, a large time constant (RINT,CINT) ensures that the integrator’s closed-loop gain quicklydecreases to prevent signal transfer to the noninvertinginput of the wideband amplifier.

Note that the amplifier’s input noise is amplified by thenoninverting closed-loop gain of the integrator. Thus, athigh frequencies, the OPA335 operates as a voltage follower(gain = 1), passing its input noise on to the widebandamplifier. To eliminate this noise, a low-pass filter (R2, C2)with low-frequency cutoff is added to the output of theAZA. The same precaution is taken for the OPA353. Herethe low-pass filter (R1, C1) limits the output noise of thewideband amplifier.

To compensate for the signal voltage drop across R1,the feedback loop is closed by connecting the right side ofRF to the filter output. The internal feedback loop via CFestablishes stability at high frequencies by compensatingthe phase shift of the low-pass filter.

SummaryTrue chopper- and chopper-stabilized amplifiers performoffset correction through amplitude modulation. Theseamplifiers are not available as integrated circuits butrequire multiple amplifier integrated circuits instead. Thecircuit design is therefore complicated and time- and cost-intensive. Despite the extreme low values for input offsetvoltage and drift, ac performance is limited to a small frac-tion of the chopper frequency and is accompanied by highlevels of output noise.

AZAs perform offset correction by a sample-and-holdmethod. Older-generation amplifier designs benefited from integrated circuit design. Aliasing and IMD, however,narrowed the input bandwidth down to half the auto-zeroclock frequency. These devices required supply voltages of10 V minimum and had quiescent currents in the range ofmilliamperes. In addition, external capacitors were neededto store the offset-correcting voltages.

Today’s AZAs are by far the most sophisticated precisionamplifiers available. Advancements in process technologieshave drastically lowered the effects of aliasing and IMD,thus enabling true differential signal operation across theentire gain bandwidth of the amplifier. Proprietary circuitdesign has reduced the amount of supply voltage and quiescent current significantly, allowing for low-poweroperation in high-gain, high-precision applications. Theintegration of the external storage capacitors in combina-tion with the given performance enhancements makesAZAs as easy to use as standard CMOS op amps.

VIN

VOUT

RG1 kΩ

RINT

100 kΩ CINT10 nF

CF22 pF

R10 k

FΩ

R1100 Ω

C210 nF

C11 nFR2

49.9 kΩ

C = C1(R + R1)/RF O FBandwidth = 1/2 C (R + R1)π F F

Auto-ZeroAmplifier

WidebandAmplifier

OPA353

OPA335

+

–

+

–

Figure 11. Auto-zeroed wideband amplifier



27


In addition to operational amplifiers, the auto-zero tech-nique has also been implemented in a wide range of othersignal conditioning components such as:

• the OPA734/735 op amps with extended supply rangefrom 2.7 to 12 V;

• the OPA380 wideband transimpedance amplifier;

• the INA326 instrumentation amplifier for single-supplyapplications;

• the INA330 instrumentation amplifier for constant temperature control; and

• the PGA309, a fully integrated pressure sensor condi-tioning system on-chip.

Future design ideas aim to shape the noise floor ofextremely high-gain-bandwidth amplifiers by shifting energyfrom the baseband to higher, out-of-band frequencies. Thiswould approach the ideal op amp—an interesting conceptthat may not be far in the future.

Related Web sitesamplifier.ti.com


Replace partnumber with INA326, INA330, OPA335,OPA353, OPA380, OPA734, OPA735, PGA309, REF3040,or TLC2654


http://amplifier.ti.com

http://www.ti.com/sc/device/INA326

http://www.ti.com/sc/device/INA330

http://www.ti.com/sc/device/OPA335





http://www.ti.com/sc/device/PGA309

http://www.ti.com/sc/device/REF3040

http://www.ti.com/sc/device/TLC2654

28


Texas Instruments IncorporatedIndex of Articles

Analog and Mixed-Signal Products www.ti.com/aaj 2Q 2005

Title Issue Page Lit. No.

Data AcquisitionAspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .1 SLYT191Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .4 SLYT192Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .7 SLYT193Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .1 SLYT183Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . . . .November 1999 . . . .5 SLYT184A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . . .1 SLYT175The operation of the SAR-ADC based on charge redistribution . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .10 SLYT176The design and performance of a precision voltage reference circuit for 14-bit and

16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .1 SLYT168Introduction to phase-locked loop system modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .5 SLYT169New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .1 SLYT158Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .5 SLYT159Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .10 SLYT160Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .1 SLYT148Hardware auto-identification and software auto-configuration for the

TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .8 SLYT149Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .15 SLYT150Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .1 SLYT136Using SPI synchronous communication with data converters — interfacing the

MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .7 SLYT137A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . . . .February 2001 . . . .11 SLYT138A/D and D/A conversion of PC graphics and component video signals, Part 2: Software

and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .5 SLYT129Intelligent sensor system maximizes battery life: Interfacing the MSP430F123

Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . .5 SLYT123SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . . .5 SLYT114Synchronizing non-FIFO variations of the THS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .12 SLYT115Adjusting the A/D voltage reference to provide gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .5 SLYT109MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .7 SLYT110Using direct data transfer to maximize data acquisition throughput . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .14 SLYT111Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . . .5 SLYT104ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . . .5 SLYT089Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .11 SLYT090Evaluation criteria for ADSL analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .16 SLYT091Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .5 SLYT082ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .8 SLYT083Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169 . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . . .5 SLYT078Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . . .5 SLYT07314-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .13 SLYT074Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .20 SLYT075Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .27 SLYT076

Power ManagementStability analysis of low-dropout linear regulators with a PMOS pass element . . . . . . . . . . . . . . . .August 1999 . . . . . .10 SLYT194Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .13 SLYT195Migrating from the TI TL770x to the TI TLC770x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .14 SLYT196TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .8 SLYT185Synchronous buck regulator design using the TI TPS5211 high-frequency

hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .10 SLYT186

Index of Articles


http://www-s.ti.com/sc/techlit/SLYT191









































Texas Instruments Incorporated Index of Articles

29



Power Management (Continued)Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . . .November 1999 . . .14 SLYT187Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .12 SLYT177Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . . .February 2000 . . . .20 SLYT178Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . . . .May 2000 . . . . . . . .11 SLYT170Low-cost, minimum-size solution for powering future-generation CeleronTM-type

processors with peak currents up to 26 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .14 SLYT171Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . . . .August 2000 . . . . . .16 SLYT161Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .22 SLYT162Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .19 SLYT151Comparison of different power supplies for portable DSP solutions

working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .24 SLYT152Optimal design for an interleaved synchronous buck converter under high-slew-rate,

load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .15 SLYT139–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .20 SLYT140Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .9 SLYT130Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .15 SLYT131Power control design key to realizing InfiniBandSM benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .10 SLYT124Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . . . .1Q, 2002 . . . . . . . . .12 SLYT125Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .18 SLYT126SWIFTTM Designer power supply design program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .15 SLYT116Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .23 SLYT117Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .28 SLYT118Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . . .4Q, 2002 . . . . . . . . . .8 SLYT105Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . . .4Q, 2002 . . . . . . . . .12 SLYT106Understanding piezoelectric transformers in CCFL backlight applications . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .18 SLYT107Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .5 SLYT100Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .7 SLYT101Auto-TrackTM voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . . .3Q, 2003 . . . . . . . . . .5 SLYT095Soft-start circuits for LDO linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .10 SLYT096UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1 . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .13 SLYT097UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2 . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .21 SLYT092LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .14 SLYT084Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .11 SLYT079A better bootstrap/bias supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .33 SLYT077Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .5 SLYT201Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .8 SLYT202

Interface (Data Transmission)TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS) . . . . . . . . . . . . . . . . .August 1999 . . . . . .16 SLYT197Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .17 SLYT188Skew definition and jitter analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .29 SLYT179LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .33 SLYT180LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .19 SLYT172Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .30 SLYT163A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .30 SLYT153The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .35 SLYT154The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .19 SLYT132Power consumption of LVPECL and LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .23 SLYT127Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .18 SLYT085The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .21 SLYT086Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .16 SLYT080Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .11 SLYT203

















































Texas Instruments IncorporatedIndex of Articles

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Amplifiers: AudioReducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .19 SLYT198Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . . .August 1999 . . . . . .24 SLYT199PCB layout for the TPA005D1x and TPA032D0x Class-D APAs . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .39 SLYT182An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .39 SLYT1551.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .23 SLYT141Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .27 SLYT142An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .41 SLYT145An audio circuit collection, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .34 SLYT134Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .40 SLYT135Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .26 SLYT128

Amplifiers: Op AmpsSingle-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .20 SLYT189Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .23 SLYT190Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .36 SLYT181Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .22 SLYT173Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .26 SLYT174Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .33 SLYT164Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .38 SLYT165The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .42 SLYT166Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .48 SLYT167Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .44 SLYT156Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .48 SLYT157Fully differential amplifiers applications: Line termination, driving high-speed ADCs,

and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .32 SLYT143Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .38 SLYT144Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .48 SLYT146Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .25 SLYT133Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .35 SLYT119Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .42 SLYT120Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .46 SLYT121Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .21 SLYT112FilterProTM low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .24 SLYT113Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .24 SLYT108RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .9 SLYT102Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . .14 SLYT103Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .20 SLYT098Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .23 SLYT099Op amp attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .28 SLYT093Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .31 SLYT094Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .24 SLYT087Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .28 SLYT088Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .21 SLYT081Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .19 SLYT204

General InterestSynthesis and characterization of nickel manganite from different carboxylate

precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .52 SLYT147Analog design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .50 SLYT122













































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Documents

Analog Applications Journal 2Q05 - TI.com · op amp input (assuming the noise contributor is located downstream on the signal path). The next step is now to refer the totalinput-referred