AN10009 Differential Terminations

8/6/2019 AN10009 Differential Terminations

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SiTime Corporation 1 SiT-AN10009 Rev 1.0The information contained in this document is confidential and proprietary to SiTime Corporation. Unauthorized reproduction or distribution is prohibited.

SiT-AN10009 Rev. 1.09 March 2009

Differential Output TerminationsLVPECL, HCSL, LVDS, and CML

1 IntroductionSiTime offers a wide selection of differential outputs to facilitate various types of clockapplications. This application note describes each output type and the recommendedtermination methods.

2 LVPECLThe SiTime LVPECL outputs use current-mode drivers, primarily to accommodate multiplesignaling formats. Two types of LVPECL outputs are provided: LVPECL DC-coupled andLVPECL AC-coupled. The DC-coupled version has a 16 mA switched current driver while theAC-coupled version has a stronger driver with 22mA of switched current. Both types areavailable for 3.3V and 2.5V applications.

2.1 LVPECL DC-coupledThe structure of a SiTime DC-coupled LVPECL driver is shown in Figure 1.

Figure 1. SiTime DC-coupled LVPECL Output Structure

6mA 6mA

16mA

VDD

Chipboundary

OUT+

OUT


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Differential Output TerminationsLVPECL, HCSL, LVDS, CML

Each output is driven by two current sources: a switched 16 mA current source and a dedicated6 mA constant current source. The outputs are terminated to VDD-2V via 50 resistors. Whenan output is active, it will source 22 mA of current (16 mA + 6 mA). When it is not active, it willdrive only 6 mA of current. Consequently, the voltage developed across the 50 load resistorwill vary between 1.1V and 300 mV, thus creating a single-ended signal swing of 800mV.

The single-ended signal swing is 800mV nominally and could vary between 600 mV and 1000mV due to process, voltage, and temperature (PVT) variations. In addition, the output voltage isproportional to the value of the load resistor. Therefore, large resistor variations may result inexcessive voltage swing variations beyond the limits above. For systems sensitive to signalswings beyond the nominal range, the usage of 1% precision resistors is recommended.

2.1.1 Termination Recommendations

If a termination voltage source (VDD -2V) is readily available, then each output can beterminated simply with a 50 resistor to the termination voltage as shown in Figure 2. The 50resistors should be placed as close to the receiver as possible.

Figure 2. DC-coupled LVPECL with load termination

In applications where the termination voltage is not readily available, a pull-up and a pull-downresistor forming a Thevenin Equivalent network can terminate the 50 transmission line whileestablishing an effective termination voltage of VDD-2V at the receiver. This terminationmethod is shown in Figure 3. Please note that the resistor values are different for 3.3V and2.5V operations.

VT = VDD 2.0V

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+


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Figure 3. DC-coupled LVPECL load termination with Thevenin Equivalent Network

The termination methods in Figures 2 and 3 work well if the impedance of the PC trace and theimpedance of the termination circuit at the load end are reasonably matched. However, that isnot always an adequate assumption because the termination circuit also includes the receiversinput structure and the receivers package.

The termination at the receiver (load) end can be viewed as a RLC circuit with an impedance ofZload. Because Zload and Zo are seldom matched exactly, some of the signal from the driver(source) will be reflected back. The amount of signal reflected is determined by the reflectioncoefficient of the load (L).

oLoad

oLoad

L

ZZ

ZZ

+

= Equation 1

Generally speaking, the L in terminated interfaces shown in Figures 2 and 3 is relatively small

(less than 10%), so only a small amount of the signal will be reflected back towards the source.However, the source also has its own reflection coefficient (S) and it is defined as:

oSource

oSource

S

ZZ

ZZ

+

= Equation 2

where Zsource is the impedance of the driver. For the SiTime LVPECL current driver, the outputimpedance is the range of several K-ohms, so S is close to 100%; thus reflecting back virtuallyall the signal from the load. Fortunately, the majority of the signals will be absorbed by the loaddue to its low L value.

R4R2

Z = 50

Z = 50

R1 R3

VDD

R1 R2 R3 R4VDD

133 82 1333.3V

2.5V

82

250 25062.5 62.5

OUT+

OUT- D-

D+


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For most applications, the single termination at the load is sufficient. In situations where theload reflection coefficient is relatively high, the round trip reflected signal may result inerroneous triggering of the receiver. To eliminate this effect, a double termination strategy, asshown in Figure 4, may be used.

Figure 4. AC-coupled LVPECL with double termination (source and load)

With the addition of the 50 termination at the source, a 25 equivalent load is presented to theLVPECL driver; causing the signal swing to reduce from 800 mV to 400 mV. If this signal levelis insufficient for the receiver, the user can choose the LVPECL, AC Coupled version of theoscillator with higher switched current drivers. The switched current sources (see Figure 1) inthese oscillators are enhanced from 16 mA to 22 mA, thus increasing the signal swing for a 25load from 400 mV to 550 mV.

2.2 LVPECL AC-coupledIf the LVPECL output drives a differential receiver with a different common mode voltage, thenan AC-coupled connection is recommended. A capacitor is used to block the DC path to thereceiver, allowing its inputs to be biased by a separate circuit. Figure 5 shows such a

connection. In this example, the receiver inputs are biased by a 50 resistor to a terminationvoltage (VT). The value of VT is determined by the common mode voltage requirement of thereceiver.

In an AC-coupled connection, the capacitor blocks the DC path for the drivers outputs.Therefore, additional 150 resistors are installed between the outputs and ground at the sourceend to provide the required DC current paths.

VT = VDD 2.0V

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+

VT = VDD 2.0V

5050


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Figure 5. AC-coupled LVPECL

From the AC stand point, the 150 resistor at the source is in parallel with the 50 resistor atthe load, resulting in a 37.5 equivalent load to the driver. If the LVPECL, DC-coupled versionwith 16 mA current drivers is used, the receiver will observe a 595 mV signal swing. While thissignal level may be sufficient for most of the receivers, some of them may require a larger signalswing. For those applications, the user could choose the LVPECL, AC Coupled version with22 mA current drivers; thus increasing the nominal signal swing to 825 mV.

3 HCSLThe High Speed Current Steering Logic output (Figure 6) is driven by a 15 mA switched currentsource typically terminated to ground via a 50 resistor. The nominal signal swing is 750 mV.

Figure 6. HCSL output structure

VT (receiver dependent)

5050

Z = 50

Z = 50

150150

100 nF

100 nF

OUT+

OUT- D-

D+

15mA

VDDChip

boundary

OUT+

OUT-


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The HCSL interface is typically source-terminated with a 50 load as shown in Figure 7. Theopen-drain transistor at the output has fairly high impedance in the range of several kilo-ohms.From an AC standard point, the impedance of the output transistor is parallel to the 50 loadresistor, resulting in an equivalent resistance very close to 50 ohms. Since the PC traces usedin this interface has a characteristic impedance of 50, any signal reflected from the load will beabsorbed at the source. The 10 30 series resistor is not part of the termination circuit andits value is layout dependent. It is used as an overshoot limiter by slowing down the rapid rise ofcurrent from the output. SiTime recommends 20 ohms as the starting value for the seriesresistor.

Figure 7. HCSL Interface Termination

4 LVDSLVDS (Low-Voltage Differential Signaling) is a high-speed digital interface suitable for manyapplications that require low power consumption and high noise immunity. It is defined in theTIA/EIA-644 standard. LVDS uses differential signals with low voltage swings to transmit dataat high rates. Figure 8 is the diagram of a LVDS driver consisting of a 3.5 mA nominal currentsource connected to differential outputs via a switching network. The outputs are typicallyattached to 100-ohm differential transmission lines terminated with a 100 resistor at thereceiver end. The resistor matches the impedance of the transmission lines and provides a

current path for the signal. The common mode voltage is specified at 1.2V.

Signal switching is accomplished with four transistors labeled A, B, C, and D, respectively.Because the impedance of the receiver is typically high, virtually all the current from the driverwill flow through the 100 resistor, resulting in a voltage difference of 350 mV between thereceiver inputs. In Figure 8, when the signal IN is low, transistors A and B will be turned on; thecurrent will flow through transistor A, the 100 resistor, and return through transistor B. Whensignal IN is high, transistors C and D will be turned on; the current will flow through transistor C,the 100 resistor, and return through transistor D.

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+

10-30

10-30


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Figure 8. LVDS driver shown with termination resistor

It is important to note that direction of the current flowing through the resistor changes accordingto the state of the output signal. For the receiver, the direction of the current flowing through thetermination resistor determines whether a positive or negative differential voltage is registered.A positive differential voltage represents a logic high level, while a negative differential voltagerepresents a logic low level.

SiTime provides two types of LVDS output swings: normal and high. The normal swing versionhas a 3.5mA current source while the high swing version features a 7 mA current source. Thehigh swing version is designed to be used in double termination configurations. Both versionsare available for 3.3V and 2.5V applications.

4.1 Termination Recommendations

4.1.1 DC Termination

A LVDS interface with 100 differential traces is typically terminated at the receiver end with a100 resistor across the differential inputs of the receiver (see Figure 9). Some receivers haveincorporated the 100 resistor on-chip, so no external termination component is required withthose receivers.

3.5mA

VDD Chipboundary

OUT+

OUT-

3.5mA

100

ININ A

B

C

D


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Figure 9. LVDS single DC termination at the load

For most applications, a single termination at the load is sufficient. In situations where the loadreflection coefficient is relatively high, a double termination arrangement may reduce the overallround trip reflection and prevent the erroneous triggering of the receiver (see Figure 10). Pleaserefer to section 2.1.1 for more information.

With a 100 resistor at both the source and the load, the equivalent resistance seen by theoutput driver is reduced to 50; causing the output signal swing to be cut by half. SiTimeprovides the high swing version for its LVDS drivers with a 7 mA current driver to restore thedifferential signal swing back to 750 mV.

Figure 10. LVDS double DC termination

4.1.2 AC Termination

If the LVDS driver and the receiver are operating with different common mode voltages, then anAC termination is recommended. A capacitor is used to block the DC current path from thedriver, so the receiver must implement it own input bias circuit.

AC termination can be configured as either a single termination at the load or as a doubletermination. The former configuration is shown in Figure 11 while the latter configuration is

100

Z = 50

Z = 50

OUT+

OUT-D-

D+

Normal Swing

100

Z = 50

Z = 50

OUT+

OUT-D-

D+

100

High Swing


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shown in Figures 12 and 13. Please note that the high swing version may be used with thedouble termination.

Figure 11. LVDS single AC termination at the load

The double terminations shown in Figures 12 and 13 are very similar. They differ only by theposition of the DC-blocking capacitor. The capacitor in Figure 12 is charged by the commonmode current flowing through half the differential resistance, which is the equivalent of 50. Onthe other hand, the capacitor in Figure 13 is charged by the current through the resistance of thereceivers inputs which can be in the range of kilo-ohms. During clock start-up, the capacitor inFigure 12 will be charged much faster than that in Figure 13. Therefore, a valid clock signal willbe available to the receiver sooner. If fast clock start-up is important, the configuration shown in

Figure 12 is recommended.

Figure 12. LVDS double AC termination with capacitor close to source

In data transmission applications, the configuration shown in Figure 13 may be moreadvantageous. Because of its higher RC time constant, it can sustain data sequences withlonger ones and zeros without experiencing significant voltage droop.

100

Z = 50

Z = 50

OUT+

OUT-D-

D+

0.1uF

0.1uF

Normal Swing

100

Z = 50

Z = 50

OUT+

OUT-D-

D+

100

0.1uF

0.1uF

High Swing


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Figure 13. LVDS double AC termination with capacitor close to load

5 CMLSiTime Current Mode Logic (CML) drivers are constructed with a NMOS open-drain differentialpair and an 8 mA constant current source. The output structure is shown in Figure14. Becausethe open-drain transistors are only capable of pulling down a signal, external pull-up resistorsare needed. Voltage swing across a 50 resistor is typically 400 mV.

Figure 14. Output structure of a CML driver

100

Z = 50

Z = 50

OUT+

OUT-D-

D+

100

0.1uF

0.1uF

High Swing

Chipboundary

OUT+

OUT-

8 mA


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SiTimes CML clocks can operate at 3.3V, 2.5V, and 1.8V. Two output signal swing versionsare supported: normal and high. The normal swing version is equipped with an 8 mA currentsource while the high swing version has a 16 mA current source.

5.1 Termination Recommendations

5.1.1 DC Termination

A typical CML termination is shown in Figure 15. The differential outputs are pulled up to atermination voltage VT. In most cases, VDD is used as the termination voltage. However, inapplications where the driver and the receiver are operated at different VDDs, VT is typically setto the higher of the two VDDs.

Figure 15. CML with single DC load termination

In situations where the round trip reflections due to a relatively high load reflection coefficientmay cause extra triggering of the receiver, a double termination strategy, as shown in Figure 16,could be used. Please refer to section 2.1.1 for more information. In such case, both the sourceand the load are typically terminated to the same VT. Because two 50 termination resistorsare connected in parallel to the output, their equivalent resistance is reduced to 25; causing a50% reduction in the output swing. SiTime offers the CML high swing version with 16 mAcurrent drivers to restore the signal swing back to 400mV.

VDD VT 3.63V

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+

Normal Swing


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Figure 16. CML with double DC termination

5.1.2 AC Termination

An AC termination should be used if the receiver requires a different input bias. The DC path tothe receiver is blocked by the capacitor, so the user must provide a separate bias circuit for thereceiver inputs.

In many cases, a single termination at the load end is sufficient (Figure 17). The VT is typically

the VDD of the driver. For noise sensitive application, a double termination configuration shownin Figures 18 and 19 can be used. As we explained in the previous section, the High Swingversion may be used in double terminations to maintain a 400 mV signal swing.

Figure 17. CML single AC termination at the load end

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+

5050

VDD VT 3.63VVDD VT 3.63V

High Swing

Z = 50

Z = 50

OUT+

OUT-D-

D+

0.1uF

0.1uF

Normal Swing 50

VDD VT 3.63V

50


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Figure 18. CML double AC termination with capacitor close to source

Figure 19. CML double AC termination with capacitor close to load

The double terminations shown in Figures 18 and 19 are very similar. They differ only by theposition of the DC-blocking capacitor. In Figure 18, VT1 is typically the VDD of the driver andVT2 is typically the VDD of the receiver. In Figure 19, VT1 and VT2 are typically set to VDD ofthe driver.

The capacitor in Figure 18 is charged by the current flowing through the 50 terminationresistor, whereas the capacitor in Figure 19 is charged by the current through the resistance ofthe receivers inputs which can be in the range of kilo-ohms. During clock start-up, the capacitor

5050

Z = 50

Z = 50

OUT+

OUT- D-

D+

5050

VDD VT2 3.63VVDD VT1 3.63V

High Swing

0.1uF

0.1uF

Z = 50

Z = 50

OUT+

OUT-D-

D+

0.1uF

0.1uF

High Swing 50

VDD VT2 3.63V

5050 50

VDD VT1 3.63V


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in Figure 18 will be charged much faster than that in Figure 19. Therefore, a valid clock signalwill be available to the receiver sooner. If fast clock start-up is important, the configurationshown in Figure 18 is recommended.

In data transmission applications, the configuration shown in Figure 19 may be moreadvantageous. Because of its higher RC time constant, it can sustain data sequences withlonger ones and zeros without experiencing significant voltage droop.

6 ConclusionThis application note presented the SiT9102 and SiT9002 differential output driver models andthe most commonly used termination recommendations for four types of differential outputs:

LVPECL, HCSL, LVDS, and CML. Additionally, multiple current strength options in these clockssupport double termination strategies without sacrificing signal swing voltages. With such a richselection of output types, the user can easily find one that fits his/her design requirements.

SiTime Corporation

990 Almanor Avenue

Sunnyvale, CA 94085

USA

Phone: 408-328-4400

http://www.sitime.com

SiTime Corporation, 2008-2009. The information contained herein is subject to change at any time without notice. SiTimeassumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of anycircuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii)unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by

SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) beingsubjected to unusual physical, thermal, or electrical stress.

Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims anyand all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties ofmerchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage oftrade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime productand any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application orcomponent, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake.

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