An-Using Microcontrollers in DSCH

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DSCHAPPLICATION NOTE Microcontrollers

Introducing Micro-controllers in DSCHEtienne SICARD

Professor

INSA-Dgei, 135 Av de Rangueil31077 Toulouse France

email: [email protected]

This document details the implementation of two microcontroller models: the 8051 from Intel and the

16f54 from PIC.

1 Logic Model of the 8051

In DSCH3, a simplified model of the Intel 8051 micro-controller is included.

1.1 Arithmetic and Logic Unit

The 8051 core includes an arithmetic and logic unit to support a huge set of instructions. Most of the

data format is in 8 bit format. We consider here the following instructions, listed in table 1. Some

instructions do not appear in this list, such as the multiplication and division.

Mnemonic Type Description

CLR Clear Clear the accumulatorCPL Complement Complements the accumulator, a bit or a memory

contents. All the bits will be reversed.

ADD Addition Add the operand to the value of the accumulator,

leaving the resulting value in the accumulator.

SUBB Substractor Subtracts the operand to the value of the accumulator,

leaving the resulting value in the accumulator.

INC Increment Increment the content of the accumulator, the register or

the memory.

DEC Decrement Decrement the content of the accumulator, the register

or the memory.

XRL XOR operator Exclusive OR operation between the accumulator and

the operand, leaving the resulting value in theaccumulator.

ANL AND operator AND operation between the accumulator and the

operand, leaving the resulting value in accumulator.

ORL OR operator OR operation between the accumulator and the operand,

leaving the resulting value in accumulator.

RR Rotate right Shifts the bits of the accumulator to the right. The bit 0

is loaded into bit 7.

RL Rotate left Shifts the bits of the accumulator to the left. The bit 7 is

loaded into bit 0.

Table 1. Some important instructions implemented in the ALU of the 8051 micro-controller

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Accumulator A

Arithmetic and

Logic Unit

8 bits8 bits

Result S

8 bits

OpCodeinput

Registers R0..R7

Immediate value

Memory contents

CarryIn

CarryOut

Figure 2. The arithmetic and logic unit of the 8051

For example:

ADD A,R0 (Opcode 0x28) overwrites the accumulator with the result of the addition of

A and the content of R0.

SUBB A,#2 (Opcode 0x94 0x02) overwrites the accumulator with the result of the

subtraction of A and the sum of the Carry and the byte 0x02.

INC A (0x04) increments the content of the accumulator.

DEC A (0x14) Decrements the content of the accumulator.

ANL A,#10 (0x54) overwrites the accumulator with by the AND-gating of A and the

constant 0x10.

ORL A,R7 (0x4F) overwrites the accumulator with by the OR-gating of A and the

content of R7.

XRL A, R1 (0x69) overwrites the accumulator with the result of the XOR-gating of A

and the content of the internal register R1.

1.2 Inside the 8051

A simplified model of the 8-bit micro-controller 8051 exists through the symbol 8051.SYM

accessible using the command Insert User Symbol. The symbol is also directly accessible through

the symbol palette starting version 3.5.

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Figure 3. The IEEE symbol library contains the 8051 symbol (8051.SYM)

Figure 4. Access to the 8051 symbol from the palette, in the Advanced list

The symbol consists mainly of general purpose input/output ports (P0,P1,P2and P3), a clockand a

resetcontrol signals. The basic connection consists of a clock on the Clockinput and a button on the

Resetinput (Figure 5).

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Figure 5. The 8051 symbol and its embedded software (8051.SCH)

After a double-click in the symbol, the embedded code appears. That code may be edited and modified

(Figure 6). When the button Assemblyis pressed, the assembly text is translated into executable

binary format. Once the logic simulation is running, the code is executed as soon as the reset input is

deactivated. The value of the program counter, the accumulator A, the current op_codeand the

registers is displayed.

1.3 Minimum features for running the 8051

The user should

1. Add a clock on input Clock

2. Add a button on input RST

3. Double click on the symbol and click Assembly so that the editable text of the code isconverted into assembly code

4. Run the logic simulator

5. Click the RST button (RST=1, button red) so that Reset is INACTIVE

In the chronograms, the accumulator variations versus the time are displayed. It can be noticed that

this core operates with one single clock cycle per instruction, except for some instructions such as

MOV (Move data) and AJMP (Jump to a specific address).

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Click Assembly to compute

Figure 6. The default code proposed in the 8051 component compiled using DSCH3

(8051.SYM)

Figure 7. The simulation of the arithmetic and logic operation using the 8051 micro-controller

(8051.SCH)

1.4 Traffic light Example

An example of code and schematic diagram for traffic light control is proposed below. Notice the

subroutine call through the instruction AJUMP.

Figure 8. A simple code for 8051 micro-controller for traffic light control

(8051_traffic_lights.sch)

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Figure 9. Interface for compiling the code for the traffic light controller(8051_traffic_lights.sch)

Ports are activated using control commands such as MOV P3,#0, while port input pins are tested

through the instruction such as JB P2.2,URG. See table 2 for the complete code embedded in the

8051 processor.

/ / Traf f i c Li ghts E. Si card/ / 11. nov. 01L1 MOV P3, #84H

ACALL TEMPO

{ Feu1=r , F2=ver t }J B P2. 2, URGJ B P2. 1, FJAJ MP L1

FJ ACALL TEMPOMOV P3, #88H

{ Feu1=r , F2=j aune}ACALL TEMPOMOV P3, #90HACALL TEMPO

{ r, r}L2 MOV P3, #30H{ v , r }

J B P2. 2, URGJ B P2. 0, FJ 1AJ MP L2

FJ 1 ACALL TEMPOMOV P3, #50HACALL TEMPO

{ j , r }

MOV P3, #90HACALL TEMPO{ r, r }

MOV P3, #84HAJ MP L1

{ Tempor i sat i on}TEMPO NOP

NOPNOP

NOPNOPNOPNOPRET

{ Ur gence }URG MOV P3, #48H

NOPMOV P3, #0J NB P2. 2, L1AJ MP URG

Table 2. Code embedded in the traffic light controller (8051_traffic_lights.sch)

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2 Model of the PIC 16f84

DSCH3 includes the model of the PIC16f84 micro-controller.

2.1 Activating Ports of the 16f84

The following program is used to activate the Port B as output. The schematic diagram which

implements this code is 16f84.SCH (Fig. 10). The corresponding simulation is reported in Fig. 11.

; PI C16f 84 by Eti enne Si card f or Dsch; Si mpl e pr ogr am t o put 10101010 on por t B; 01010101 on port B;Por t B equ 0x06 ; decl ares t he addr ess of out put port B

org 0l oop movl w 0x55 ; l oad W wi t h a pat t ern ( hexa f ormat)

movwf Port B ; Moves t he pat t ern t o por t Bmovl w 0xaa ; l oad W wi t h an other pat t ernmovwf Port B ; Moves t he pat t ern t o por t Bgoto l oop ; and agai n

Figure 10. Simulation of the PIC 16f84 (16f84.SCH)

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Figure 11. Activating output ports of the PIC 16f84 (16f84.SCH)

2.2 Adder using 16f84

An example file can be found in 16f84adder.SCH. Double click the 16f84 symbol, and click

Assemblyto convert the text lines into binary executable code.

; Si mpl e pr ogram t o add t wo number s;oper 1 EQU 0x0coper 2 EQU 0x0dr esul t EQU 0x0e

or g 0

movl w 5movwf oper 1movl w 2movwf oper 2movf oper 1, 0addwf oper 2, 0movwf r esul tsl eep

Then click OK, run the simulation. Click theResetbutton to activate the processor. The default code

realizes the addition of two numbers (Instruction addwf) and stores the result in the internal registers.

Modify the code to perform the AND (Instruction andwf), OR (Instruction i or wf) , XOR

(Instruction xor wf) and SUB (Instruction subwf) operations.

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Figure 12. Adder using PIC 16f84 (16f84_adder.SCH)

3 References

E. Sicard, S. Ben Dhia Basic CMOS cell Design Mc Graw Hill professional series, 2006, http://books.mcgraw-

hill.comE. Sicard. Microwind & Dsch user's manual version 3.5on-line at http://www.microwind.org

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http://books.mcgraw-hill.com/http://books.mcgraw-hill.com/http://www.microwind.org/http://www.microwind.org/http://www.microwind.org/http://books.mcgraw-hill.com/http://books.mcgraw-hill.com/


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4 Appendix

4.1 8051 Labels

Name Descr i pt i on Addr essSP St ack $81P0 Port 0 $80P1 Port 1 $90P2 Port 2 $A0P3 Port 3 $B0P0. 0 Por t 0 bi t 0 $80P0. 1 Por t 0 bi t 1 $81P0. 2 Por t 0 bi t 2 $82P0. 3 Por t 0 bi t 3 $83P0. 4 Por t 0 bi t 4 $84P0. 5 Por t 0 bi t 5 $85P0. 6 Por t 0 bi t 6 $86P0. 7 Por t 0 bi t 7 $87

4.2 8051 Instruction Model

CASE muCode OF$0 : ;$1 : muAddr ess: = Next Byt e(1) ;$3 : i f ( muregA AND $01) 0 t hen muregA: =( muregA shr 1) +$80

el se muregA: =( muregA shr 1) ;$4 : I F muRegA


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$48, $49, $4A, $4B, $4C, $4D, $4E, $4F: muregA: =muregA or mureg[mucode- $48] ;$54 : muregA: =muregA and Next Byte( 1) ;

$58, $59, $5A, $5B, $5C, $5D, $5E, $5F: muregA: =muregA and mureg[ mucode- $58] ;$60 : i f muregA=$0 t hen j umprel at i ve( 1) el se muAddr ess: =muAddr ess+2;$64 : muregA: =muregA xor Next Byt e( 1) ; / / XRL$68, $69, $6A, $6B, $6C, $6D, $6E, $6F: muregA: =muregA xor mureg[ mucode- $68] ;$70 : i f muregA$0 t hen j umprel at i ve( 1) el se muAddr ess: =muAddr ess+2;

$73 : j umpr el at i ve( 1) ;$74 : muRegA : = NextByt e( 1) ;$75 : DumpDat a(1, NextByt e(2) ) ;$78, $79, $7A, $7B, $7C, $7D, $7E, $7F: mureg[mucode- $78] : =mumem[ muAddress+1] ;$B2 : i f Pi n( Bi t Pi n( 1) ) =l ogi c1 t hen

Store( Bi t Pi n(1) , l ogi c0)el seStore( Bi t Pi n(1) , l ogi c1) ;

$B4 : i f muRegANextByt e(1) t hen J umpRel at i ve(2)el se muAddress : =muAddress+3;

$B8, $B9, $BA, $BB, $BC, $BD, $BE, $BF: i f mureg[ mucode- $B8]Next Byt e( 1)t hen j umpr el ati ve( 2)el se muAddress : =muAddress+3;

$C2 : St ore(Bi tP i n( 1) , l ogi c0);$D2 : Store(Bi t Pi n( 1) , l ogi c1) ;$E4 : muregA: =0; / / CLR A$E5 : muRegA : = Dat aOf Byt e( 1);$E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF: muregA : = mureg[ mucode- $E8] ;$F4 : muregA: =muregA xor $FF; / / CPL$F5 : DumpDat a( 1, muRegA) ;$F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF: mureg[mucode- $F8] : =muregA;

END;

4.3 16f84 Instruction Model

I F words[ 2]=' ADDLW' t hendataWor d : = addl w OR ( HexAdr( wor ds[ 3] ) AND $FF)

el seI F words[ 2]=' ANDLW' t hendataWor d : = andl w OR ( HexAdr( wor ds[ 3] ) AND $FF)

el se

I F words[ 2]=' ADDWF' t hendataWor d : = addwf OR (HexAdr( wor ds[ 3] ) AND $7F) OR (( HexAdr( words[ 4] ) AND $01) SHL 8)

el seI F words[ 2]=' ANDWF' t hendataWor d : = andwf OR (HexAdr( wor ds[ 3] ) AND $7F) OR (( HexAdr( words[ 4] ) AND $01) SHL 8)

I F words[ 2]=' BCF' t hendat aWord : = bcf OR (HexAdr( words[ 4] ) SHL 7) OR (HexAdr( words[ 3]) AND $7F)

el seI F words[ 2]=' BTFSC' t hendat aWord : = bt f sc OR (HexAdr( words[ 4] ) SHL 7) OR ( HexAdr( words[ 3] ) AND $7F)

el seI F words[ 2]=' BSF' t hendat aWord : = bsf OR (HexAdr( words[ 4] ) SHL 7) OR (HexAdr( words[ 3]) AND $7F)

el seI F words[ 2]=' BTFSS' t hen

dat aWord : = bt f ss OR (HexAdr( words[ 4] ) SHL 7) OR ( HexAdr( words[ 3] ) AND $7F)

I F words[ 2]=' CALL' t hendat aWord : = cal l OR ( HexAdr( words[ 3] ) AND $7FF)

el seI F words[ 2]=' CLRF' t hendat aWord : = cl r f OR ( HexAdr( words[ 3] ) AND $7F)

el seI F words[ 2]=' CLRW' t hendat aWord : = cl r w OR (HexAdr( words[ 3] ) AND $7F)

el seI F words[ 2]=' CLRWDT' t hendataWord : = cl r wdt

el seI F words[ 2]=' COMF' t hendataWor d : = comf OR (( HexAdr( wor ds[ 4] ) AND $01) SHL 7) OR (HexAdr( wor ds[ 3] ) AND $7F)

I F words[ 2]=' DECFSZ' t hendataWor d : = decf sz OR ( ( HexAdr( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr( words[ 3] ) AND $7F)

el se

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I F words[ 2]=' DECF' t hendataWor d : = decf OR ( ( HexAdr( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr( wor ds[ 3] ) AND $7F)

I F wor ds[ 2]=' EQU' t hen DoNot hi ng ELSEI F words[ 2]=' END' t hen DoNot hi ng

I F words[ 2]=' GOTO' t henBEGI N

dat aWord : = got o1 OR (HexAdr( words[ 3] ) AND $7FF) ;END

I F words[2] =' I NCF' t hendataWor d : = i ncf OR ( ( HexAdr( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr( wor ds[ 3] ) AND $7F)

el seI F words[ 2]=' I NCFSZ' t hendat aWord : = i ncf sz OR ( ( HexAdr( words[ 4] ) AND $01) SHL 7) OR (HexAdr( words[ 3] ) AND $7F)

el seI F words[ 2]=' I ORLW' t hendat aWord : = i or l w OR ( HexAdr( words[ 3] ) AND $FF)

el seI F words[ 2]=' I ORWF' t hendataWor d : = i or wf OR ( ( HexAdr( words[ 4] ) AND $01) SHL 7) OR ( HexAdr( wor ds[ 3] ) AND $7F)

I F words[ 2]=' MOVLW' t hendataWor d : = movl w OR (HexAdr( wor ds[ 3] ) AND $FF)

el seI F words[ 2]=' MOVF' t hendataWor d : = movf OR (HexAdr( wor ds[ 3] ) AND $7F) OR (( HexAdr( wor ds[ 4] ) AND $01) SHL 7)

el seI F words[ 2]=' MOVWF' t hendataWor d : = movwf OR (HexAdr( wor ds[ 3] ) AND $7F)

I F words[ 2]=' NOP' t hendat aWord : = nop;

I F words[ 2]=' ORG' t henBEGI N

actual Addr ess: =HexAdr ( words[ 3]) ;byt eNumber : =0;i gnoreLi ne : = TRUE;

END

I F words[2] =' RETFI E' t hendat aWord : =r et f i e

el seI F words[ 2]=' RETLW' t hendataWor d : =r et l w OR ( HexAdr( wor ds[ 3] ) AND $FF)

el seI F words[ 2]=' RETURN' t hendataWor d : =r et urn

el seI F words[ 2]=' RLF' t hendat aWord : = r l f OR ( HexAdr( words[ 3] ) AND $7F) OR ( ( HexAdr( words[ 4]) AND $01) SHL 7)

el seI F words[ 2]=' RRF' t hendat aWord : = r r f OR (HexAdr( words[ 3] ) AND $7F) OR ( ( HexAdr( words[ 4]) AND $01) SHL 7)

I F words[ 2]=' SLEEP' t hendat aWord : = sl eep1el seI F words[ 2]=' SUBLW' t hendat aWor d : =subl w OR ( HexAdr ( wor ds[ 3] ) AND $FF)

el seI F words[ 2]=' SUBWF' t hendataWor d : = subwf OR ( HexAdr( wor ds[ 3] ) AND $7F) OR ( ( HexAdr( words[ 4] ) AND $01) SHL 7)

el seI F words[ 2]=' SWAPF' t hendataWor d : = swapf OR ( HexAdr( wor ds[ 3] ) AND $7F) OR ( ( HexAdr( words[ 4] ) AND $01) SHL 7)

I F words[ 2]=' XORLW' t hendat aWord : = xorl w OR (HexAdr( words[ 3] ) AND $FF)

el seI F words[ 2]=' XORWF' t hendataWor d : = xorwf OR ( HexAdr( wor ds[ 3] ) AND $7F) OR ( ( HexAdr( words[ 4] ) AND $01) SHL 7)

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