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An update on Power Pulsing with SDHCAL
Kieffer Robert IPN Lyon« CALICE collaboration meeting »
May 2011, CERN
21/05/11 [email protected] 1
Intro: SDHCAL Part I: The power pulsing with HARDROCsPart II: Beamtest under B field @ CERNConclusion
OutlineOutline
21/05/11 [email protected] 2
Absorber: 2 cm thick iron plates Each sensitive cassette sensitive cassette contains a readout boardreadout board stick to a GRPCGRPC. Total (barrel + end caps): 50 millions 50 millions readout channels (1x1cm2) HARDROC power dissipation: 7.5 μW/channel7.5 μW/channel (using power pulsing)
=>375 W =>375 W for the whole SDHCAL very front end boards. Detector interface cards located on border sides host FPGAs: these cards will probably need active cooling or the use of specific power pulsed ASICs to operate data transfer tasks.
Absorber: 2 cm thick iron plates Each sensitive cassette sensitive cassette contains a readout boardreadout board stick to a GRPCGRPC. Total (barrel + end caps): 50 millions 50 millions readout channels (1x1cm2) HARDROC power dissipation: 7.5 μW/channel7.5 μW/channel (using power pulsing)
=>375 W =>375 W for the whole SDHCAL very front end boards. Detector interface cards located on border sides host FPGAs: these cards will probably need active cooling or the use of specific power pulsed ASICs to operate data transfer tasks.
SDHCALSDHCAL
21/05/11 [email protected]
• The readout board readout board hosting 24 chips connected through a daisy chain scheme is controled by a DIF DIF (detector interface)(detector interface)
• This board is fixed on a 50x33 cm2 GRPC detector.
SDHCAL power pulsing test ASUSDHCAL power pulsing test ASUThe active sensitive unit:The active sensitive unit:
• A non-magnetic metallic cassette contains this assembly.21/05/11
DIFDIF Redout board 1536 channelsRedout board 1536 channels
SDHCAL power pulsing principleSDHCAL power pulsing principle
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Readout architecture common to all calorimeters and minimization of data lines & power
Daisy chain using token ring mode Open collector, low voltage signals Low capacitance lines
Acquisition DAQ IDLE MODEChip 0
Chip 1 Acquisition DAQ IDLE MODEIDLE
Chip 2 Acquisition IDLE MODEIDLE
Chip 3 Acquisition IDLE MODEIDLE
Chip 4 Acquisition IDLE MODEIDLE DAQ
1ms (.5%) .5ms (.25%)
1% duty cycle 99% duty cycle
198ms (99%)
5 ev
ents
3 ev
ents
0 ev
ent
1 ev
ent
0 ev
ent
Chip 0 Chip 1 Chip 2 Chip 3 Chip 4
Data bus
Courtesy :N.Seguin Moreau LAL
Power Pulsing in HARDROCPower Pulsing in HARDROC
Shut down bias currents and reference voltages with vdd: ALWAYS ALWAYS ONONBandgap + other ref voltages + master I : POWER PULSED ON/OFFPOWER PULSED ON/OFF
Shut down bias currents and reference voltages with vdd: ALWAYS ALWAYS ONONBandgap + other ref voltages + master I : POWER PULSED ON/OFFPOWER PULSED ON/OFF
3 Power pulsing lines Power pulsing lines used: AnlogAnlog, ADCADC, DigitalDigital Each stage can be power pulsed (or not) by setting setting ON/OFF the related slow control shift registers ON/OFF the related slow control shift registers.
3 Power pulsing lines Power pulsing lines used: AnlogAnlog, ADCADC, DigitalDigital Each stage can be power pulsed (or not) by setting setting ON/OFF the related slow control shift registers ON/OFF the related slow control shift registers.
Slow control shift registersSlow control shift registers
Analog power line
ADC power line
21/05/11 [email protected]
Power lines sequencePower lines sequence
Power analog. (DAQ)Power analog. (DAQ)
Power DAC (DAQ)Power DAC (DAQ)
Power digital (DAQ)Power digital (DAQ)
Power digital (POD)Power digital (POD)
• The Power On Digital manage the LVDS buffers to provide clock signal only when needed.
• When the StartReadout comes from the daisy chain loop to trigger the data transfer, Power digital line is automatically switched ON by the POD.
Idle IdleREADOUTREADOUT4ms/chip Abs. Max.
ACQUISITIONACQUISITION
Controled by the DIFControled by the DIF
POD modulePOD module
21/05/11 [email protected]
Power consomption on HARDROCPower consomption on HARDROC
HR2 ON
Vdd_pa 5.5 mA
Vdd_fsbx3 12.3 mA
Vdd_d0,1,2 7.3 mA
Vdd_bandgap 1.2 mA
Vdd_dac 0.84 mA
Vddd 0.67 mA
vddd2 0.4mA(=0 if 40MHz
OFF)
Total (noPP) 29 mA
Total with 0.5% PP
145 µA
Pwr_on_a alone 26.5mA
Pwr_on_dac 1.0 mA
Pwr_on_d 1.0 mA
ALL OFF <4µA
ILD Requirement: 10 µW/ch with 0.5% duty cycle 200 µA for the entire chip (64 channels)
HR2 power consomption measurement: 29 mA x 3.3V ≈ 100 mW => 1.5 mW/ch 7.5 µW/ch with 0.5% duty cycle
Power consomption of each digital part Power consomption setting up
the tree power lines: AnlogAnlog, ADCADC, DigitalDigital
21/05/11 [email protected]
Power pulsing test beamJune 2010: 10 days, SPS H2, parasitic operation
Beam conditions: 80GeV @ High RateAim: PowerPulsing tests using B field.PowerPulsed events: 42 kEventsNon-PowerPulsed events: 74 kEvents
BeamBeam
BeamBeam
32x48 cm2 GRPC
B fieldfield
3T Magnet3T Magnet3T Magnet3T Magnet
A testbeam under B fieldA testbeam under B field
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I Current (Power Pulsing)
First tests with B fieldPower pulsing cyclePower pulsing cyclePower OnPeriod: 10ms(100 Hz)DutyCycle: 2/10
2 ms
Enable Acquisition
Trigger for chip readout
Injecting on falling edge through a 2pC build in capacitor
Scintillator Coincidence
« In Spill » Signal &Veto From Acquisition
DIFTriggerTrigger
Power OnPower On
ASU
BusyBusy
Trigger
21/05/11 [email protected]
Clock period:Time selection for
triggered events:
Noise contamination ratio:
NoiseNoise
Signal+NoiseSignal+Noise
0<EvTime<1.2us0<EvTime<1.2us
1%1%
400ns400ns
Data time structure no Power PulsingData time structure no Power Pulsing
Time to trigger spectraTime to trigger spectra
Time to external trigger in clock counts
21/05/11 [email protected]
First tests with B fieldEfficiency with power pulsingEfficiency with power pulsingAbout 4% efficiency loss!
3T B field3T B field
Remember my talk @ CALICE CASBALANCA
21/05/11 [email protected]
A suspicious behaviour suspicious behaviour as been pointed out in the time to trigger distribution using power pulsingpower pulsing! First we filtered filtered out out these events.
Digging into the data to understandDigging into the data to understand
NoiseNoiseSignal+Noise?Signal+Noise?
Signal+Noise ?Signal+Noise ?
Time to external trigger in clock counts
21/05/11 [email protected]
In the HARDROC, there is a double latch procedure applied on the BCid if the reset command is set before start_acquisition command adding 3 clock count to this timing flag: this is the classical scheme (right peak)the classical scheme (right peak). On each power cycle, the first triggethe first trigger is recorded without these 3 clock count because the reset happen after the start_acquisition command (left peak)(left peak).
Digging in the DIF’s FPGA firmware we found the reason of this double peak structure!
Two kind of Bcid:
First tests with B fieldDigging into the data to understandDigging into the data to understand
Some trigger have been taken by the DIF during the waking up time. Indeed, in the firmware the trigger veto was removed during all power_on period, but before the 100μs waking time there is no data in the chip to be readed out.
=> First these no data triggers where thought as inefficient triggers an we lose efficiency.
Spatial cut in data
20 cm Cut
13 cm Cut
Position X (cm)
Pos
ition
Y (
cm)
21/05/11 [email protected]
Another firmware faillure: trigger recorded while HARDOC is sleeping
Only the triggers taken in the beam area are taken in account as good events for efficiency studies.
First tests with B fieldEfficiency using Power PulsingEfficiency using Power Pulsing3T B field3T B field
Now we can say that: Now we can say that: No efficiency loss No efficiency loss is found runing under power pulsing.
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First tests with B fieldTiming of power cycle in the dataTiming of power cycle in the data
Trigger taken in the same power-cycle (2ms)
Trigger taken in two consecutive power-cycles (10ms)
One cycle without trigger (20ms)
Two cycles without trigger…
Up to 11 power-cycles acquiring during a spill !!!
Gaussian fit sigma: ±0.84 ms<=> Power on 2ms
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First tests with B fieldSummarySummary
Power pulsing scheme validated in testbeam with SDHCAL prototype, and the data is now well understood.
Power consumption matches our goals.
Up to now:Up to now:
Next:Next: Publish a paper about these interesting results. Go to a large scale prof of power pulsing: maybe on SDHCAL physical
protoype in a second period.(SDHCAL under construction: testbeam scheduled June 2011)
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First tests with B fieldInjection with power pulsingInjection with power pulsing
Power OnT: 100msDutyCycle 2/100
2.15 ms
Enable Acquisition
Trigger Trigger for chip readout
Charge injection on falling edge
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First tests with B fieldInjection with power pulsingInjection with power pulsing
Power OnT: 100msDutyCycle 2/100
2.15 ms
Enable Acquisition
Trigger for chip readout
Injecting on falling edge through a 2pC build in capacitor
Power OnPower OnPower OnPower On
DIF ASU
Trigger21/05/11 [email protected] 21
POWER PULSING: « AWAKE TIME »
PWR ON
FSB0
8 µs
All decoupling capacitors removed on bias voltages
PWR ON: ILC like (1ms,199ms) PP of the analog part:
Input signal synchronised on PWR ON
Awake time= 8 µs
DAC output (Vth)
Trigger
25 µs
PWR ON
Power pulsing of the 10 bit-DAC: 25 µs (slew rate limited)
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First tests with B fieldInjection with power pulsingInjection with power pulsing
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First tests with B fieldInjection with power pulsingInjection with power pulsing
We will use this point Charge: 0.54 pCEff: 96.4% To check time stability.time stability.
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First tests with B fieldInjection with power pulsingInjection with power pulsingSuspecting threshold stability, we injected charges with different delays from Power-ON edge. Efficiency is quite constantquite constant during the 2ms power cycle. Work is still ongoing still ongoing to understand efficiency loss recorded on beam data.
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First tests with B fieldPreliminary tests using B fieldPreliminary tests using B field
Is B fieldB field having an effect on cluster shape?effect on cluster shape?
No Power Pulsing
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Preliminary tests using B fieldPreliminary tests using B field
B field has no impactno impact on efficiencyefficiency.
No Power Pulsing
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Preliminary tests using B fieldPreliminary tests using B field
B fieldB field increase a bit a bit the multiplicitymultiplicity.
No Power Pulsing
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