IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009 529

An Improvement to the Numerical Robustness of theSurface Potential Approximation for

Double-Gate MOSFETsVenkatnarayan Hariharan, Student Member, IEEE, Juzer Vasi, Fellow, IEEE,

and V. Ramgopal Rao, Senior Member, IEEE

Abstract—In developing the drain current model of a symmetricdouble-gate MOSFET, one encounters a transcendental equationrelating the value of an intermediate variable β to the gate anddrain voltages. In this brief, we present an enhancement to anexisting approximation for β, which improves its numerical ro-bustness. We also benchmark our suggested enhancement andshow that our enhancement is as computationally efficient as theoriginal approximation but is numerically much more robust, withan accuracy that is comparable to the original approximation.

Index Terms—Approximation, charge, compact model,DGFET, MOSFETs, surface potential.

I. INTRODUCTION

THERE have been many core models for the drain currentof a symmetric double-gate MOSFET [2]–[14]. In such

models, one typically encounters a transcendental equation [4]relating the value of an intermediate variable β (which we callβ1 in this brief) to the gate and drain voltages. This equation canonly be solved numerically by means of iterative techniques.To implement the model in a circuit simulator, it is desirableto have closed-form expressions. In [1] and [15], a closed-form approximation procedure for β1 was presented. However,these procedures have some drawbacks, which we discuss inthe next section, after which we suggest an enhancement to [1]to overcome the drawbacks.

II. DRAWBACKS OF EXISTING APPROXIMATIONS

The approximations described in [1] and [15], as well asour proposed enhancement described in the next section, wereimplemented in Scilab and investigated for accuracy, numericalrobustness, and computation expense in terms of CPU time.The investigation was carried out on an AMD Opteron 2.4-GHzLinux-based PC featuring 16-GB RAM. The free variable(VGD − Δϕ) was swept from −0.34 to 4 V in steps of 0.01 V,and the candidate approximation procedures were executed ateach bias point. The odd value of −0.34 V was chosen because

Manuscript received July 25, 2008; revised November 17, 2008. Currentversion published February 25, 2009. The review of this brief was arrangedby Editor C. Jungemann.

The authors are with the Center for Nanoelectronics, Department of Elec-trical Engineering, Indian Institute of Technology Bombay, Mumbai 400 076,India (e-mail: rrao@ee.iitb.ac.in).

Color versions of one or more of the figures in this brief are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.2011721

TABLE IBENCHMARK RESULTS

Fig. 1. Accuracy of our proposed enhancement to [1]. The trace labeled [1]-Modified denotes the present work. The missing data points for the tracelabeled [1] correspond to an error < 10−14%.

it is the lowest bias point at which the approximations discussedin both [15] and [1] work. Table I summarizes the results (theaccuracy is shown in Fig. 1).

For bias ranges below −0.34 V, the approximation describedin [15] gives a divide-by-zero error. The root cause of thisproblem was diagnosed to be the computation of ζ in [15,eq. 13], which gets calculated as zero when z is very small,which happens when (VGD − Δϕ) is less than about −0.34 V.Another drawback of this approximation is the piecewise com-putation of the Lambert-W function [16]. Such bias-dependentbreak points of a piecewise computation are not desirable in acompact model implementation.

Similarly, for bias ranges below −1.34 V, the approximationdescribed in [1] gives a singularity of log function error. Theroot cause of this problem was diagnosed to be the computationof η0 in [1, eq. 14]. When (VGD − Δϕ) is less than about−1.34 V, the second term in the square root in [1, eq. 13] gets

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530 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

neglected in comparison to the first term, and z1 gets computedas zero.

The numerical robustness was investigated for many geome-tries (Wfin and tox combinations), and the limit points of−0.34 and −1.34 V of the approximations described in [1]and [15], respectively, are found to be quite typical for variousgeometries.

In Table I, the approximation labeled Present work is oursuggested enhancement to the approximation described in [1],in order to overcome its numerical robustness limitation. It isdescribed in the next section.

III. PROPOSED ENHANCEMENT TO [1]

The transcendental equation in question [4] is

f(β1) = 0 =4εφtβ1 tan(β1)

WfinCox+ φfn + 2φt ln

(2β1 sec(β1)

βWfin

)

− (VGS − Δφ). (1)

β1 is a state variable with a value between 0 and π/2, andis the same as β in [4]. The term β in (1) is given by β =√

(qni/2εφt). In (1), Wfin is the silicon thickness, Cox is thegate oxide capacitance per unit area, ε is the permittivity ofsilicon, Φt is the thermal voltage (kT/q), Φfn is the electronquasi-Fermi potential (equals zero and VDS at the source anddrain ends, respectively), q is the electronic charge, and ΔΦis work function difference between the gate electrodes andintrinsic silicon. Equation (1) can also be written as

4εφtβ1 tan(β1)WfinCox

+ 2φt ln

(2√

β21 + β2

1 tan2(β1)βWfin

)

= VGS − Δφ − φfn. (2)

Defining β2 = β1 tan(β1), we get

4εφtβ2

WfinCox+ 2φt ln

(2√

β21 + β2

2

βWfin

)= VGS − Δφ − φfn.

(3)

In (3), the first term in the LHS dominates the second term tosome extent at large values of β1, and the second term (i.e.,the logarithm term) dominates the first term overwhelmingly atsmall values of β1. However, at small values of β1, we haveβ2

1∼= β1 tan β1 = β2. Using this approximation, (3) becomes

4εφtβ2

WfinCox+ 2φt ln

(2√

β2 + β22

βWfin

)= VGS − Δφ − φfn.

(4)

Equation (4) is equivalent to [13, eq. 9]. This can bewritten as

β22 + β2 = u2e−2bβ2 (5)

if we define u = (βWfin/2)e(VGS−Δφ−φfn)/2φt and b =(2ε/WfinCox).

At small values of β2, (5) can be approximated as β2_sm =u2 (neglecting the β2

2 term in the LHS and approximatingthe exponential term in the RHS as one). Similarly, at largevalues of β2, (5) can be approximated as β2

2_lrg = u2e−2bβ2_lrg

(by neglecting the β2 term in the LHS), which can further besimplified as

β2_lrg =W (bu)

b(6)

where W (x) is the Lambert-W function [16] defined as thesolution of WeW = x. We then utilize the following closed-form approximation [17] for the Lambert-W function:

W (x) ∼= 0.04 + 0.665 [1 + 0.0195 · ln(1 + x)] · ln(1 + x).(7)

This has been shown [17] to be valid for x < 500. Using (7) in(6), we get

β2_md∼= 0.04 + 0.665 [1 + 0.0195 · ln(1 + bu)] · ln(1 + bu)

b.

(8)

The suffix _md implies applicability to medium values ofβ2 because the approximation that we have used for theLambert-W function is not applicable for very large valuesof its argument. A plot of β2_sm and β2_md shows that theydiffer in orders of magnitude, with β2_sm < β2_md for smallvalues of β2, and β2_md < β2_sm for medium values of β2.Hence, they can be conveniently combined as β2_sm_md =((β2_sm · β2_md)/(β2_sm + β2_md)). This gives a single-pieceapproximation for β2, which is valid for small and mediumvalues of bu. The notions of small and medium are arbitraryand do not affect the suggested procedure, as will be seen.

Next, considering the root cause analysis stated in Section IIof the limited numerical robustness of the approximation de-scribed in [1], we suggest a different starting guess for z1

(which equals tan(β1) in [1]), than that used in [1, eqs. 12 and13]. It is seen that if the following starting guess is used:

z1 =√

β2_sm_md (9)

then the numerical robustness limitation is overcome, and theaccuracy (for most of the practical bias range in most applica-tions) and the computation expense remain unchanged.

The rest of the procedure remains the same as in [1]. Thejustification for choosing z1 as in (9) is that, at small valuesof β1, it is clear that β2 = β1 tan(β1) ≈ tan2(β1). However,at small and medium values of β1, we have already shownthat β2_sm_md is a good approximation for β2. Extending thisassertion beyond small values of β1 since this is only a startingguess, we can thus say that β2_sm_md ≈ tan2(β1). Therefore,z1 equals

√β2_sm_md.

IV. RESULTS

The channel length Lg , work function difference Δϕ, andmobility μ used in the current/transconductance calculationsand 2-D device simulations are 1 μm, 0 V, and 300 cm2/V · s,respectively. These are the same values as those considered

HARIHARAN et al.: IMPROVEMENT TO THE ROBUSTNESS OF SURFACE POTENTIAL APPROXIMATION FOR MOSFET 531

Fig. 2. Id–Vg at VDS = 50 mV compared with the (symbols) 2-D devicesimulation results. The red, green, and blue traces fall exactly over each other.

Fig. 3. Id–Vg at VDS = 1 V compared with the (symbols) 2-D devicesimulation results. The red, green, and blue traces fall exactly over each other.

in [1]. For a range of values of (VGS − Δϕ − VDS), theoriginal transcendental equation (1) was solved numericallyfor β1. Fig. 1 shows the accuracy of the proposed enhancementwhen plotted over a bias range of −4 to 4 V. Even though thevoltages are not expected to be as high as 4 V at the geometriesconsidered in most applications, it is possible that higher thannormal voltages are encountered in the various internal itera-tions during the solution process in a circuit simulator. Moreimportantly, I/O devices use higher voltages, as do also someof the reliability studies involving circuits. In Fig. 1, the tracelabeled [1] is shown only for VGS − Δϕ − VDS > −1.34 Vbecause of the numerical robustness issue stated earlier. We cansee that the error is comparable to the original approximationfor VGS − Δϕ − VDS < 0.8 V. For bias ranges above that,the accuracy of our suggested enhancement degrades to about10−6%, which is still very small.

Figs. 2–5 show a comparison of current and transconduc-tance with 2-D device simulations using Synopsys SentaurusDevice for three silicon body thicknesses. In these plots, thedrain current model described in [4] was used for the analyticalmodel. Fig. 6 shows the transcapacitances using the analyticalmodel presented in [14]. The curve labels (a), (b), and (c)correspond to calculations of β1 using [1], the present work,and numerical calculations, respectively, and they fall exactlyover each other.

Fig. 4. gm − Vg at VDS = 50 mV compared with the (symbols) 2-D devicesimulation results. The red, green, and blue traces fall exactly over each other.

Fig. 5. gm − Vg at VDS = 1 V compared with the (symbols) 2-D devicesimulation results. The red, green, and blue traces fall exactly over each other.

Fig. 6. Transcapacitances per unit fin height versus VGS at VDS = 1 V,normalized to 2LCox. The symbols are the 2-D device simulation data. Thered, green, and blue traces fall exactly over each other.

V. CONCLUSION

An enhancement of an existing approximation to the solu-tion of a key transcendental equation in symmetric DGFETshas been presented. The enhancement was shown to increasethe numerical robustness of the original approximation whilecausing no loss in computational efficiency.

532 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009

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Venkatnarayan Hariharan (S’03) received theB.Tech. degree in electrical engineering from theIndian Institute of Technology (IIT) Bombay,Mumbai, India, in 1991, the M.S. degree in electri-cal engineering from Santa Clara University, SantaClara, CA, in 2003, and the Ph.D. degree in electricalengineering from IIT Bombay in 2008.

He worked in database software development withTata Motors, Pune, India, the Oracle Corporation,Redwood Shores, CA, and other companies beforeembarking on a career change into semiconductors.

Since 2008, he has been a Device Modeling Engineer with Maxim IntegratedProducts, Sunnyvale, CA. His research interests include compact model devel-opment, device optimization, and TCAD tool development.

Juzer Vasi (M’74–SM’96–F’04) received theB.Tech. degree in electrical engineering from theIndian Institute of Technology (IIT) Bombay,Mumbai, India, in 1969 and the Ph.D. degree fromthe Johns Hopkins University, Baltimore, MD,in 1973.

He was with the Johns Hopkins University andIIT Delhi, before moving to IIT Bombay, in 1981,where he is currently a Professor in the Center forNanoelectronics, Department of Electrical Engineer-ing. His research interests are in the area of CMOS

devices, technology, and design. He has worked on MOS insulators, radiationeffects in MOS devices, degradation and reliability of MOS devices, andmodeling and simulation of MOS devices.

V. Ramgopal Rao (M’98–SM’02) received theM.Tech. degree from the Indian Institute of Technol-ogy (IIT) Bombay, Mumbai, India, in 1991 and theDr. Ingenieur degree from the Faculty of ElectricalEngineering, Universitaet der Bundeswehr, Munich,Germany, in 1997.

During 1997–1998 and again in 2001, he was aVisiting Scholar with the Electrical Engineering De-partment, University of California, Los Angeles. Heis currently a Professor with the Center for Nanoelec-tronics, Department of Electrical Engineering, IIT

Bombay. His areas of interest include physics, technology, and characterizationof silicon CMOS devices for logic and mixed-signal applications, bio-MEMS,and nanoelectronics. He has over 200 publications in these areas in refereedinternational journals and conference proceedings and is the holder of twopatents with eight pending. He is the Chief Investigator for the Centre forNanoelectronics project, IIT Bombay, besides being the Principal Investigatorfor many ongoing sponsored projects funded by various multinational indus-tries and government agencies. He is also a Working Group Member setup bythe Ministry of Communications and Information Technology, Government ofIndia, on Nanotechnology.

Prof. Rao is a fellow of the Indian National Academy of Engineeringand the Institution of Electronics and Telecommunication Engineers (IETE).He received the Shanti Swarup Bhatnagar Prize in Engineering Sciences in2005 for his work on electron devices. He also received the SwarnajayantiFellowship Award for 2003–2004, instituted by the Department of Scienceand Technology, Government of India; the 2007 IBM Faculty award; andthe 2008 “The Materials Research Society of India Superconductivity andMaterials Science Prize.” He is the Editor for the IEEE TRANSACTIONS ON

ELECTRON DEVICES in the CMOS devices and technology area and is aDistinguished Lecturer of the IEEE Electron Devices Society. He was theOrganizing Committee Chair for the 17th International Conference on VLSIDesign and the 14th International Workshop on the Physics of SemiconductorDevices. He serves on the program/organizing committees of various interna-tional conferences including the 2008 International Electron Devices Meeting,the IEEE Asian Solid State Circuits Conference, the 2006 IEEE Conferenceon Nano-Networks, the ACM/IEEE International Symposium on Low PowerElectronics and Design, and the 11th IEEE VLSI Design and Test Symposiumamong others. He was the Chairman of the IEEE AP/ED Bombay Chapterduring 2002–2003, and he currently serves on the executive committee of theIEEE Bombay Section besides being the Vice-Chair and the IEEE Asia-PacificRegions/Chapters Subcommittee.