An Improved Virtual Space Vector Modulation Scheme …download.xuebalib.com/39eXvBGNan2.pdfIEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017 7419 An Improved Virtual

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017 7419

An Improved Virtual Space Vector ModulationScheme for Three-Level ActiveNeutral-Point-Clamped Inverter

Cungang Hu, Member, IEEE, Xinghuo Yu, Fellow, IEEE, Donald Grahame Holmes, Fellow, IEEE,Weixiang Shen, Member, IEEE, Qunjing Wang, Member, IEEE, Fanglin Luo, Senior Member, IEEE,

and Nian Liu, Member, IEEE

Abstract—This paper presents an improved virtual space vectormodulation (IVSVM) scheme for a three-level active neutral-point-clamped (3L-ANPC) inverter to balance neutral-point potential(NP), reduce switching loss, and suppress common mode voltage(CMV). In the IVSVM scheme, an improved virtual medium vec-tor (VMV) is synthesized by the original medium vector and theadjacent two pairs of the small vectors since there are always twopairs of the small vectors in any regions of the new space vectordiagram. The improved VMV provides the flexibility to controlthe NP balancing under any modulation indexes and power fac-tors in one switching cycle while achieving SL reduction and CMVsuppression. This is achieved by the proper selection of two pairsof small vectors in terms of NP charge and the pulse sequence.The experimental platform based on a 3L-ANPC inverter is estab-lished and results obtained to verify the effectiveness of the IVSVMcontrol strategy.

Index Terms—Active neutral-point-clamped, common-modevoltage, neutral-point potential balancing, space vector modula-tion, switching loss (SL).

I. INTRODUCTION

THE multilevel neutral-point-clamped (NPC) inverter hasbeen widely used in power electronics equipment of high-

power and high-voltage applications [1]. However, the unequaldistribution of loss among switches in this inverter limits itsmaximum output power and switching frequency. The activeNPC (ANPC) inverter was introduced to evenly distribute lossesamong switching devices by selecting upper and lower NPC

Manuscript received April 20, 2016; revised July 9, 2016 and September 9,2016; accepted October 17, 2016. Date of publication October 26, 2016; date ofcurrent version May 9, 2017. This work was supported in part by the NationalNatural Science Foundation of China under Grant 51307002. Recommendedfor publication by Associate Editor D. O. Neacsu.

C. Hu, Q. Wang, and F. Luo are with the School of Electrical Engineer-ing and Automation, Anhui University, Hefei, Anhui 230601, China (e-mail:[email protected]; [email protected]; [email protected]).

X. Yu and D. G. Holmes are with the School of Electrical and Computer Engi-neering, Royal Melbourne Institute of Technology University, Melbourne, VIC3000, Australia (e-mail: [email protected]; [email protected]).

W. Shen is with the Electrical Engineering in Faculty of Science, Engineeringand Technology, Swinburne University of Technology, Melbourne, VIC 3122,Australia (e-mail: [email protected]).

N. Liu is with the School of Electrical and Electronic Engineering,North China Electric Power University, Beijing 102206, China (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2016.2621776

paths, leading to a substantial increase in inverter output powerand switching frequency [2], [3].

The main disadvantage of NPC inverters is the variation ofneutral-point potential (NP). The unbalancing of the NP will in-crease harmonics, reduce output power quality, damage switch-ing devices, and increase filter capacitance in power systems[4]. Therefore, NP balancing is essential to the NPC invert-ers. The existing NP control methods can be divided into twogroups. One group of the methods is to add extra hardware cir-cuits, which increases the complexity and cost of the circuit[5], [6]. The other group is based on the pulse width mod-ulation (PWM). Various PWM methods have been proposed,such as carrier-based sinusoidal PWM (SPWM) [7]–[9], spacevector PWM (SVM) [10]–[13], and selective harmonic elimi-nation PWM (SHEPWM) [14]. Compared with the SPWM andSHEPWM, the SVM has many advantages such as small ripple,low noise, and high dc voltage utilization, and can be easilyimplemented in a microcontroller. Due to the above merits, theSVM has attracted more and more attention. It is highly suitablefor the applications of high-voltage and high-efficiency con-verters, photovoltaic grid-connected inverters, and microgridbidirectional converters.

The SVM control strategy for five-level ANPC inverter waspresented to balance the NP [10]. In this strategy, 125 space vec-tors are combined by 96 triangles using a seven-segment vectorsynthesis method. Each triangle is divided into seven categoriesthat have different characteristics of the NP balancing and ev-ery category has its own way to choose vector sequence andcompute vector duration. The SVM-based neutral-point con-troller using the polarity of the output currents was presentedin [11]. This method distributes redundant voltage vectors tomaintain small neutral-point current and therefore control theNP. The main idea of the above two SVM schemes is to se-lect the nearest three vectors (NTV) that are not capable of NPbalancing at high modulation index and low power factor [15].The nearest three virtual vector modulation (VSVM) schemeswere proposed to control the NP [16]–[22], where the virtualvectors are a linear combination of real vectors. They are capa-ble of controlling the NP balancing for any load and modulationindex when the operation of the inverter is in the steady statewith the balanced output three-phase currents, but they cannotreduce switching losses (SL) and suppress the common mode

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7420 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017

Fig. 1. Three-phase 3L-ANPC inverter topology.

voltage (CMV) simultaneously. A SVM method was proposedto balance NP and reduce SL simultaneously only in some re-gions of space vector diagram (SVD) for the NPC inverter in[13]. This is due to the fact that these modulation schemes haveeither one pair of small vectors or no small vector in someregions of the SVD. A VSVM technique to reduce the CMVwas applied to a two-level inverter [22]. It mitigates the CMVby choosing original stationary space vectors to construct a setof virtual space vectors with the lowest instantaneous and zeroaverage CMVs. When this technique is extended to multilevelinverters, it is difficult to implement with heavy computationburden. In [12], there are two small vectors to balance the dc-bus voltage that has the following disadvantages:

1) it can only be used for NP balancing but not for reducingthe SL and suppressing the CMV;

2) it cannot take the influence of different small vectors onthe NP balancing into account;

3) it has a sudden change of switching state that cause highdv/dt;

4) some pulse sequences are not symmetric that increase theSL and output THD of inverters.

In this paper, an improved virtual space vector modulation(IVSVM) scheme is proposed. In this scheme, an improvedvirtual medium vector (VMV) is defined to make two pairs ofsmall vectors in any region of the SVD. Through the properselection of these two pairs of small vectors in terms of NPcharge and pulse sequence, the proposed scheme can maintainNP balancing while reducing the SL and suppressing the CMVfor any modulation indexes and power factors.

The rest of the paper is organized as follows. In Section II,the operation principles of 3L-ANPC inverter controlled by theSVM, the VSVM, and the IVSVM schemes are presented. InSections III, the IVSVM control strategy for NP balancing, SLreduction, and CMV suppression is explained. In Sections IV,the performance of the IVSVM control strategy is analyzed andcompared with the SVM and the VSVM through the experimen-tal platform of a 3L-ANPC inverter, followed by conclusions.

II. THREE-LEVEL ANPC INVERTER AND SPACE VECTOR PWM

A. Principle of Three-Level ANPC Inverter

A 3L-ANPC inverter is shown in Fig. 1. The dc link is sharedby three-phase legs. The voltages of dc-link capacitors: C1 and

TABLE ISWITCHING STATES OF 3L-ANPC INVERTER

Switches

Sx 1 Sx 2 Sx 3 Sx 4 Sx 5 Sx 6 Phase voltage Output state

1 1 0 0 0 1 Ud c /2 P0 1 0 1 1 0 0 OU10 1 0 0 1 0 0 OU21 0 1 0 0 1 0 OL10 0 1 0 0 1 0 OL20 0 1 1 1 0 −Ud c /2 N

C2 , ideally are the half of the dc-link voltage (Udc). Each phaseleg is composed of six switches (Sx1 , Sx2 , Sx3 , Sx4 , Sx5 , andSx6), where x represents the three phases a, b, and c, respectively.It can generate three different voltage levels, namely Udc/2, 0,and −Udc/2, corresponding to three switching states: P, O, andN. The six switching states of the 3L-ANPC inverter are shownin Table I. In this 3L-ANPC inverter topology, the current pathof the P state and the N state is the similar to that of the 3L-NPCinverter topology. However, there are two additional currentpaths connecting the output node to the neutral point by turningON/OFF switches Sx2 , Sx3 , Sx5 , and Sx6 . These two currentpaths of the O state can be realized by the switches: either Sx2and Sx5 or Sx3 and Sx6 [2]. This provides the four redundantswitching states, namely four zero-level O states: OU1, OU2,OL1, and OL2. When the zero-level O state is OU1 or OU2,the switches Sx2 and Sx5 are turned ON and the switches Sx1 ,Sx3 , and Sx6 are turned OFF. The difference between OU1 andOU2 lies in the switching state of Sx4 . When the zero-levelO state is OL1 or OL2, the switches Sx3 and Sx6 are turnedON and the switches Sx2 , Sx4 , and Sx5 are turned OFF. Thedifference between OL1 and OL2 lies in the switching state ofSx1 . Therefore, these four zero-level O states can be chosento reduce the SL by the appropriate arrangement of switchingbetween different switching states.

B. Space Vector PWM

The SVD of the conventional 3L-ANPC inverter and its sec-tion A are shown in Fig. 2, where the SVD is divided into sixsections, A to F, respectively. There are 27 space vectors, in-cluding large, medium, small and zero vectors. Take section Aas an example. It is divided into the four triangular regions, A0to A3, as shown in Fig. 2(b), where θ is the azimuth angle of thereference vector Vref .

The NP balancing is essential for the proper function of a3L-ANPC inverter. Large vectors do not affect the NP balanc-ing because they connect phase currents to either positive ornegative dc link. Zero vectors do not affect the NP balancingeither. Medium vectors connect one of phase currents to theNP and make the NP dependent on loading conditions. Thus,medium vectors will affect NP balancing. Small vectors comein pairs. Each pair of small vectors can be divided into a positivesmall vector and a negative small vector. A small positive vectorconnects one-phase current to neutral point and a small nega-tive vector connects two-phase currents to neutral point. Thus,small vectors will affect NP balancing too. The influences of

HU et al.: IMPROVED VIRTUAL SPACE VECTOR MODULATION SCHEME FOR 3L-ANPC INVERTER 7421

Fig. 2. (a) SVD of conventional 3L inverter and (b) section A.

TABLE IIINFLUENCES OF SMALL AND MEDIUM VECTORS ON NP

Positive smallvectors

uN P (t) Negative smallvectors

uN P (t) Medium vectors uN P (t)

ONN ↑ POO ↓ PON ↑PPO ↑ OON ↓ OPN ↑NON ↑ OPO ↓ NPO ↑OPP ↑ NOO ↓ NOP ↑NNO ↑ OOP ↓ ONP ↑POP ↑ ONO ↓ PNO ↑

medium vectors and small vectors on the NP balancing are dif-ferent. The medium vectors have stronger impact on the NPcharge at high modulation index and low power factor, whereassmall vectors coming in pairs have weaker impact on the NPcharge.

In Fig. 1, it is assumed that the current is positive when phasecurrent ix(t) (x = a, b, or c), flows from the inverter to the load,where uNP(t) is the NP voltage, and the influences of mediumvectors and small vectors on the NP are shown in Table II. Itcan be seen that the influences of a positive small vector and anegative one in a pair on the NP are opposite. Therefore, the NP

Fig. 3. Boundary of NP balancing using conventional SVM.

balancing schemes relies on the manipulation of small vectorsin a pair.

In the conventional SVM scheme, according to the NTVsynthesis rules, the reference vector Vref is generated by thethree nearest vectors in its vertexes. Mathematically, it isexpressed as {

Vref = d0 · V0 + d1 · V1 + d2 · V2

1 = d0 + d1 + d2(1)

where d0 , d1 , and d2 are the duty cycles of these three nearestvectors V0 , V1 , and V2 , respectively.

According to the NP balancing model in the SVM scheme,the boundary surface of the NP balancing under different powerfactors and modulation indexes for one section (e.g., sectionA) is shown in Fig. 3, where the NP cannot be balanced in theregion above the surface and can be balanced in the region underthe surface.

In the SVD of the conventional 3L-ANPC inverter, as shownin Fig. 2(a), the white-colored star-shaped region includes twopairs of small vectors in its vertexes. One pair of small vectorscan be selected for the NP balancing control and the other pairof small vectors can be selected for other control objectives,such as the SL reduction or the CMV suppression or both; thegrey-colored region includes only one pair of small vectors in itsvertexes. The selection of this pair of small vectors only focuseson the NP balancing, and no redundant small vector can be usedfor other control objectives.

C. Virtual Space Vector PWM

In order to solve the problem that the NP cannot be com-pletely balanced in some regions, the VSVM control strategy isproposed in [16]–[21]. The virtual space vectors are defined asa linear combination of the real vectors corresponding to certainswitching states.

Take section A of the SVD in Fig. 2(b) as an example. AVMV VVM0 is defined as a linear combination of the originalmedium vector VPON and one pair of the small vectors VONNand VPPO [16], [17]

VVM0 = rA0VPON + rA1VONN + rA2VPPO (2)


Fig. 4. Section A with virtual space vectors.

where ra0 , rA1 , rA2 ∈ [0, 1] and rA0 + rA1 + rA2 = 1. WhenrA0 = rA1 = rA2 = 1/3, section A can be redrawn in Fig. 4.

The neutral-point current generated by the VMV VVM0 is

iNP =13(ia + ib + ic). (3)

In [16] and [17], these three-phase currents (ia , ib , and ic ) areassumed to be constant in one sampling period and the neutral-point current iNP is zero. In the steady state, the VMV VVM0does not generate the NP offset. Therefore, the NP balancingcan be controlled by adjusting the duration of the small vectorin any region. For the triangle regions A1 and A3, in Fig. 4, onepair of small vector can be used to dynamically control the NPbalancing. For the triangle region A4, in Fig. 4, there is no smallvector for the NP balancing.

In the following section, the IVSVM scheme for a 3L-ANPCinverter is proposed. In the IVSVM scheme, there are two pairsof small vectors in any region of the SVD. Hence, both the NPbalancing control and other control objectives can be realizedsimultaneously.

D. Improved VMV

An improved VMV is synthesized by the original mediumvector and the adjacent two pairs of the small vectors. Its purposeis to reduce the impact of the original medium vector on theNP and to make two pairs of small vectors in its vertexes inany region of the SVD. Due to the sixfold symmetry of theSVD, only section A is used to explain the working principleof the IVSVM scheme. The improved VMV is defined as aweighted linear combination of the vectors corresponding tocertain switching states as follows:

VNM0 = kA0VM0 + kA1VS0 + kA2VS1 (4)

where kA0 , kA1 , kA2 ∈ [0, 1] and kA0 + kA1 + kA2 = 1. It canbe seen from (4) that in the improved VMV VNM0 in-cludes two pairs of the small vectors VS0 (POO/ ONN) andVS1 (PPO/OON). The adjustment of the duty cycles of kA0 ,

kA1 , kA2 and thus the duration of medium and small vectorscan be used for the NP balancing and other control objectives.For example, when kA0 = kA1 = kA2 = 1/3, the new SVDfor the IVSVM scheme is shown in Fig. 5, each section of thenew SVD is divided into five triangle regions.

Fig. 5. New SVD for 3L-ANPC inverter.

TABLE IIISELECTION OF SPACE VECTORS IN NSVD IN SECTION A

Triangle Selected vectors Corresponding basic vectors

A0 VZ , VS 0 , VS 1 PPP, OOO, NNN, POO, ONN, PPO, OONA1 VS 0 , VN M 0 , VL 0 POO, ONN, PON, PPO, OON, PNNA2 VS 0 , VN M 0 , VS 1 POO, ONN, PON, PPO, OONA3 VS 1 , VN M 0 , VL 1 PPO, OON, PON,POO, ONN, PPNA4 VL 0 , VN M 0 , VL 1 PNN, PON, POO, ONN, PPO, OON, PPN

In each switching cycle, a set of space vectors need to beselected to synthesize the reference vector. Take section A inFig. 5 as an example. The vectors of each triangle in the newSVD are shown in Table III. It can be seen that there are twopairs of the small vectors in its vertexes in any region of thenew SVD. Therefore, the NP can be balanced by adjusting theduration of the positive and negative small vectors under anymodulation indexes and power factors.

III. IMPROVED VIRTUAL SPACE VECTOR MODULATION

SCHEME FOR 3L-ANPC INVERTER

As mentioned earlier, the IVSVM scheme includes two pairsof small vectors in any region of the new SVD. One pair of smallvectors must be selected to control the NP balancing since the NPbalancing is critical for a 3L-ANPC inverter while the other pairof the small vectors can be selected to reduce the SL and suppressthe CMV. In the following, the proposed control strategy basedon the IVSVM is analyzed and compared with those based on theSVM and the VSVM to show the effectiveness of the IVSVM.

A. Control Strategy for SL reduction

The SL mainly depends on the current in the switch and thefrequency to turn ON/OFF switches [23], [24]. In this study,the control strategy is to avoid switching the device of thelargest current phase by selecting the redundant small vectorsin the preferred pulse sequences. Take the triangle region A0 insection A of the new SVD as an example. When uNP(t) > 0 andic(t) > 0, the small vector OON is used for the NP balancing,


Fig. 6 Pulse sequences for SL reduction in triangle region A0.

whereas the other pair of the small vectors VS0 (POO/ ONN) isused for the SL reduction. There are three possible pulse se-quences including OON, as shown in Fig. 6. The total switchingtimes of three pulse sequences are equal. Where TSW is theswitching period, the control strategy of the SL reduction isshown as follows:

1) when the current in phase a is maximum, the first pulsesequence should be adopted, as shown in Fig. 6(a);

2) when the current in phase b is maximum, the second pulsesequence should be adopted, as shown in Fig. 6(b);

3) when the current in phase c is maximum, the third pulsesequence should be adopted, as shown in Fig. 6(c).

The total loss of the switching devices can be calculated basedon the output power of the inverter, its switching duration, mod-ulation index, power factor, switching frequency and switchingdevice parameters [23], [24], and the corresponding formulaeto calculate SL are included in Appendix. The switching device(IGBT) parameters from Infineon manual are used in this calcu-lation [25]. The 3L-ANPC inverter, which has the power ratingof 300 kVA with each phase leg sharing 100 kVA power and theswitching frequency of 5 kHz, is used in the simulation, withthe dc link. Fig. 7 shows the comparison of the loss distributionof one-phase leg for three SVMs at the unit power factor undertwo different modulation indexes of 1.0 and 0.6, respectively.The modulation index of 0.6 is chosen because its correspond-ing reference vector can cover more areas, such as A1, A2, andA3 of section A in Fig. 2(b). Fig. 8 shows the comparison of thesystem loss for three SVMs at the modulation index m = 1.0under different power factors. As can be seen from Figs. 7 and8, respectively, that the IVSVM has the minimal loss distribu-tion of one-phase leg and the total system loss among the threeSVMs.

B. Control Strategy for CMV Suppression

The 3L-ANPC inverter generates the CMV. For the motorapplication, the CMV can cause the shaft voltage between ro-tor and frame, and between rotor and stator winding, resultingin an excessive bearing current [26], [27]. This current maylead to premature failures of bearing and significant CMV. This

Fig. 7. Comparison of loss distribution of one phase leg for three SVMs atunit power factor under two modulation indexes (a) m = 0.6 and (b) m = 1.0.

Fig. 8. Comparison of system loss for three SVMs at m = 1.0 under differentpower factors.

CMV can cause electromagnetic interference emission. It canalso cause leakage current to flow into the ground via electro-static coupling that may trip ground protection relays falsely[28]. The CMV is calculated by

UCMV = (Uao + Ubo + Uco)/3 (5)


TABLE IVVECTORS AND AMPLITUDES OF CMVS FOR THREE-LEVEL ANPC INVERTER

Space vectors |UC M V |

Large vectors PNN,PPN,NPN,NPP,NNP,PNP Ud c /6Medium vectors PON,OPN,NPO,NOP,ONP,PNO 0Positive small vectors ONN,PPO,NON,OPP,NNO,POP Ud c /3Negative small vectors POO,OON,OPO,NOO,OOP,ONO Ud c /6Zero vector I OOO 0Zero vector II PPP,NNN Ud c /2

Fig. 9. Pulse sequences for CMV suppression in triangle region A0.

Fig. 10. Pulse sequence for CMV suppression in triangle region A2.

where Uao , Ubo , and Uco are three-phase output voltages ofa 3L-ANPC inverter. The CMV calculated by (5) with all thespace vectors are shown in Table IV. When the zero vectorsPPP, NNN, and positive small vectors are used, the amplitudeof the CMV is large. If the other space vectors are chosen tosynthesize the reference vector, the amplitude of the CMV canbe suppressed within the range of Udc/6.

Take section A of the new SVD as an example. In the triangleregion A0. When uNP(t) < 0 and ic(t) > 0, the small vectorPPO is used for the NP balancing while the other pair of thesmall vectors VS0 (POO/ ONN) is used for the CMV suppres-sion. Fig. 9 shows the two possible pulse sequences includingONN. The total switching times of the two pulse sequences areequal. Since the CMV output with the OOO is smaller thanthat with PPP, the CMV output can be reduced by selectingthe first pulse sequence in Fig. 9(a). In the triangle region A2,Fig. 10 shows the two possible pulse sequences including POO.The total switching times of two pulse sequences are equal, butthe CMV output of negative small vector OON is smaller thanthat of positive small vector PPO, thus the CMV output canbe reduced selecting the second pulse sequence in Fig. 10(b).Therefore, the negative small vectors and zero vector OOO areused to suppress the CMV for the white colored regions in

Fig. 11. Pulse sequences for CMV suppression using IVSVM in triangleregion A0.

Fig. 12. Pulse sequences for CMV suppression using IVSVM in triangleregion A1.

Fig. 5. The negative small vectors are only used to reduce theCMV for the grey colored regions in Fig. 5.

C. Control Strategy Implementation

For a 3L-ANPC inverter, the NP balancing is the top priorityand the SL reduction has higher priority than CMV suppression,


TABLE V3L-ANPC INVERTER SPECIFICATIONS

DC-link voltage 200 V

DC-link capacitors 4700 μFSwitching devices Infineon IKP40N65F5 IGBTSwitching frequency 5k HzFundamental frequency 50 HzDead time 4 μs

Fig. 13. Experimental platform of 3L-ANPC inverter.

particularly for the high voltage and power inverter. In this pa-per, the priority order of the control objectives is: the NP balanc-ing, the SL reduction, and the CMV suppression. As shown inFig. 5, there are two pairs of small vectors in any region ofthe new SVD. One pair of the small vectors to control the NPbalancing is selected based on the charge [13]

Q = ixd(VSi)TSW (6)

where, VSi is the small vector of synthetic reference vector, andix (x = a,b,c) is the corresponding phase current of the smallvector VSi , d(VSi) is the duty cycle of the small vector VSi , andTsw is the switching period.

The triangle region A2 in Fig. 4 can be used an example. Thereference vector Vref is synthesized by the small vectors VS0 andVS1 and the improved VMV VNM0 . The corresponding duty cy-cles are d(VS0), d(VS1), and d(VNM0), respectively. Accordingto (1), d(VS0), d(VS1), and d(VNM0) can be calculated by{

Vref = d(VS0) · VS0 + d(VS1) · VS1 + d(VNM0) · VNM0

1 = d(VS0) + d(VS1) + d(VNM0)(7)

then, (4) and (6) can be used to calculate the charges caused bythe small vectors VS0 and VS1 as follows:

Q(VS0) = ia [d(VS0) + kA1d(VNM0)]TSW (8)

Q(VS1) = ic [d(VS1) + ka2d(VNM0)]TSW . (9)

The small vector with the large charge is selected for the NPbalancing and the other small vector is used to reduce the SL andthe CMV. The triangle region A0 in Fig. 4 can be used as anotherexample. There are two small vectors VS0 and VS1 . If Q(VS0)is larger than Q(VS1), then VS0 has stronger influence on the

Fig. 14. Simulation results under SVM (m = 0.6, R = 33 Ω): (a) Line-to-linevoltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1 andC2, and (d) CMV.

NP than VS1 . The pair of the small vectors VS0(POO/ ONN) iskept for the NP balancing, and the other pair of the small vectorVS1(PPO/ OON) is selected for the SL reduction and the CMVsuppression. When the phase current is positive and the NP islarger than the reference voltage, POO is selected to control theNP. In order to reduce dv/dt, the switching between P and N


Fig. 15. Experimental results under SVM (m = 0.6, R = 33 Ω): (a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1and C2, and (d) CMV.

states should be avoided when the pulse sequences are selected.All pulse sequences should be symmetric which can reducethe SL and output THD of inverters. There are three possiblepulse sequences including POO, as shown in Fig. 11. The totalswitching times of three pulse sequences are equal. The controlstrategies using the IVSVM are shown as follows:

1) In the first pulse sequence, as shown in Fig. 11(a), thereis no switching in phase a. Therefore, when the current inphase a is maximum, the first pulse sequence should beadopted.

2) In the second pulse sequence, as shown in Fig. 11(b), thereis no switching in phase b. The zero vector OOO and thesmall vector OON VS1 can be used to suppress the CMV.Therefore, when the current in phase b is maximum, thesecond pulse sequence should be adopted.

3) In the third pulse sequence, as shown in Fig. 11(c), thereis no switching in phase c. The zero vector OOO can be

Fig. 16. Simulation results under VSVM (m = 0.6, R = 33 Ω): (a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1and C2, and (d) CMV.

used to suppress the CMV. Therefore, when the current inphase b is maximum, the third pulse sequence should beadopted.

The triangle region A1 in Fig. 4 is the third example. Thereis one pair of the small vectors VS0 and VS1 . If Q(VS1) is largerthan Q(VS0), then VS1 has stronger influence on the NP than


VS0 . The small vector VS1 (PPO/OON) is kept for the NPbalancing, and the pair of the small vector VS0 (POO/ ONN)is selected for the SL reduction and the CMV suppression.When the phase current is positive and the NP is smallerthan the reference voltage, PPO is selected to control the NP.Fig. 12 shows three possible pulse sequences including PPO.The first pulse sequence in Fig. 12(a) is obtained under the con-ventional SVM. The second pulse sequence in Fig. 12(b) is ob-tained under the VSVM [16], [17]. The third pulse sequence inFig. 12(c) is obtained under the IVSVM when the current inphase a is maximum. The comparison of the switching timesof these three pulse sequences indicates that the IVSVM hasthe smallest number of switching times in total and there is noswitching in phase a. Therefore, the SL reduction is achievedeffectively. At the same time, the negative small vector POO isselected as the small vector VS0 , the CMV is smaller than thepositive small vector ONN.

Thus, the IVSVM can control the NP balancing, reduce theSL, and suppress the CMV more effectively than the conven-tional SVM and the VSVM.

IV. SIMULATION AND EXPERIMENTAL VERIFICATION

The proposed IVSVM is studied experimentally under twodifferent modulation indexes and load conditions. Its simulationand experimental results are compared with those of conven-tional SVM and the VSVM schemes [16], [17].

A. Simulation and Experimental Platform

The simulation is conducted on the model of a three-phase3L-ANPC inverter built on MATLAB/Simulink. The proposedcontrol strategy is verified by an experimental platform of a3L-ANPC inverter. The parameter settings of the experimentsare shown in Table V. The hardware implementation of the3L-ANPC inverter is shown in Fig. 13.

The control board consists of a TMS320F28335 DSP and anEPM1270T144I5N CPLD. The DSP is employed to producethe triggering gate signals. The CPLD is utilized to produce adead time between the complementary switching signals andduplicate the PWM signals. The initial voltages of C1 and C2are 150 and 50 V, respectively.

B. Simulation and Experimental Results

To verify the effectiveness of the proposed control strategy,three SVM control strategies are tested under two modulationindexes (m) m = 1.0 and m = 0.6 in this study. The modula-tion indexes 0.6 and 1 can cover different sectors, which arethe representative of other modulation indexes. In the first case,the modulation index is 0.6 and the resistive load (R) is 33 Ω.For the SVM and the VSVM, the simulation and testing re-sults for the line-to-line voltage, the voltages of C1 and C2 andthe CMV are shown in Figs. 14–17, respectively. The simula-tion and testing results for the IVSVM are shown in Figs. 18and 19.

From the simulation and experimental results, it can be seenthat the NP of the three SVM control strategies can be effectively

Fig. 17. Experimental results under VSVM (m = 0.6, R = 33 Ω): (a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1and C2, and (d) CMV.

controlled at the modulation index of 0.6 and the unity powerfactor. However, the amplitudes of CMVs are different underthree SVMs. The CMVs in the output of the inverter have thedominated components of Udc/3 under conventional SVM andVSVM control schemes and the dominated component of Udc /6under the improved VSVM scheme. Thus, the improved VSVMwith the CMV suppression produces lower average CMV inthe output of the inverter than the SVM and VSVM. Due todifferences between the models of the components and realcomponents, the peak values of CMVs in the experiments showsome small discrepancies from those in simulation.

To reduce the SL of the inverters in industrial applications,the switching frequency is usually chosen below 20 kHz forIGBTs. As three-level topology is mainly used in high-powerinverters, the switching frequency of 2–8 kHz is used for theIGBT. For example, when the power is 1 MW, the switching


Fig. 18. Simulation results under IVSVM (m = 0.6, R = 33 Ω): (a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1and C2, and (d) CMV.

frequency is generally 2–3 kHz, when the power is 100 kW, theswitching frequency is generally 3–8 kHz. However, increasingthe switching frequency can effectively reduce THD. Accordingto the rule of thumb, the switching frequency is taken to be5 kHz in this study. Thus, it can be seen that the harmonicsare multiples of the switching frequency of 5 kHz, such as 10,

Fig. 19. Experimental results under IVSVM (m = 0.6, R = 33 Ω): (a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor voltages of C1and C2, and (d) CMV.

15, and 20 kHz. After the output filter, the simulation results ofTHD under the SVM, VSVM, and IVSVM are 2.71%, 3.13%,and 2.93%, respectively. The comparison results of line-to-linevoltage spectrums for three SVMs show that the THD of theproposed IVSVM is smaller than that of the VSVM but higherthan that of the conventional SVM. This is because the proposedIVSVM and the VSVM are not satisfied with the NTV synthesismethod which leads to the increase of the THD.

In the second case, the modulation index of 1.0 and the induc-tive load of R/L (33 Ω/4 mH) are selected. The testing resultsare shown in Figs. 20–22. As can be seen from experimentalresults, there is a voltage difference between two dc capaci-tors under the SVM and the VSVM, which indicates that NPis unbalanced. But, the voltages of the two dc capacitors underthe IVSVM converge to the same voltage, which indicates thatthe IVSVM scheme can effectively control the NP balancing.


Fig. 20. Experimental results under SVM (m = 1, R/L = 33 Ω/4 mH):(a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor volt-ages of C1 and C2 (d) CMV, and (e) leakage current.

The inverter based on the improved VSVM has smaller leakagecurrent than the inverters based on the SVM and VSVM due toits smaller CMV.

To verify the effectiveness of the IVSVM for the SL reduc-tion, the efficiencies of the inverter under the SVM, VSVM, andIVSVM are calculated using the data obtained from a power

Fig. 21. Experimental results under VSVM (m = 1, R/L = 33 Ω/4 mH):(a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor volt-ages of C1 and C2, (d) CMV, and (e) leakage current.

meter in the experimental platform, they are, respectively,95.75%, 95.13%, and 96.37% at the modulation index of0.6 and 96.32%, 95.64%, and 96.87% at the modula-tion index of 1. The thermal images are taken by FlukeTi400 to demonstrate the temperature distribution of thecircuit board for a single-phase leg under three SVMs.


Fig. 22. Experimental results under IVSVM (m = 1, R/L = 33 Ω/4 mH):(a) Line-to-line voltage, (b) spectrum of line-to-line voltage, (c) capacitor volt-ages of C1 and C2, (d) CMV, and (e) leakage current.

Fig. 23 shows the results under the modulation indexm = 1 and the resistive load R = 33 Ω, whereas Fig. 24 showsthe results under the modulation index m = 0.6 and the inductiveload R/L = 33 Ω/4 mH. It can be seen that the temperatureof the switches under the SVM and the VSVM is higher thanthat of the switches under the IVSVM regardless of the modu-lation indexes and load types. Take a 3L-ANPC inverter under

Fig. 23. Thermal imaging of circuit board for a single phase leg (m = 0.6,R = 33 Ω): (a) SVM, (b) VSVM, and (c) IVSVM.

Fig. 24. Thermal imaging of circuit board for a single phase leg (m = 1,R/L = 33 Ω/4 mH): (a) SVM, (b) VSVM, and (c) IVSVM.

the resistive load as an example, the respective temperatures ofthe switch S1 under both the SVM and the VSVM are 44.7 °C[see Fig. 23(a)] and 47.1 °C [see Fig. 23(b)], whereas the tem-perature of the switch S1 under the IVSVM is 42.0 °C [seeFig. 23(c)]. These experimental results show that the proposedcontrol strategy is effective in the SL reduction. In addition, theconduction times and switching frequencies of S5 and S6 areless than those of S1–S4 in each fundamental period due to thecharacteristics of ANPC topology, the temperatures of S5 andS6 are lower than those of S1–S4, which are also shown in Figs.23 and 24, respectively.

V. CONCLUSION

This paper proposes an IVSVM scheme for a 3L-ANPC in-verter. The key of the proposed scheme is that an improvedVMV makes all regions in the new SVD to contain two pairsof small vectors. The simultaneous implementation of NP bal-ancing, SL reduction, and CMV suppression in one switching


cycle are achieved by selecting two pairs of small vectors basedon the NP charge and the pulse sequence, leading to betteroutput power quality and electromagnetic compatibility of theinverter. Also, the pulse sequence order is carefully chosen toavoid sudden change of switching states, which further reducesthe SL and improves the efficiency of the inverter and the servicelife of switching devices. The results of the model simulationand experimental prototype of a 3L-ANPC inverter demonstratethat the inverter with the proposed control strategy has higherefficiency than those with other conventional space vector mod-ulation control schemes. This IVSVM scheme can also applyfor all three-level NPC inverters.

APPENDIX

A. Loss of IGBT Module

An IGBT module is widely used in the converters for high-voltage and high-power applications, so the IGBT module isselected as the switching devices for the 3L-ANPC inverterin this study. The module is composed of an IGBT and anantiparallel freewheeling diode (D). In the following, the SL ofthe switching devices are explained and their loss calculation isintroduced [23], [24].

First, the total loss of IGBT includes conduction loss and SL.Its conduction loss can be expressed as

Pcond,T = v0,T IT + rT IT2 (A1)

where, IT is the current flowing through IGBT, v0,T and rT arethe initial saturation voltage drop and on-resistance of IGBT atambient temperature T, respectively. Its SL can be expressed as

Esw ,T = (Asw ,T IT2 + Bsw ,T IT + Csw ,T )

∗(

Uce

Ubase

)D sw , T(

T

Tbase

)k sw , T

(A2)

where Asw ,T , Bsw ,T , and Csw ,T are the parameters obtainedby the quadratic fitting of the SL to the current. Uce is thereal voltage across the switch devices, T is ambient tempera-ture of IGBT. Ubase and Tbase are the reference voltage andtemperature, respectively. Dsw ,T and ksw ,T are the voltage andtemperature correction coefficients, respectively. Thus, the totalloss of IGBT is

PT = Esw ,T + Pcond,T . (A3)

Second, the total loss of D includes conduction loss and re-verse recovery loss. Its conduction loss can be expressed as

Pcond,D = v0,D ID + rD ID2 (A4)

where, ID is the current flowing through D, v0,D and rD arethe initial saturation voltage drop and on-state resistance of Dat ambient temperature, respectively.

The conduction loss of D is very small, the main SL of D isthe reverse recovery loss Erec,D which can be calculated by

Erec,D = (Arec,D ID2 + Brec,D ID + Crec,D )

∗(

Uce

Ubase

)D r e c , D(

T

Tbase

)k r e c , D

(A5)

where, Arec,D , Brec,D , and Crec,D are the parameters of D ob-tained by the quadratic fitting of the SL to the current. Drec,D andkrec,D are the voltage and temperature correction coefficients ofD, respectively. Thus, the total loss of D can be expressed as

PD = Erec,D + Pcond,D . (A6)

Consequently, the total loss of IGBT module including IGBTand D can be expressed as

PSi= PT i + PDi. (A7)

B. Loss of Inverter

Due to the symmetry between the upper and lower IGBTsof each leg in 3L-ANPC inverter, only the loss of three upperIGBT modules has been analyzed.

It is assumed that the OU1 is taken as a zero-level O state,the loss of the IGBT modules are analyzed in details under theswitching sequence of phase A shown in Fig. 6(b). Suppose thatthe load current of phase A is

ia (t) = Im sin (ωt − ϕ) (A8)

where, ϕ is the phase angle of load.According to the Table I, within a switching period TSW ,

there are the conduction losses in Sa1 and Sa2 when the outputstate of the inverter is P and Sa2 and Sa5 when the output stateis OU1. Under these states, the currents flowing through Ta1 ,Ta2 , and Ta5 can be, respectively, expressed as

ITa 1 (t) =

{ia (t) , if (ia (t)> 0 and the output state is P)

0, else

(A9)

ITa 2 (t) ={ia (t) , if (ia (t)> 0 and the output state is P or OU1)

0, else

(A10)

ITa 5 (t) ={ia (t) , if (ia (t)< 0 and the output state is OU1)

0, else

(A11)

and the current flowing through Da1 , Da2 , and Da5 can be,respectively, expressed as

IDa 1 (t) ={ia (t) , if (ia (t) < 0 and the output state is P)

0, else(A12)

IDa 2 (t) ={ia (t) , if (ia (t) < 0 and the output state is P or OU1)

0, else

(A13)


IDa 5 (t) ={ia (t) , if (ia (t) > 0 and the output state is OU1)

0, else.

(A14)

The conduction loss of three IGBTs can be, respectively,calculated as

Pcond,Ta 1 =1

Tsw

∫ T sw

0(v0,T + rT ITa 1 (t))ITa 1 (t) dt (A15)

Pcond,Ta 2 =1

Tsw

∫ T sw


Pcond,Ta 5 =1

Tsw

∫ T sw


and the conduction loss of three diodes can be, respectively,calculated as

Pcond,Da 1 =1

Tsw

∫ T sw

0(v0,D + rD IDa 1 (t))IDa 1 (t) dt

(A18)

Pcond,Da 2 =1

Tsw

∫ T sw

0(v0,D + rD IDa 2 (t))IDa 2 (t) dt

(A19)

Pcond,Da 5 =1

Tsw

∫ T sw

0(v0,D + rD IDa 5 (t))IDa 5 (t) dt.

(A20)

During the commutation between P and OU1, the SL of Sa2equals to zero since Sa2 has kept on-state; Sa1 and Sa5 has turnedON and OFF for one time. Thus, the SL of three IGBTs and threefreewheeling diodes can be, respectively, expressed as

Esw , Ta 1 = (Asw , T ITa 12 (t) + Bsw ,T ITa 1 (t) + Csw ,T )

∗(

Uce

Ubase

)D sw , T(

T

Tbase

)k sw , T

(A21)

Esw ,Ta 2 = 0 (A22)

Esw ,Ta 5 = (Asw ,T ITa 52 (t) + Bsw ,T ITa 5 (t) + Csw ,T )

∗(

Uce

Ubase

)D sw , T(

T

Tbase

)k sw , T

(A23)

Erec,Da 1 = (Arec,D IDa 12 (t) + Brec,D IDa 1 (t) + Crec,D )

∗(

Uce

Ubase

)D r e c , D(

T

Tbase

)k r e c , D

(A24)

Erec,Da 2 = 0 (A25)

Erec,Da 5 = (Arec,D IDa 52 (t) + Brec,D IDa 5 (t) + Crec,D )

∗(

Uce

Ubase

)D r e c , D(

T

Tbase

)k r e c , D

. (A26)

Thus, according to (A7), the total loss of the three IGBTmodules at the upper legs can be obtained. Similarly, the total

loss of the three IGBT modules at the lower legs can be obtained.As a result, the total loss of the inverter is the summation of thetotal loss of three IGBT modules in the upper and lower legs.

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Cungang Hu (M’13) received the B.S. degree in elec-trical engineering and automation from the ElectronicEngineering Institute, Hefei, China, in 2001, the M.S.degree in detection technique and automatic deviceform Hefei University of Technology, Hefei, China,in 2008, and the Ph.D. degree in power electronicsand electric drives from Hefei University of Technol-ogy, Hefei, China, in 2008.

From 2004 to 2013, he was with Hefei Universityof Technology, China. Since 2013, he has been an As-sociate Professor at Anhui University, Hefei, China

and a Distinguished Professor at Provincial Collaborative Innovation Center ofIndustrial Energy-saving and Power Quality Control, Anhui University, China,and he serves as a Research Fellow in the National Engineering Laboratory ofEnergy-saving Motor and Control Technique, Anhui University, China, PowerQuality Engineering Research Center of China Ministry of Education, AnhuiUniversity, and Energy-saving Research Institute, Hefei University of Technol-ogy, Hefei, China. His research interests include multilevel converter technol-ogy, photovoltaic power generation technology, power quality, and micro grid.

Dr. Hu is the Technical Program Committee Chairman of the 11th IEEEConference on Industrial Electronics and Applications and the General Chair-man 12th IEEE Conference on Industrial Electronics and Applications.

Xinghuo Yu (M’92–SM’98–F’08) received B.Eng.and M.Eng. degrees in electrical engineering fromthe University of Science and Technology of China,Hefei, China, in 1982 and 1984, respectively, andPh.D. degree in control science and engineering fromSoutheast University, Nanjing, China, in 1988.

He is and Associate Deputy Vice-Chancellorand a Distinguished Professor of RMIT Univer-sity (Royal Melbourne Institute of Technology),Melbourne, Australia. His research interests includevariable structure and nonlinear control, complex and

intelligent systems, and smart energy systems.Dr. Yu served/is serving as an Associate Editor in the IEEE TRANSACTIONS

ON AUTOMATIC CONTROL, the IEEE TRANSACTIONS ON INDUSTRIAL ELEC-TRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, and the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS – PART I. He is the President-Elect(2016–2017) of the IEEE Industrial Electronics Society. He received a numberof awards and honors for his contributions, including 2013 Dr.-Ing. EugeneMittelmann Achievement Award of the IEEE Industrial Electronics Society andthe 2012 IEEE Industrial Electronics Magazine Best Paper Award.

Donald Grahame Holmes (M’88–SM’03–F’13) re-ceived the B.S. and M.S. degrees in power systemsengineering from the University of Melbourne, Mel-bourne, Australia, in 1974 and 1979, respectively,and the Ph.D. degree in PWM theory for power elec-tronic converters from Monash University, Clayton,Australia, in 1998.

In 1984, he joined Monash University, Clay-ton, Australia, where he established and directed thePower Electronics Group for more than 25 years.In 2010, he moved to (Royal Melbourne Institute of

Technology) RMIT University, Melbourne, Australia to take up a professorialchair in Smart Energy. He has a strong commitment and interest in the con-trol and operation of electrical power converters His research interests includefundamental modulation theory and its application to the operation of energyconversion systems, current regulators for drive systems, and PWM rectifiers,active filter systems for quality of supply improvement, resonant converters,current-source inverters for drive systems, and multilevel converters. He hasmade a significant contribution to the understanding of PWM theory throughhis publications and has developed close ties with the international researchcommunity in the area. He has published more than 200 papers at internationalconferences and in professional journals, and regularly reviews papers for allmajor IEEE transactions in his area. He has also coauthored a major refer-ence textbook on PWM theory with Prof. Thomas Lipo of the University ofWisconsin-Madison, Madison, WI, USA.

Prof. Holmes is a member of the Industrial Power Converter and the IndustrialDrive Committees of the IEEE Industrial Applications Society, and has held anumber of positions on the Adcom of the IEEE Power Electronics Society overmany years.

Weixiang Shen (S’00–M’02) received Ph.D. degreein electrical engineering from the University of HongKong, Hong Kong, China, in 2002.

From 2002 to 2003, He was a Lecturer in NgeeAnn Polytechnic, Singapore. From 2003 to 2008, hewas a Lecturer and then a Senior Lecturer in theSchool of Engineering, Monash University , SubangJaya, Malaysia. He then was a Research Fellow forone year in the School of Electrical and Electron-ics Engineering, Nanyang Technological University,Singapore. He is currently an Associate Professor of

electrical engineering in the Faculty of Science, Engineering, and Technology,Swinburne University of Technology, Melbourne, Australia. His research inter-ests focus on electric vehicles, renewable energy, and power systems.

Qunjing Wang (M’13) was born in Bengbu, Anhui,China, in1960. He received the Ph.D. degree in elec-trical engineering from the Department of PrecisionMachinery and Precision Instrumentation, Universityof Science Technology, Hefei, China, in 1998.

From 1983 to 2007, he was with the Hefei Uni-versity of Technology, Hefei, China. Since 2007, hehas been a Professor and a Vice-President at AnhuiUniversity, Hefei, China. And he serves as a ResearchChair Professor in the National Engineering Labora-tory of Energy-saving Motor and Control Technique,

Anhui University, China, Power Quality Engineering Research Center of ChinaMinistry of Education, Anhui University, Provincial Collaborative InnovationCenter of Industrial Energy-saving and Power Quality Control, Anhui Univer-sity, China, and Energy-saving Research Institute, Hefei University of Technol-ogy. His research interests include motor and drive, converter technology, powerquality, and micro grid.

Dr. Wang is the General Chairman of the 11th IEEE Conference on IndustrialElectronics and Applications.


Fanglin Luo (M’84–SM’95) received the B.Sc. de-gree, First Class with Honors (magna cum laude),in radio-electronic physics from Sichuan University,Chengdu, China, in 1968, and the Ph.D. degree inelectrical engineering and computer science fromCambridge University, England, U.K., in 1986.

He is a Professor at Anhui University (AHU),HeFei, China and the Director of the Research In-stitute of Renewable Energy and Power Electronics,AHU. He also holds a joint professional position atNanyang Technological University (NTU), Nanyang,

Singapore . He was an Associate Professor in the School of Electrical and Elec-tronic engineering, NTU during 1995–2012. After his graduation from SichuanUniversity, He joined Chinese Automation Research Institute of Metallurgy,Beijing, China, as a Senior Engineer. He then went to Entreprises Saunier Du-val, Paris, France as a Project Engineer in 1981–1982. He was with HockingNDT Ltd, Allen-Bradley IAP Ltd., and Simplatroll Ltd. in England as a Se-nior Engineer after he receiving the Ph. D. degree. He has published 18 booksand more than 300 technical papers in IEE/IET Proceedings and IEEE Trans-actions, and various International Conferences. His research interests includepower electronics, dc & ac motor drives with computerized artificial intelligentcontrol, digital signal processing, advanced power electronics: ac/dc & dc/dc& ac/ac converters and dc/ac inverters, distributed generation, micro grid andsmart grid (3G), renewable energy systems and electrical vehicle.

He is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER

ELECTRONICS and the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. Heis also the International Editor of International journal (Advanced Technology ofElectrical Engineering and Energy), and was the Chief Editor of Internationaljournal (Power Supply Technologies and Applications) in 1998–2003. He is theGeneral Chairman of the First IEEE Conference on Industrial Electronics andApplications and the Third IEEE Conference on Industrial Electronics and Ap-plications. He is a Fellow of Cambridge Philosophical Society.

Nian Liu (S’06-M’11) received the B.S. and M.S.degrees in electric engineering from Xiangtan Uni-versity, Hunan, China, in 2003 and 2006, respec-tively, and the Ph.D. degree in electrical engineeringfrom North China Electric Power University, Beijing,China, in 2009.

Currently, he is an Associate Professor in theSchool of Electrical and Electronic Engineering,North China Electric Power University, Beijing,China. His research interests include demand-side en-ergy management, microgrids, electric vehicles, and

cyber security of smart grid.

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