An implementation of double-frequency oscillation cancellation technique in control of DSTATCOM

An implementation of double-frequency oscillation cancellationtechnique in control of DSTATCOM

Bhim Singh1, Sabha Raj Arya1* and Pankajkumar Verma2

1Department of Electrical Engineering, Indian Institute of Technology - Delhi, New Delhi-110016, India2Department of Civil Engineering, Indian Institute of Technology-Delhi, New Delhi-110016, India

SUMMARY

This paper presents an implementation of double-frequency oscillation cancellation (DFOC) technique inphase locked loop less synchronous reference frame theory for control of a distribution static compensator(DSTATCOM). This control algorithm on DSTATCOM is used for improvement of power quality underlinear and nonlinear loads. The DFOC technique is used for cancellation of double-frequency componentfrom the load fundamental active and reactive power components of currents which are used for derivingthe reference supply currents without time delay. A DSTATCOM is developed, and its performance is testedusing a digital signal processor. The performance of DSTATCOM is found satisfactory for different types ofloads in transient and steady state conditions. Copyright © 2013 John Wiley & Sons, Ltd.

key words: DFOC; DSTATCOM; VSC; PFC; unit templates

1. INTRODUCTION

Current waveform distortion and voltage dip are increasing attention because of awareness on power qualityin different power levels of consumer loads [1]. Today, control processes of various manufacturing, food pro-cessing sectors are based on computerized equipment with several relay arrangement which aremost sensitiveto AC mains interruptions and disturbances [2]. Compensating type custom power devices such as distribu-tion static compensators (DSTATCOMs) can be applied as reactive power compensator for compensation ofunbalanced loads, harmonics elimination and voltage regulation [3]. Several power quality standards such asIEEE 519–1992, IEEE 1100–1999, IEEE 1159–1995, IEC 61000-3-2 and IEC 61000-3-4 are used as guide-lines for power quality analysis at the point of common coupling (PCC) [4–6]. Performance and utilization ofDSTATCOM depend upon its design, control algorithm used for derivation of reference currents and gatingpulse generation [7–9]. Some of the field applications of this device are reported in the literature [10–13].These applications include voltage dip compensation in grid-connected sensitive loads, reactive powercompensation in micro grid aircraft power distribution to improve its quality and reliability in non powerfrequency supply voltage with application of digital signal processor (DSP) and fast control algorithms.Many control algorithms are available in time and frequency domain for estimation of reference current

from distorted load currents. Some of the time domain control algorithms are based on P–Q theory [14],Adaline control algorithm [15], concept of sensor less control algorithm [16], synchronous-reference-frame-based control [17] and instantaneous phase angle detection algorithm [18] under unbalanced ACmains, etc. Various modifications in synchronous reference frame (SRF)-based control algorithm are reportedin the literature [19–22]. Benhabib and Saadate [19] have reported the application of SRF theory with phaselocked loop (PLL) in three-phase system and compared with other control algorithm. Sadigh and Barakati[20] have described a new control algorithm based on the SRF principle and used for active filtering. Silvaet al. [21] have used digital PLL scheme for three-phase system usingmodified SRF.Miranda et al. [22] haveexplained the DQ SRF theory for single-phase application. This control method consists of transformation anorthogonal pair composed by the actual single-phase input current and a fictitious current, from a stationary to

*Correspondence to: Sabha Raj Ary, Department of Electrical Engineering, Indian Institute of Technology Delhi, India.†E-mail: [email protected]

Copyright © 2013 John Wiley & Sons, Ltd.

INTERNATIONAL TRANSACTIONS ON ELECTRICAL ENERGY SYSTEMSInt. Trans. Electr. Energ. Syst. 2014; 24:796–807Published online 2 April 2013 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/etep.1735

a rotating frame. Shunt active compensator using SRF theory are described using proportional-integral (PI)controller in direct and quadrature axis components for improvement of performance for specific processrequirements [23]. A new modification, based on theoretical analysis of SRF with double-frequencyoscillation cancellation (DFOC), is reported by Golestan et al. [24,25] only in single-phase system.In this paper, a DFOC technique in SRF control algorithm is implemented first time for three-phase

DSTATCOM without application of PLL. It is used for estimation of reference supply currents forpower factor correction (PFC) and zero voltage regulation (ZVR) modes along with load balancingand harmonic elimination. This technique is able to cancel double-frequency oscillation by injectingdouble-frequency signals with same amplitude and opposite phase angle in to d-q components withoutdegrading the stability and transient performance of system. Stable and fast transient response,accuracy in reference currents estimation, frequency-independent operation and simple structure areobserved the main advantages of this modification in the control of DSTATCOM.

2. STRUCTURE OF DSTATCOM

A schematic diagram of a three-phase DSTATCOM is shown in Figure 1where anACmains is feeding three-phase linear/nonlinear loads. Main parts of DSTATCOM are the voltage source converter (VSC), interfacinginductors (Lf), and series connected Rf –Cf circuit as a ripple filter. A ripple filter is used for filtering the high-frequency switching noise of VSC at PCC. Required compensating currents (iCa, iCb, iCc) are injected by theDSTATCOM for power quality improvement. For a considered load of 30 kVA (0.8 lagging), theDSTATCOMdata are given in Appendix ‘A’. The rating of the VSC for the reactive power compensation/harmonicselimination is found to be 20 kVA (approximately 10% higher than reactive current from rated value).

3. CONTROL ALGORITHM

Figure 2 shows the block diagram of a control algorithm-based DFOC with modified SRF theory forestimation of reference supply currents. Three-phase PCC voltages (vsa, vsb, vsc), distorted load currents(iLa, iLb, iLc) and DC link voltage (vdc) of DSTATCOM are sensed as input signals in this control algorithm.Distorted three-phase load currents are converted into d-q axis using a-b-c to d-q-0 transformation as

iLdiLqiLo

24

35 ¼

ffiffiffi23

r uqa uqb uqcupa upb upc

1=ffiffiffi2

p1=

ffiffiffi2

p1=

ffiffiffi2

p

24

35 iLa

iLbiLc

24

35 (1)

isa

vab

Isolation and amplification circuit

d-SPACE (1104) DSP

PWM current controller

Lf

vdc

ADC

isb

vbc

vdc

iLa iLb iLc

isa

Rs

Ls

vsa

vsb

vsc

bc

Linear/ Nonlinear

loads

Ripple Filter

isbisc

VSC

iCa

iCb

iCc

iLaiLbiLc

AC Mains

Cf

Rf

PCC

isc

(isa*,isb*,isc*)

a

Figure 1. Schematic diagram of DSTATCOM.

BHIM SINGH, SABHA RAJ ARYA AND PANKAJKUMAR VERMA 797

Copyright © 2013 John Wiley & Sons, Ltd. Int. Trans. Electr. Energ. Syst. 2014; 24:796–807DOI: 10.1002/etep

In-phase and quadrature unit templates of three-phase AC mains voltages are used as upa, upb, upcand uqa, uqb, uqc, respectively, in Equation (1). These components are estimated after dividing respectivephase voltage with amplitude of three-phase PCC voltages (vt). The amplitude of PCC voltages andin-phase unit templates are computed as [9].Amplitude of PCC voltage is as

vt ¼ 2 vsa2 þ vsb

2 þ vsc2

� �=3

� �1=2(2)

The unit templates in phase of PCC voltages as

upa ¼ vsavt

; upb ¼ vsbvt

; upc ¼ vscvt

(3)

The quadrature unit templates are estimated as

uqa ¼�upb þ upc� �

ffiffiffi3

p ; uqb ¼3upa þ upb � upc� �

2ffiffiffi3

p ; uqc ¼�3upa þ upb � upc� �

2ffiffiffi3

p (4)

The d-q components (iLd, iLq) are then passed through DFOC block to extract constant DC compo-nents of idc(n) and iqc(n) at n

th sampling instant. It is used for separation of double-frequency oscillationcomponent from iLd and iLq. Feedback signals of DFOC idc(n�1) and iqc(n�1) are presented (n�1)th

instant of idc and iqc.Figure 3 shows a block diagram of DFOC. It is applied for elimination of double-frequency ripple

ILm cos 2ot � θð Þ and ILm sin 2ot � θð Þ in load currents iLd and iLq components. Peak magnitude ofload current and phase angle of fundamental components are represented as iLm and θ, respectively.For mathematical analysis, expressions for iLd and iLq components are considered as [24],

iLd ¼ ILm cosθ� ILm cosθ cos2ot � ILm sinθ sin2ot (5)

vdc*

d- q

a-b-c

LPF

LPF

+

PI Controller

PI Controller vdc

-

-+ vt

*

iLa

iLb

iLc

++

-+

a-b-c/d-q Transformation d- q / a- b- cTransformation

a-b-c

d- qiLd

iLq

icd

icq

isd*

i sq*

isa*

isb*

isc*

DFOC

DFOC

idc

iqc

vt

Inphase and quadratue voltage unit templates

vsa

vsb

vsc

upa upb upcuqa uqb uqc

Figure 2. Estimation of reference supply currents using DFOC in SRF control algorithm.

iLd

iLq

idc(n)

2

sincos

++

++

++

-+

X X

XX

iqc(n)

idc(n-1) iqc(n-1)

LPF

LPF

ˆ t

Figure 3. Block diagram of DFOC technique.

B. SINGH ET AL.798


iLq ¼ ILm sinθþ ILm sinθ cos2ot � ILm cosθ sin2ot (6)

FromEquations (5) and (6), it is observed that the amplitude of double-frequency oscillation terms iLp andiLq are directly related to average values of iLp and iLq. Hence, undesirable oscillation due to double-frequency components can be easily cancelled out by injecting double-frequency components with sameamplitude and opposite phase angles in load current iLp and iLq components. In DFOC block, o denotesthe estimated frequency using in-phase and quadrature unit templates, and it is considered that supply fre-quency and estimated frequency both are equal. Using Laplace transformation, idc and iqc are given as [25],

idc sð Þ ¼ oc

sþ ocL iLd þ idc cos2ot þ iqc sin2ot� �

(7)

iqc sð Þ ¼ oc

sþ ocL iLq þ idc sin2ot þ iqc cos2ot� �

(8)

where ‘L’ and ‘oc’ are the notation of Laplace transformation and cut off frequency of low pass filter,respectively.Equations (7) and (8) can be rearranged and converted in to time domain as

i:

dc tð Þi:

qc tð Þ

¼ occos2ot � 1 sin2otsin2ot � cos2ot � 1

idc tð Þiqc tð Þ

þ oc 0

0 oc

iLd tð ÞiLq tð Þ

(9)

Equations (5), (6) and (9) can be rearranged as

i:

dc tð Þi:

qc tð Þ

¼ occos2ot � 1 sin2otsin2ot � cos2ot � 1

idc tð Þ � ILm cosθiqc tð Þ � ILm sinθ

(10)

Equation (10) is a linear time variant systemwhich has two input and two outputs. ‘idc’ and ‘iqc’ are estimatedafter solving Equation (10) where fluctuating terms decrease to zero with time constant of 1/oc and convergeto ILm cosθ and ILm sinθ, respectively, and provide perfect cancellation of double-frequency components.Reference (vdc*) and sensed (vdc) DC link voltages of VSC of DSTATCOM are fed to a PI controller

which output signal (icd) is required for maintaining DC link voltage of the DSTATCOM. The amplitudeof direct axis component of the reference supply current is estimated by an addition of output of DC linkvoltage PI controller (icd) and direct axis component of load currents (idc) as,

isd� ¼ icd þ idc (11)

Similarly, another PI controller is used regulate the PCC voltage (vt). The output signal of AC busvoltage PI controller is considered icq. The amplitude of quadrature component of reference supplycurrent (isq*) is calculated by difference of output of the PCC voltage PI controller (icq) and quadraturecomponent of load currents (iqc) as,

isq� ¼ icq � iqc (12)

The resultant reference supply d-q currents (isd*, isq*) are converted into the reference supply currentsin a-b-c frame (isa*, isb*, isc*) using a d-q-0 to a-b-c transformation as

isa�isb�isc�

24

35 ¼

ffiffiffi23

r upa uqa1ffiffiffi2

p

upb uqb1ffiffiffi2

p

upc uqc1ffiffiffi2

p

26666664

37777775

isd�isq�io�

24

35 (13)

The sensed supply currents (isa, isb, isc) and these reference supply currents (isa*, isb

*, isc*) are com-

pared, and each phase current error is amplified using PI current controller, and outputs of PI currentcontrollers are compared with a carrier signal to generate the gating signals for insulated gate bipolartransistors of VSC of DSTATCOM.

4. SIMULATION RESULTS

The performance of DSTATCOMusing DFOC technique in PLL-less SRF control algorithm is simulatedusing MATLAB for PFC and ZVR modes of operation at linear and nonlinear loads. Its performance isanalyzed for linear and nonlinear loads.



4.1. Performance of DSTATCOM in PFC mode

The dynamic performance of a three-phase VSC-based DSTATCOM for PFC mode at linear load isshown in Figure 4. The performance indices are as phase voltages at PCC (vs), balanced supplycurrents (is), load currents (iLa, iLb, iLc), compensator currents (iCa, iCb, iCc) and DC link voltage (vdc)which are shown under a varying load (at t= 1.25 s to 1.35 s) conditions. It shows the satisfactoryoperation of DSTATCOM for reactive power compensation and load balancing.Similarly, a diode bridge rectifier as a nonlinear load is connected to the AC mains. The dynamic

performance of DSTATCOM (with PCC voltages, supply currents, load currents, compensatingcurrents and DC link voltage) and waveforms with harmonic spectra of phase ‘a’ voltage at PCC(vsa), supply current (isa) and load current (iLa) are shown in Figures 5 and 6 (a–c), respectively. Totalharmonic distortion (THD) of the phase ‘a’ at PCC voltage, supply current and load current are 2.97%,

Figure 4. Dynamic performance of DSTATCOM under varying linear loads in PFC mode.

Figure 5. Dynamic performance of DSTATCOM under varying nonlinear loads in PFC mode.

B. SINGH ET AL.800


2.45% and 25.07%, respectively. It is observed that the DSTATCOM is able to perform the functionsof load balancing, harmonic elimination and PFC.

4.2. Performance of DSTATCOM in ZVR mode

In ZVR mode, the amplitude of PCC voltage is regulated to the reference amplitude by injectingthe required leading reactive power components. Figure 7 shows the dynamic performance of theDSTATCOM used for voltage regulation and load balancing under linear loads (at t=1.25 s to 1.35 s).Performance indices such as PCC phase voltages (vs), balanced supply currents (is), load currents(iLa, iLb, iLc), compensator currents (iCa, iCb, iCc), amplitude of voltages at PCC (vt) and DC link voltage(vdc) are shown under linear loads. Its performance is also studied under nonlinear loads. The dynamicperformance of DSTATCOM in terms of waveforms and harmonics spectra of phase ‘a’ voltage atPCC (vsa), supply current (isa) and load current (iLa) are shown in Figures 8 and 9 (a–c), respectively.THDs of the phase ‘a’ at PCC voltage, supply current and load current are 3.98%, 3.25% and 25.15%,respectively. Three-phase PCC voltages are regulated to desired value. Amplitude of three-phase PCC

(a) (b) (c)

Figure 6. Waveforms and harmonic spectra of (a) PCC voltage of phase ‘a’, (b) supply current of phase ‘a’and (c) load current of phase ‘a’ in PFC mode.

Figure 7. Dynamic performance of DSTATCOM under varying linear loads in ZVR mode.



voltage is regulated from 335.87V to 338.84 V and 332.9V to 338.6V at linear and nonlinear loads,respectively. Table 1 shows the summarized results demonstrating the performance of three-phaseDSTATCOM for harmonics elimination, reactive power compensation and load balancing in PFCand ZVR modes.

5. EXPERIMENTAL RESULTS

A prototype of DSTATCOM is developed using a VSC, interfacing inductors, isolation and amplificationcircuits. ABB make voltage sensors (EM010 BB) and current sensors (EL50P1 BB) are used for sensingthe PCC voltages, supply currents, load currents and DC link voltage. A DFOC technique with PLL-lessSRF control is realized using a DSP (dSPACE-1104). For recording the tests results, a Fluke (43B) poweranalyzer and four channel Agilent made digital oscilloscope scope (DSO-6014A) are used. Hardwareimplementation data are given in Appendix ‘B’. During these tests, DC link voltage of DSTATCOM isregulated at 300V, and test results are recorded in balanced and unbalanced operations in steady stateand transient conditions as discussed below.

Figure 8. Dynamic performance of DSTATCOM under varying nonlinear loads in ZVR mode.

(a) (b) (c)

Figure 9. Waveforms and harmonic spectra of (a) PCC voltage of phase ‘a’, (b) supply current of phase and‘a’ (c) load current of phase ‘a’ in ZVR mode.

B. SINGH ET AL.802


5.1. Performance of DSTATCOM at nonlinear loads

Figure 10 (a–c), (d) and (e–f) shows the waveform of three-phase supply currents(isa, isb, isc) with PCCvoltage (vab), harmonic spectrum of phase a source current (isa), waveform and harmonic spectrum ofphase ‘a’ load current (iLa) and under nonlinear loads. In Figure 10 (d) and (f), THD of phase ‘a’supply current and load current are observed of the order of 4.2% and 25.8%, respectively. Figure 10(g–h) shows the harmonic spectrum of PCC phase ‘a’ voltage and waveform of phase ‘a’ DSTATCOM

Table I. Performance of DSTATCOM.

Operating mode Performance parameters Linear loadNonlinear load (3 j uncontrolrectifier with R and L load)

PFC mode PCC voltage (V), %THD 237.5V, 1.07% 235.39V, 2.97%Supply current (A), %THD 33.14A, 2.57% 59.31A, 2.45%Load current (A), %THD 41.37A, 0.17% 60.11A, 25.07%

ZVR mode PCC voltage (V), %THD 239.4V, 1.31% 239.42V, 3.98%Supply current (A), % THD 34.1A, 3.39, % 62.09A, 3.25%Load current (A), % THD 41.71A, 0.23% 60.94A, 25.15%DC link voltage (V) 700V 700V

(a) (b) (c)

(d) (e) (f)

(g) (h)

Figure 10. Performance of DSTATCOM under nonlinear loads. (a–c) isa, isb and isc with respect to vab.(d) Harmonic spectra of isa. (e–f) Waveform and harmonic spectrum of iLa. (g) Harmonic spectrum of vsa.

(h) iCa.



current (iCa). These results show satisfactory performance of the control algorithm used in DSTATCOMfor harmonics elimination under nonlinear loads.

5.2. Load balancing using DSTATCOM

Figure 11 (a–c), (d–f) and (g–i) shows the waveform of three-phase supply currents (isa, isb, isc), loadcurrents (iLa, iLb, iLc) and DSTATCOM currents (iCa, iCb, iCc) with respect to PCC voltage underunbalanced nonlinear loads. Unbalanced load condition is created by removal of load in phase ‘c’. Itshows the balanced supply currents when load currents are unbalanced in nature. These resultsdemonstrate the satisfactory performance of control algorithm under load balancing operation.

5.3. Dynamic performance of DSTATCOM

Figure 12 (a), (b) and (c) shows the waveform of supply currents (isa, isb, isc), load currents (iLa, iLb, iLc)and DSTATCOM currents (iCa, iCb, iCc) with respect to PCC line voltages (vab) under unbalancednonlinear load. Unbalanced load condition can be observed after load removal. It is created by removalof load in phase ‘c’. Variation of supply current (isa), DSTATCOM current (iCa) and load current (iLa)are shown with DC link voltage (vdc) and PCC voltage (vab) in Figure 12 (d, e). It shows the balancedsupply currents when load currents are unbalanced in nature. These results demonstrate the satisfactoryand fast response of control algorithm under unbalanced load in dynamic condition.

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

Figure 11. Load balancing performance of DSTATCOM at unbalanced nonlinear loads. (a–c) isa, isa and isawith vab. (d–f) iLa, iLb and iLc. (g–i) iCa, iCb and iCc.

B. SINGH ET AL.804


(a) Ch.1-500V/div, Ch. 2, 3 and 4 -20A/div,Time axis-10ms/div

(b) Ch.1-500V/div, Ch. 2, 3 and 4 -10A/div, Time axis-10ms/div

(c) Ch.1-500V/div, Ch. 2, 3 and 4 -10A/div , Time axis-10ms/div

(d) Ch.1-200V/div, Ch. 2, 3 and 4 -10A/div, Time axis-10ms/div

(e) Ch.1-500V/div, Ch. 2, 3 and 4 -10A/div, Time axis-10ms/div

iCb

iCa

iCc

isa

iCa

iLa

vdcvab

iLaisa

iLc

iLb

isc

isb

vabvab

Load removal

Load removal

vab

isa

iCa

iLaLoad removal

Load removal

Load removal

Figure 12. Dynamic performance of DSTATCOM during injection of phase ‘c’ in nonlinear loads. (a) isa,isa and isa with vab. (b) iLa, iLb and iLc with vab. (c) iCa, iCb and iCc with vab. (d) Variation of isa, iCa and iLa

with vdc. (e) Variation of isa, iCa and iLa with vab.



6. CONCLUSION

A three-phase DSTATCOM with proposed control algorithm has been implemented for compensationof three-phase linear and nonlinear loads. A DFOC in PLL-less synchronous reference theory-basedcontrol algorithm has been applied for estimation of reference supply currents for developed DSTAT-COM. Transient response has been improved after introducing DFOC technique in SRF controlalgorithm because it is effectively able to cancel the double-frequency oscillation components presentin load currents. The performance of DSTATCOM has been found quite satisfactory for power qualityimprovement in PFC and ZVR modes. The DC link voltage of the DSTATCOM has also beenregulated to desired value without any over shoot and under-shoot.

7. LIST OF SYMBOLS AND ABBREVIATIONS

’ Phases Secondθ Phase Angle of Fundamental ComponentAC Alternating CurrentDC Direct CurrentDFOC Double Frequency Oscillation CancellationIGBTs Insulate Gate Bipolar TransistorsPCC Point of Common CouplingPLL Phase Locked LoopPI Proportional-IntegralSRF Synchronous Reference FrameTHD Total Harmonic Distortion

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APPENDIX A

AC supply source: three phase, 415 V (L-L), 50Hz; Source impedance: Rs= 0.07 Ω, Ls = 2 mH; Load:(1) Linear: 30 kVA, 0.8 p.f. lagging (2) Nonlinear: Three-phase full bridge uncontrolled rectifier withR= 7Ω and L= 200mH; Ripple filter: Rf= 5 Ω, Cf= 10 mF; DC link capacitance: 8000mF; ReferenceDC link voltage: 700 V; Interfacing inductor (Lf) = 2.75mH; Gains of PI controller for DC linkvoltage: Kpd= 3.24, Kid = 0.05; Gains of voltage PI controller: Kpq= 3.4, Kiq =5.78, Cut-off frequencyof low filter used in DC link voltage: first order, 10 Hz, cut-off frequency of low filter used in AC busvoltage: first order, 10 Hz.

APPENDIX B

AC mains: three phase, 160 V (L-L), 50Hz; Nonlinear load: Three-phase full bridge uncontrolledrectifier with R= 20Ω, L= 150mH; DC link capacitance: 1650 mF; Reference DC link voltage: 300V; Interfacing inductor (Lf) = 2.5mH; Ripple filter: Rf = 5 Ω, Cf= 10 mF, sampling time (ts) = 45 ms;Cut-off frequency of low pass filter used in estimation of load active current amplitude of terminalvoltage: first order, 10 Hz, Cut-off frequency of low filter used in DC link voltage: first order, 10 Hz.



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An implementation of double-frequency oscillation cancellation technique in control of DSTATCOM