An Efficient Scan Tree Design for Test

Time Reduction

Boda NehruUnder the guidance of

Prof. Virendra SinghCo-guide

Prof. Shankar Balachandran

Outline

• Introduction• Full compatible scan tree architecture• Scan tree architecture with Scan Tree Mode & Single scan Mode• Scan tree architecture generation• Experimental Results• Conclusion• Reference

Introduction

• The full scan design is the most popular DfT technique and it is very largely used in integrated circuits (ICs) or in System on chip (SoC) cores

• Unfortunately, scan based architectures are expensive in test power consumption and in test application time.

• The number of clock cycles required to scan in/out the test data is equal to the product of the number of test patterns by the scan chain length

Introduction contd..

• The effectiveness of a scan tree architecture depends on the correlation between the test data of the different scan cells

• an optimal scan tree architecture for reducing the dependency.

• The idea is to use a dynamic reconfiguration during the test application to switch from a scan tree mode to a single scan mode

Optimal Construction of A Scan Tree

Incompatibility Graph

• For all the test sequences in which every test vector is presented in incompatibility graph.

• In which every scan flip-flap is represented by vertex

• The edge between vertices is formed if they are incompatible

Incompatibility graph

Rules to form coloring graph

• The vertex coloring problem is to find an assignment of the minimum number of colors, it is very time-consuming to find the optimum solution of the problem.

• In the proposed method, we solve the problem with a greedy algorithm, i.e., we assign colors to each vertex in order of edges incident on it.

• The vertices with the same color give groups of compatible scan flip-flops

Scan tree architecture with STM & SSM

Forming graph

Scan tree generation

• The first step is to compute the number of incompatibilities for each test pattern.

• The number of incompatibilities corresponds to the number of edges in the coloring graph.

• The second step consists in sorting the test sequence according to the number of incompatibilities

Scan tree generation contd..

• The last step reduces the test sequence by removing the equivalent test patterns

• Definition: a test pattern is equivalent to test pattern if they have the same incompatibility another

Scan tree generation contd..

Test pattern selection procedure

Experimental results

• # clock_cycles = ( (#• # is the number of test patterns applier in ST mode• is the length of the scan tree architecture• is the test sequence length and is the number of scan cells• For single scan chain, # is equal to 0• For full compatible scan tree, # is equivalent to .

` Experimental results contd..• The test shift time saving using the full compatible scan tree is equal

to 52.3% in average and to 78.9% at maximum in comparison with the single scan architecture.

• Scan tree architecture of (STM & SSM) method reaches 95.45% for s38584.

Experimental results contd..

Experimental results contd..

Conclusion

• Experimental results for benchmark circuits show that this method can reduce scan test shift time up to 95% of that for the single scan

• Future work is considering design constraints and reducing the scan tree generation complexity.

References

• k. Miyase and S. Kajihara, “Optimal Scan Tree Construction with Test Vector Modification for Test Compression”, IEEE Asian Test Symp., pp. 136-141, November 2003.• Y. Bonhomme, T. Yoneda ,H. Fujiwara, P. Girard Graduate School of

Information Science,Nara Institute of Science and Technology• A.R. Pandey and J. H. Patel, “Reconfiguration Technique for Reducing

Test Time and Test Data Volume in Illinois Scan Architecture Based Designs”, IEEE VLSI Test Symp., pp. 9-15, April 2002.• H. Yotsuyanagi, T. Kuchii, S. Nishikawa, M. Hashizume and K. Kinoshita,

“Reducing Scan Shifts using Folding Scan Trees”, IEEE Asian Test Symp., pp. 6-11, November 2003.

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